BR112015029930A2 - pares de imposição de ordem de instrução de instruções, processadores, métodos e sistemas - Google Patents
pares de imposição de ordem de instrução de instruções, processadores, métodos e sistemasInfo
- Publication number
- BR112015029930A2 BR112015029930A2 BR112015029930A BR112015029930A BR112015029930A2 BR 112015029930 A2 BR112015029930 A2 BR 112015029930A2 BR 112015029930 A BR112015029930 A BR 112015029930A BR 112015029930 A BR112015029930 A BR 112015029930A BR 112015029930 A2 BR112015029930 A2 BR 112015029930A2
- Authority
- BR
- Brazil
- Prior art keywords
- instruction
- order
- enforcement
- instructions
- processors
- Prior art date
Links
- 230000004913 activation Effects 0.000 abstract 2
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30003—Arrangements for executing specific machine instructions
- G06F9/30076—Arrangements for executing specific machine instructions to perform miscellaneous control operations, e.g. NOP
- G06F9/30079—Pipeline control instructions, e.g. multicycle NOP
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30003—Arrangements for executing specific machine instructions
- G06F9/30076—Arrangements for executing specific machine instructions to perform miscellaneous control operations, e.g. NOP
- G06F9/30087—Synchronisation or serialisation instructions
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3854—Instruction completion, e.g. retiring, committing or graduating
- G06F9/3856—Reordering of instructions, e.g. using queues or age tags
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3885—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units
- G06F9/3889—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units controlled by multiple instructions, e.g. MIMD, decoupled access or execute
- G06F9/3891—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units controlled by multiple instructions, e.g. MIMD, decoupled access or execute organised in groups of units sharing resources, e.g. clusters
Landscapes
- Engineering & Computer Science (AREA)
- Software Systems (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Advance Control (AREA)
- Executing Machine-Instructions (AREA)
Abstract
pares de imposição de ordem de instrução de instruções, processadores, métodos e sistemas trata-se de um processador de um aspecto que inclui uma unidade de busca de instrução para buscar um par de instruções de imposição de ordem de instrução. o par de instruções de imposição de ordem de instrução é parte de um conjunto de instrução do processador. o par de instruções de imposição de ordem de instrução inclui uma instrução de ativação e uma instrução de imposição. a instrução de ativação deve ocorrer antes da instrução de imposição em uma ordem de programa. o processador também inclui um módulo de imposição de ordem de instrução. o módulo de imposição de ordem de instrução, em resposta ao par das instruções de imposição de ordem de instrução, deve impedir que as instruções que ocorrem após a instrução de imposição na ordem de programa sejam processadas antes da instrução de ativação, em uma porção fora de ordem do processador. outros processadores também são revelados, como são vários métodos, sistemas e instruções.
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US13/931,544 US9323535B2 (en) | 2013-06-28 | 2013-06-28 | Instruction order enforcement pairs of instructions, processors, methods, and systems |
| US13/931,544 | 2013-06-28 | ||
| PCT/US2014/042153 WO2014209627A1 (en) | 2013-06-28 | 2014-06-12 | Instruction order enforcement pairs of instructions, processors, methods, and systems |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| BR112015029930A2 true BR112015029930A2 (pt) | 2017-07-25 |
| BR112015029930B1 BR112015029930B1 (pt) | 2022-01-11 |
Family
ID=52116846
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| BR112015029930-0A BR112015029930B1 (pt) | 2013-06-28 | 2014-06-12 | Pares de imposição de ordem de instrução de instruções, processadores, métodos e sistemas |
Country Status (8)
| Country | Link |
|---|---|
| US (1) | US9323535B2 (pt) |
| EP (1) | EP3014424B1 (pt) |
| KR (1) | KR101806279B1 (pt) |
| CN (1) | CN105247479B (pt) |
| BR (1) | BR112015029930B1 (pt) |
| RU (1) | RU2630745C2 (pt) |
| TW (1) | TWI515653B (pt) |
| WO (1) | WO2014209627A1 (pt) |
Families Citing this family (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9323535B2 (en) | 2013-06-28 | 2016-04-26 | Intel Corporation | Instruction order enforcement pairs of instructions, processors, methods, and systems |
| US10152452B2 (en) * | 2015-05-29 | 2018-12-11 | Intel Corporation | Source operand read suppression for graphics processors |
| US10108417B2 (en) | 2015-08-14 | 2018-10-23 | Qualcomm Incorporated | Storing narrow produced values for instruction operands directly in a register map in an out-of-order processor |
| US9830150B2 (en) | 2015-12-04 | 2017-11-28 | Google Llc | Multi-functional execution lane for image processor |
| US10761849B2 (en) * | 2016-09-22 | 2020-09-01 | Intel Corporation | Processors, methods, systems, and instruction conversion modules for instructions with compact instruction encodings due to use of context of a prior instruction |
| GB2563589B (en) * | 2017-06-16 | 2019-06-12 | Imagination Tech Ltd | Scheduling tasks |
| IT202100002642A1 (it) | 2021-02-05 | 2022-08-05 | Sk Hynix Inc | Metodo implementato da un microcontrollore per gestire una istruzione nop e microcontrollore corrispondente |
Family Cites Families (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5941983A (en) * | 1997-06-24 | 1999-08-24 | Hewlett-Packard Company | Out-of-order execution using encoded dependencies between instructions in queues to determine stall values that control issurance of instructions from the queues |
| US6671795B1 (en) * | 2000-01-21 | 2003-12-30 | Intel Corporation | Method and apparatus for pausing execution in a processor or the like |
| US6880073B2 (en) | 2000-12-28 | 2005-04-12 | International Business Machines Corporation | Speculative execution of instructions and processes before completion of preceding barrier operations |
| US7398376B2 (en) * | 2001-03-23 | 2008-07-08 | International Business Machines Corporation | Instructions for ordering execution in pipelined processes |
| US20050066151A1 (en) * | 2003-09-19 | 2005-03-24 | Sailesh Kottapalli | Method and apparatus for handling predicated instructions in an out-of-order processor |
| US7426612B2 (en) | 2004-06-30 | 2008-09-16 | Intel Corporation | Methods and apparatus for enforcing instruction-cache coherence |
| US20090164758A1 (en) * | 2007-12-20 | 2009-06-25 | Haertel Michael J | System and Method for Performing Locked Operations |
| US9058179B2 (en) * | 2010-11-12 | 2015-06-16 | Arm Limited | Retirement serialisation of status register access operations |
| CN102541511B (zh) | 2010-12-30 | 2015-07-08 | 世意法（北京）半导体研发有限责任公司 | 用于可乱序执行指令的处理器的流水线排空 |
| US9323535B2 (en) | 2013-06-28 | 2016-04-26 | Intel Corporation | Instruction order enforcement pairs of instructions, processors, methods, and systems |
-
2013
- 2013-06-28 US US13/931,544 patent/US9323535B2/en active Active
-
2014
- 2014-06-12 WO PCT/US2014/042153 patent/WO2014209627A1/en active Application Filing
- 2014-06-12 EP EP14818771.9A patent/EP3014424B1/en active Active
- 2014-06-12 BR BR112015029930-0A patent/BR112015029930B1/pt not_active IP Right Cessation
- 2014-06-12 RU RU2015151117A patent/RU2630745C2/ru not_active IP Right Cessation
- 2014-06-12 KR KR1020157031073A patent/KR101806279B1/ko active IP Right Grant
- 2014-06-12 CN CN201480030660.2A patent/CN105247479B/zh active Active
- 2014-06-23 TW TW103121587A patent/TWI515653B/zh not_active IP Right Cessation
Also Published As
| Publication number | Publication date |
|---|---|
| RU2015151117A (ru) | 2017-06-01 |
| EP3014424A1 (en) | 2016-05-04 |
| CN105247479B (zh) | 2018-01-09 |
| BR112015029930B1 (pt) | 2022-01-11 |
| RU2630745C2 (ru) | 2017-09-12 |
| CN105247479A (zh) | 2016-01-13 |
| TWI515653B (zh) | 2016-01-01 |
| KR20150138306A (ko) | 2015-12-09 |
| KR101806279B1 (ko) | 2017-12-07 |
| TW201510861A (zh) | 2015-03-16 |
| WO2014209627A1 (en) | 2014-12-31 |
| EP3014424B1 (en) | 2019-11-27 |
| US9323535B2 (en) | 2016-04-26 |
| EP3014424A4 (en) | 2017-03-01 |
| US20150006851A1 (en) | 2015-01-01 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| B06U | Preliminary requirement: requests with searches performed by other patent offices: procedure suspended [chapter 6.21 patent gazette] | ||
| B350 | Update of information on the portal [chapter 15.35 patent gazette] | ||
| B09A | Decision: intention to grant [chapter 9.1 patent gazette] | ||
| B16A | Patent or certificate of addition of invention granted [chapter 16.1 patent gazette] |
Free format text: PRAZO DE VALIDADE: 20 (VINTE) ANOS CONTADOS A PARTIR DE 12/06/2014, OBSERVADAS AS CONDICOES LEGAIS. |
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| B21F | Lapse acc. art. 78, item iv - on non-payment of the annual fees in time |
Free format text: REFERENTE A 9A ANUIDADE. |
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| B24J | Lapse because of non-payment of annual fees (definitively: art 78 iv lpi, resolution 113/2013 art. 12) |
Free format text: EM VIRTUDE DA EXTINCAO PUBLICADA NA RPI 2726 DE 04-04-2023 E CONSIDERANDO AUSENCIA DE MANIFESTACAO DENTRO DOS PRAZOS LEGAIS, INFORMO QUE CABE SER MANTIDA A EXTINCAO DA PATENTE E SEUS CERTIFICADOS, CONFORME O DISPOSTO NO ARTIGO 12, DA RESOLUCAO 113/2013. |