BR112012017426A2 - processo de otimização de memória de acesso, quando da recuperação de execução de uma aplicação em um microprocessador, compreendendo diversos núcleos lógicos e programa de computador, a fim de implementar o tal processo - Google Patents

processo de otimização de memória de acesso, quando da recuperação de execução de uma aplicação em um microprocessador, compreendendo diversos núcleos lógicos e programa de computador, a fim de implementar o tal processo

Info

Publication number
BR112012017426A2
BR112012017426A2 BR112012017426A BR112012017426A BR112012017426A2 BR 112012017426 A2 BR112012017426 A2 BR 112012017426A2 BR 112012017426 A BR112012017426 A BR 112012017426A BR 112012017426 A BR112012017426 A BR 112012017426A BR 112012017426 A2 BR112012017426 A2 BR 112012017426A2
Authority
BR
Brazil
Prior art keywords
execution
application
memory
microprocessor
retrieving
Prior art date
Application number
BR112012017426A
Other languages
English (en)
Inventor
Benoît Welterlen
Philippe Couvee
Yann Kalemkarian
Original Assignee
Bull Sas
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Bull Sas filed Critical Bull Sas
Publication of BR112012017426A2 publication Critical patent/BR112012017426A2/pt

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/50—Allocation of resources, e.g. of the central processing unit [CPU]
    • G06F9/5005—Allocation of resources, e.g. of the central processing unit [CPU] to service a request
    • G06F9/5011—Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resources being hardware resources other than CPUs, Servers and Terminals
    • G06F9/5016—Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resources being hardware resources other than CPUs, Servers and Terminals the resource being the memory
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/461—Saving or restoring of program or task context
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0862—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with prefetch
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30098—Register arrangements
    • G06F9/3012—Organisation of register space, e.g. banked or distributed register file
    • G06F9/30123—Organisation of register space, e.g. banked or distributed register file according to context, e.g. thread buffers
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0842—Multiuser, multiprocessor or multiprocessing cache systems for multiprocessing or multitasking
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/60—Details of cache memory
    • G06F2212/6028—Prefetching based on hints or prefetch instructions
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F8/00—Arrangements for software engineering
    • G06F8/40—Transformation of program code
    • G06F8/41—Compilation
    • G06F8/44—Encoding
    • G06F8/443—Optimisation
    • G06F8/4441—Reducing the execution time required by the program code

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Memory System (AREA)

Abstract

processo de otimização de memória de acesso, quando da recuperação de execução de uma aplicação em um microprocessador, compreendendo diversos núcleos lógicos e programa de computador, a fim de implementar o tal processo. a invenção tem notadamente por objetivo a otimização de acesso de memória, quando da retomada de execução de uma aplicação principal, em um microprocessador compreendendo diversos núcleos lógicos e permitindo a execução simultânea de pelo menos dois processos em um ambiente compreendendo uma memória compartilhada e organizada de modo hierárquica compreendendo as partes alta e baixa, de um dado e, sendo copiado da parte baixa à parte alta para ser tartada pela aplicação. o computador é adaptado a interromper a execução da aplicação principal. quando uma interrupção da execução desta aplicação, uma referência a um dado memorizado em uma parte alta da memória é memorizada, este dado devendo ser utilizado para permitir a execução da aplicação. após uma programação de uma retomada de execução da aplicação e antes da retomada, este dado é acessado em uma parte baixa da memória conforme a referência para ser memorizado em uma parte alta da memória.
BR112012017426A 2010-07-12 2011-07-07 processo de otimização de memória de acesso, quando da recuperação de execução de uma aplicação em um microprocessador, compreendendo diversos núcleos lógicos e programa de computador, a fim de implementar o tal processo BR112012017426A2 (pt)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR1055681A FR2962567B1 (fr) 2010-07-12 2010-07-12 Procede d'optimisation d'acces memoire, lors de la reprise d'execution d'une application, dans un microprocesseur comprenant plusieurs coeurs logiques et programme d'ordinateur mettant en oeuvre un tel procede
PCT/FR2011/051616 WO2012007675A1 (fr) 2010-07-12 2011-07-07 Procede d'optimisation d'acces memoire, lors de la reprise d'execution d'une application, dans un microprocesseur comprenant plusieurs coeurs logiques et programme d'ordinateur mettant en oeuvre un tel procede

Publications (1)

Publication Number Publication Date
BR112012017426A2 true BR112012017426A2 (pt) 2016-04-19

Family

ID=43639110

Family Applications (1)

Application Number Title Priority Date Filing Date
BR112012017426A BR112012017426A2 (pt) 2010-07-12 2011-07-07 processo de otimização de memória de acesso, quando da recuperação de execução de uma aplicação em um microprocessador, compreendendo diversos núcleos lógicos e programa de computador, a fim de implementar o tal processo

Country Status (6)

Country Link
US (2) US10025633B2 (pt)
EP (1) EP2593872B1 (pt)
JP (1) JP2013534670A (pt)
BR (1) BR112012017426A2 (pt)
FR (1) FR2962567B1 (pt)
WO (1) WO2012007675A1 (pt)

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* Cited by examiner, † Cited by third party
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US9684685B2 (en) 2013-10-24 2017-06-20 Sap Se Using message-passing with procedural code in a database kernel
US9600551B2 (en) 2013-10-24 2017-03-21 Sap Se Coexistence of message-passing-like algorithms and procedural coding
FR3054902B1 (fr) * 2016-08-04 2019-06-21 Thales Procede et dispositif de distribution de partitions sur un processeur multi-coeurs
US10824481B2 (en) * 2018-11-13 2020-11-03 International Business Machines Corporation Partial synchronization between compute tasks based on threshold specification in a computing system

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US4761783A (en) * 1986-10-17 1988-08-02 Christensen Harold F Apparatus and method for reporting occurrences of errors in signals stored in a data processor
GB2234613B (en) * 1989-08-03 1993-07-07 Sun Microsystems Inc Method and apparatus for switching context of state elements in a microprocessor
US6026471A (en) 1996-11-19 2000-02-15 International Business Machines Corporation Anticipating cache memory loader and method
EP0856798B1 (en) * 1997-01-30 2004-09-29 STMicroelectronics Limited A cache system
TW405090B (en) * 1997-04-04 2000-09-11 Ibm Predictive cache loading by program address discontinuity history
US8234477B2 (en) * 1998-07-31 2012-07-31 Kom Networks, Inc. Method and system for providing restricted access to a storage medium
US6420903B1 (en) * 2000-08-14 2002-07-16 Sun Microsystems, Inc. High speed multiple-bit flip-flop
CA2427354A1 (en) * 2000-10-31 2002-08-01 Michael Philip Kaufman System and method for generating automatic user interface for arbitrarily complex or large databases
US20030154349A1 (en) * 2002-01-24 2003-08-14 Berg Stefan G. Program-directed cache prefetching for media processors
JP2004157636A (ja) * 2002-11-05 2004-06-03 Renesas Technology Corp データ処理装置
EP1599803B1 (en) * 2003-02-24 2009-09-30 Nxp B.V. Reducing cache trashing of certain pieces
US8266379B2 (en) * 2003-06-02 2012-09-11 Infineon Technologies Ag Multithreaded processor with multiple caches
US7328433B2 (en) * 2003-10-02 2008-02-05 Intel Corporation Methods and apparatus for reducing memory latency in a software application
US7617499B2 (en) * 2003-12-18 2009-11-10 International Business Machines Corporation Context switch instruction prefetching in multithreaded computer
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JP2008102623A (ja) * 2006-10-17 2008-05-01 Matsushita Electric Ind Co Ltd プロセッサ
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US9367462B2 (en) * 2009-12-29 2016-06-14 Empire Technology Development Llc Shared memories for energy efficient multi-core processors

Also Published As

Publication number Publication date
FR2962567A1 (fr) 2012-01-13
US10838768B2 (en) 2020-11-17
EP2593872B1 (fr) 2021-09-01
US20130111152A1 (en) 2013-05-02
US20190087227A1 (en) 2019-03-21
US10025633B2 (en) 2018-07-17
WO2012007675A1 (fr) 2012-01-19
FR2962567B1 (fr) 2013-04-26
EP2593872A1 (fr) 2013-05-22
JP2013534670A (ja) 2013-09-05

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B06F Objections, documents and/or translations needed after an examination request according [chapter 6.6 patent gazette]
B06U Preliminary requirement: requests with searches performed by other patent offices: procedure suspended [chapter 6.21 patent gazette]
B11B Dismissal acc. art. 36, par 1 of ipl - no reply within 90 days to fullfil the necessary requirements