BG49792A1 - Device for controlling the access to common resources of microprocessor z80 and personal computer - Google Patents

Device for controlling the access to common resources of microprocessor z80 and personal computer

Info

Publication number
BG49792A1
BG49792A1 BG9078889A BG9078889A BG49792A1 BG 49792 A1 BG49792 A1 BG 49792A1 BG 9078889 A BG9078889 A BG 9078889A BG 9078889 A BG9078889 A BG 9078889A BG 49792 A1 BG49792 A1 BG 49792A1
Authority
BG
Bulgaria
Prior art keywords
address
block
inputs
microprocessor
bus
Prior art date
Application number
BG9078889A
Inventor
Bozhidar T Kanev
Emil I Stoilov
Jordan D Kisaov
Todor D Stanchev
Dobrin Z Tsotskov
Stefan G Dinev
Dancho P Khristozov
Aleksandar K Aleksandrov
Original Assignee
Inst Tekhn Kib I Robotika Pri
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Inst Tekhn Kib I Robotika Pri filed Critical Inst Tekhn Kib I Robotika Pri
Priority to BG9078889A priority Critical patent/BG49792A1/en
Publication of BG49792A1 publication Critical patent/BG49792A1/en

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Abstract

The device is used in computing technology and ensures normal uploading of all address areas in the common resource of a dynamic memory with a capacity over 64 kbit. The device contains an arbitrator block (1) for access control to the common dynamic memory (2), control (9) and address (3) bus, input/output highway (4) of the personal computer (5), two address multiplexers (6 and 7) and a multiplexer address bus (8). The control outputs (10) of the microprocessor Z80 (11) are connected to the arbitrator block (1) and to inputs (29 and 30) of the modification block of a junior address bus (28), and the outputs (13, 14, 15, 16 and 17) of the arbitration block (1) are connected respectively to the inputs "reset" and "busreq" of the microprocessor Z80 (11), with the inputs "ras", "cas" and "wr" of the common dynamic memory (2), with the inputs "E" and "S" of the two address multiplexers (6 and 7) and with inputs of the modification block of the junior address bus (28). Output (12) of the arbitration block (1) is connected with the input line "RDY" for readiness of the input/output highway (4); two outputs (23 and 24) are connected to the data buffer (21) and one output (25) for address control - to the multiplexers (6 and 7). The address lines from A8 to A15 (26) of the microprocessor Z80 (11) are connected to the second address multiplexer (7), and address lines from A0 to A8 (27) - to the modification block of junior address bus (28), and the block outputs (31) are connected with the remaining address inputs of the second address multiplexer (7). Through the first bi-directional data bus (20) the microprocessor Z80 (11) is connected to the common dynamic memory (2) and to the data buffer (21), which is connected through a second data bus (22) to input/output highway (4).
BG9078889A 1989-12-28 1989-12-28 Device for controlling the access to common resources of microprocessor z80 and personal computer BG49792A1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
BG9078889A BG49792A1 (en) 1989-12-28 1989-12-28 Device for controlling the access to common resources of microprocessor z80 and personal computer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
BG9078889A BG49792A1 (en) 1989-12-28 1989-12-28 Device for controlling the access to common resources of microprocessor z80 and personal computer

Publications (1)

Publication Number Publication Date
BG49792A1 true BG49792A1 (en) 1992-02-14

Family

ID=3922608

Family Applications (1)

Application Number Title Priority Date Filing Date
BG9078889A BG49792A1 (en) 1989-12-28 1989-12-28 Device for controlling the access to common resources of microprocessor z80 and personal computer

Country Status (1)

Country Link
BG (1) BG49792A1 (en)

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