BE903898A - Circuit generateur de cadrage pseudo-aleatoire. - Google Patents

Circuit generateur de cadrage pseudo-aleatoire.

Info

Publication number
BE903898A
BE903898A BE2/60882A BE2060882A BE903898A BE 903898 A BE903898 A BE 903898A BE 2/60882 A BE2/60882 A BE 2/60882A BE 2060882 A BE2060882 A BE 2060882A BE 903898 A BE903898 A BE 903898A
Authority
BE
Belgium
Prior art keywords
framing
pseudo
generator circuit
patterns
random
Prior art date
Application number
BE2/60882A
Other languages
English (en)
Inventor
R H Beeman
Original Assignee
Gte Comm Systems Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Gte Comm Systems Corp filed Critical Gte Comm Systems Corp
Publication of BE903898A publication Critical patent/BE903898A/fr

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements
    • H04J3/0602—Systems characterised by the synchronising information used
    • H04J3/0605—Special codes used as synchronising signal
    • H04J3/0611—PN codes

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Time-Division Multiplex Systems (AREA)

Abstract

Un circuit générant un patron de cadrage consistant en une séquence de régistre à décalage pseudo-aléatoire. Ce circuit utilise un patron de cadrage extremement long, ne nécessitant pas une grande capacité de mémoire ni de recevoir un grand nombre de bits pour reconnaitre le patron de cadrage. L'utilisation de patrons de cadrage longs limite le risque de mauvais cadrage causé par des patrons en positions binaires différentes de la position binaire du cadrage.
BE2/60882A 1984-12-24 1985-12-20 Circuit generateur de cadrage pseudo-aleatoire. BE903898A (fr)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US06/685,702 US4590601A (en) 1984-12-24 1984-12-24 Pseudo random framing detector circuit

Publications (1)

Publication Number Publication Date
BE903898A true BE903898A (fr) 1986-04-16

Family

ID=24753334

Family Applications (1)

Application Number Title Priority Date Filing Date
BE2/60882A BE903898A (fr) 1984-12-24 1985-12-20 Circuit generateur de cadrage pseudo-aleatoire.

Country Status (5)

Country Link
US (1) US4590601A (fr)
JP (1) JPS61157040A (fr)
BE (1) BE903898A (fr)
CA (1) CA1255402A (fr)
IT (1) IT1186159B (fr)

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4819231A (en) * 1983-01-20 1989-04-04 Nippon Hoso Kyokai Framing timing detection circuit for a character code broadcasting system
ATE84165T1 (de) * 1985-10-15 1993-01-15 Sony Corp Logische schaltung mit zusammengeschalteten mehrtorflip-flops.
US4815018A (en) * 1985-12-24 1989-03-21 Hughes Aircraft Company Spurless fractional divider direct digital frequency synthesizer and method
DE3773369D1 (de) * 1987-03-05 1991-10-31 Hewlett Packard Ltd Erzeugung von triggersignalen.
JPH01165239A (ja) * 1987-12-21 1989-06-29 Advantest Corp データパターン同期装置
GB8814821D0 (en) * 1988-06-22 1988-07-27 British Broadcasting Corp Data synchronisation
JPH0475426U (fr) * 1990-11-14 1992-07-01
US5349611A (en) * 1992-11-13 1994-09-20 Ampex Systems Corporation Recovering synchronization in a data stream
US5365585A (en) * 1993-08-30 1994-11-15 Motorola, Inc. Method and apparatus for encryption having a feedback register with selectable taps
US6201870B1 (en) * 1997-03-20 2001-03-13 Massachusetts Institue Of Technology Pseudorandom noise sequence generator
US6947960B2 (en) * 2002-02-21 2005-09-20 Koninklijke Philips Electronics N.V. Randomness test utilizing auto-correlation
US9344146B2 (en) * 2013-03-11 2016-05-17 Intel Corporation De-correlating training pattern sequences between lanes in high-speed multi-lane links and interconnects
EP3297205A1 (fr) * 2016-09-16 2018-03-21 Universiteit Gent Aligneur de séquence pour synchronisation de données

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3731198A (en) * 1966-08-25 1973-05-01 Ibm Synchronization device for anti-jamming communications system
GB1360260A (en) * 1971-09-23 1974-07-17 Standard Telephones Cables Ltd Multilevel pcm system
US3854011A (en) * 1973-09-24 1974-12-10 Gen Dynamics Corp Frame synchronization system for digital multiplexing systems
US4475208A (en) * 1982-01-18 1984-10-02 Ricketts James A Wired spread spectrum data communication system

Also Published As

Publication number Publication date
IT8523318A0 (it) 1985-12-20
CA1255402A (fr) 1989-06-06
US4590601A (en) 1986-05-20
JPS61157040A (ja) 1986-07-16
IT1186159B (it) 1987-11-18

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Legal Events

Date Code Title Description
RE Patent lapsed

Owner name: GTE COMMUNICATION SYSTEMS CORP.

Effective date: 19901231