BE890775A - INTERPOLATION ANALOG-TO-DIGITAL CONVERTER - Google Patents

Description

       

  The present invention relates generally to devices used in telecommunications systems and relates more particularly to a new audio processing circuit for subscriber line in which input voice signals in analog form are converted and processed in digital form before being transmitted and, conversely, the received signals are processed in digital form before being reconverted in analog form.

  
Prior art telecommunications devices for converting voice signals to a digital format for transmission typically include a subscriber line interface circuit which provides two-wire to four-wire conversion and operation line supply using transformer coupling techniques, as well as additional circuits to provide supervisory and ringing test functions, analog transmit and receive filters, and an encoder-decoder that performs actual signal conversion

  
  <EMI ID = 1.1>

  
reverse MIC signals into analog signals. Integrated circuit manufacturers are currently attempting to replace these individual circuit components with integrated circuits which perform the various functions as they are currently performed, i.e., a single channel monolithic codec decoder replaces the coding-decoding function, single-channel filters replace the filtering function and a monolithic subscriber line interface circuit replaces the transformer and the equipment associated with it.

   Because the prior art systems were based on a system architecture which was developed a number of years ago and took advantage of the components available at that time, simple replacement of the components using the technology of Complex integrated circuits does not allow you to make the most of this technology.

  
The systems of the prior art perform a certain number of functions which can be divided into three main categories. (1) The high-voltage analog interface function with the subscriber line, (2) voice signal processing, including two-wire to four-wire conversion, filtering and coding, and (3) the d interface with the digital world comprising the circuits for transmitting MIC signals and the command line which comes from a processor or a controller. To make a new system, it is reasonable to cut the new system according to these categories. The analog interface with the subscriber line requires high current and high voltage devices and is therefore most advantageously achieved with high voltage bipolar technology.

   High voltage bipolar technologies are not high density technologies and the corresponding device should therefore be kept as simple as possible. Both signal processing and digital interface functions can be performed in low voltage technology. Low-voltage technologies are technologies with a high level of integration and high density among which the n-channel MOS technology corresponds to the optimal choice as regards cost.

  
At present, signal processing is carried out in the form of a two-wire to four-wire analog conversion followed by analog filtering,

  
  <EMI ID = 2.1>

  
analog-digital or digital-analog conversion, The compression-extension functions are also performed in an analog way in analog-digital and digital-analog converters. Since n-channel MOS technology is optimal for digital functions, it seems possible in practice to base a new system on digital signal processing. However, the designers of such systems have so far been reluctant to use digital filters, since these devices are complex structures which require a large amount of material and which dissipate significant power.

  
To achieve a digital filter structure, it is necessary to use an analog-to-digital and digital-to-analog converter. However, in subscriber line audio processing functions, analog to digital and analog digital converters are required even with analog filters, so the use of such converters does not represent a penalty. They are simply placed in different parts of the system. Digital filters also require a reasonable amount of equipment from the start that performs general functions. The realization of such a filter requires an arithmetic processing unit, a read only memory and a random access memory. Therefore, a very simple filter requires almost as much silicon-based material as a complex filter.

   Although the filters required for subscriber line functions are complex filters, the digital filter has a cost advantage when compared to the analog filter.

  
When we examine how the cost of a filter (based on the silicon area) varies according to the complexity (or degree of difficulty) and performance required of the filter, we see that with filters

  
of analog type the cost increases according to a linear function of the complexity. However, in the case of digital filters, the initial cost is high but the cost corresponding to an increase in complexity is greatly reduced. One of the reasons for this is that digital filters can use multiplex and time-sharing equipment, while analog filters cannot. In addition, the digital filter does not require precision components while the analog filter requires a large number of precision components (which may need to be adjusted and must have very little drift) in order to meet performance specifications. . You can also increase the precision of the digital filter by simply adding additional -bits in the calculation circuit.

  
Another difficulty was power dissipation due to the importance of arithmetic processing.

  
  <EMI ID = 3.1>

  
such applications. Characteristic digital filters require fast multipliers that dissipate a lot of power. Telecommunication systems require very little power dissipation and analog filters have tended to require less power than digital filters. Consequently, the embodiments of the prior art have traditionally used analog filters rather than digital filters.

  
An essential aim of the invention is therefore to produce a new audio frequency processing circuit for subscriber line in which all the signal processing is carried out after conversion of the input voice signals into digital form.

  
The invention also aims to produce an improved analog-digital conversion circuit intended for use in the audio-frequency processing parts of a telecommunications device.

  
The object of the invention is also to offer improved digital filtering techniques which are intended to be used in the signal processing parts of a telecommunications device.

  
In summary, a preferred embodiment of the invention consists of a transmission circuit comprising an input filter, an analog-digital converter, a digital signal processing circuit comprising digital filtering devices controlled by computer and user programmable, and a transmission register; and a reception circuit comprising a reception system, a digital signal processing circuit comprising digital filtering devices controlled by computer and programmable by the user, a digital-analog converter and an output filter.

  
Other characteristics and advantages of the invention will be better understood on reading the following description of embodiments and with reference to

  
to the accompanying drawings in which:

  
FIG. 1 is a block diagram showing the system architecture of an audio-frequency processing circuit for subscriber line which corresponds to the invention; Figure 2 is a diagram showing a finite impulse response filter;

  
Figures 3 and 4 are diagrams showing two types of filters with infinite impulse response; FIG. 5 is a block diagram representing an analog-digital converter with interpolation of the prior art, of the type used in accordance with the invention;

  
FIGS. 6a and 6b respectively represent the interpolation at three levels and the interpolation at two

  
  <EMI ID = 4.1>

  
Figures 7a and 7b illustrate the operation of the device corresponding to the invention;

  
Figure 8 is a graph showing the gain characteristic as a function of the frequency of an analog-to-digital converter using a converter of the type shown in Figure 10; FIG. 9 is a block diagram representing an analog-digital converter with digital interpolation modified according to the invention; FIG. 10 represents another embodiment of an analog-digital converter with interpolation corresponding to the invention; Figure 11 illustrates the operation of the analog-to-digital converter which is shown in Figure 10; FIG. 12 is a graph representing the digital signal / noise ratios for an adaptive analog-digital-digital converter corresponding to the invention;

   Figure 13 is a block diagram showing a circuit for modifying the operation of the converter which is shown in Figure 10 Figure 14 is a driagram illustrating the operation of a converter with and without the modification which is shown in Figure 13 ; FIG. 15 is a block diagram of a digital filter with reduction in sampling frequency corresponding to the invention; FIG. 16 represents an embodiment by material of the filter which is represented in FIG. 15; FIG. 17 is a logic diagram showing an embodiment of a finite impulse response filter corresponding to the invention; FIG. 18 is a logic diagram representing the production of a 23-tap finite impulse response filter corresponding to the invention;

   Figure 19 is a logic diagram showing an embodiment of a parallel adder filter corresponding to one invention; FIG. 20 is a logic diagram showing an embodiment of a combinational logic network of a three tap infinite impulse response filter corresponding to the invention; FIG. 21 is a block diagram showing a finite impulse response filter with five taps using a device for consulting a read-only memory; and Figure 22 is a block diagram showing an embodiment of an eight tap finite impulse response filter using read-only memory consultation.

  
We will now consider FIG. 1 in which we see a block diagram of a subscriber line audiofrequency processing circuit, 10, intended for use in association with a subscriber line interface circuit 12, an example of which is described in <EMI ID = 5.1>

  
In general, the subscriber line audiofrequency processing circuit comprises elements forming a transmission circuit which comprises an input filter 14,

  
an analog to digital converter 16, a digital signal processing circuit 18 and a transmission register 20. The received signal circuit comprises a reception register 22, a reception signal processing circuit 24, a digital to analog converter 26 and an output filter 28. In addition, there is also an input / output control element 30 as well as additional circuits comprising a system control circuit 32 and a control circuit 34 for the audio frequency processing circuit of subscriber line.

  
More specifically, the input filter 14 is a simple anti-aliasing filter which is used to prevent signals close to the sampling rate from being folded back into the voice band during subsequent operations to reduce the sampling rate. . Filter 14 must have attenuation of at least 10 dB at 508 kHz (if F = 512 kHz). This can be achieved by using a single pole filter placed at 114 kHz. The delay that manifests in this

  
  <EMI ID = 6.1>

  
As will be explained further below

  
detailed, the analog-to-digital converter 16 is

  
an interpolation encoder that samples the signal

  
analog input (voice) at a relatively high sampling frequency, such as 512 kHz (or

  
256 kHz) and which produces digital words with several

  
bits representative of the signal amplitude for each sample.

  
The analog-to-digital converter is of

  
great importance in determining system performance and it creates most of the errors manifesting in the system. These performances determine the

  
signal to noise ratio, gain stability, noise

  
channel at rest, harmonic distortion, response to out-of-band signals, intermodulation distortion and they can limit the frequency response.

  
The transmission signal processing circuit

  
18 includes two low-pass filters for reducing the sampling frequency, 40 and 42, a balancing filter 44, a filter for correction of the attenuation distortion in transmission, -46, a gain adjustment circuit in emission 48, a main emission filter 50

  
and a digital compressor circuit 52. As will be explained in more detail below, the analog-to-digital converter 16 is also capable of precisely converting signals which are above 3.4 kHz and these signals must therefore be mitigated

  
with low-pass filters, as in a conventional filter system. According to the invention, the filtering is accomplished by means of a series of low-pass filters including those which are represented at 40,

  
42 and 50. The low pass filters 40 and 42 are filters for reducing the sampling frequency. The emission filter 50 is not only a low-pass filter and it further comprises a high-pass filter section for performing the rejection at 50 Hz which

  
is normally performed as part of the anti-aliasing filter in a telephone system.

  
Digital filters require volume

  
of significant computation and this computation volume is all the greater the higher the frequency, because of

  
the higher rate of computation which is necessary. he

  
is therefore important from an economic point of view of

  
reduce the number of calculations and reduce the sampling rate as quickly as possible. The filters 40 and 42 therefore have the function of reducing the sampling rate. More specifically, the filter 40 reduces the sampling rate from 512 kHz to 32 kHz

  
by performing a low pass filtering function. This filter should ensure that no signal greater than

  
32 kHz is not folded back into the expanding bandwidth

  
from 0 to 3.4 kHz. In addition, the filter 40 must have characteristics in the passband which are as flat as possible. However, it is not obligatory, nor particularly critical, that the characteristic in the passband be kept absolutely flat, since this can be compensated for in other sections of digital filters.

  
  <EMI ID = 7.1>

  
An advantage of using digital filters is that you can use other filters to compensate for the effects of a previous filter, du'fait

  
that their characteristics are very precisely defined. When using an analog filter, it is

  
very difficult to use a next filter section to cancel the effects of a previous section, because the variations of a filter are due to the components

  
of this filter.

  
The 32 kHz signal from filter 40 is then applied to a second sample frequency reduction low pass filter, 42, which further reduces the frequency to 16 kHz.

  
This filter must ensure that no component

  
is folded back into the bandwidth and that there is

  
not in its output signal components that would represent frequencies greater than 12.6 kHz, that is, 16 kHz minus 3.4 kHz. These two filters could be combined into a single filter structure,

  
but they are effectively separated in two in the invention so as to provide dots corresponding to 32 kHz and 16 kHz signals which are intended for use by other circuit components.

  
For the moment, filters 46 and 48 will be skipped to consider the main emission filter 50 which provides both low-pass and high-pass filtering functions. The low-pass filtering function defines a low-pass filter with a descending slope characteristic from 3.4 kHz to 4.6 kHz and this function is analogous to that which is fulfilled by analog filters in digital systems. prior art. This filter also provides attenuation correction to compensate for the effects of filters 40 and 42 as well as any effect produced by the pre-filter 14. The high-pass section of this filter provides rejection at 50 Hz and makes any signal disappear. low frequency that is not desirable to transmit in a telephone system. The output signal of the filter 50 consists of a linear code. It is necessary to choose

  
  <EMI ID = 8.1>

  
signal-to-noise ratios in the system, as well as for easy signal processing.

  
The digital compressor 52 uses a digital algorithm to convert the linear code to a code corresponding to the p-law or the A-law which is necessary in some telephone systems. If a linear code output signal is desired, this subset of the system can be skipped. The output signal of the compressor is applied to a transmission register circuit 20 which, when controlled by system control signals applied at 21, transmits the data to a telephone exchange which is connected to the terminal. emission 50. The functional subsets described so far are quite similar to those corresponding

  
to the usual functions performed by the emission filter and the analog-digital converter of the circuits of the prior art. The circuits of the prior art usually include a gain adjustment element upstream of the transmission sub-assembly of the system, this element being constituted by a certain type of amplifier. In the embodiment which is represented, the gain function is accomplished by a gain adjustment circuit 48 which provides gain by multiplying by a digital constant the digital word which comes from the sampling frequency reduction filter 42.

   The digital constant is user programmable and can be precisely programmed so that the gain has a very wide range of variation, from +12 dB to almost -00 dB, depending on what is determined by an appropriate choice of gain control words that the user programs in the device.

  
While in the systems of the prior art the gain must be programmed by a certain manual adjustment of the system, in the device of the invention there is no physical component to be modified, since the gain is programmed by a command input / output bus, 51, and the gain can be programmed at the time of installation, under the control of a computer, which represents a significant saving of time and money for the manufacturer. The balancing filter 44 is used to perform a transhybrid balancing function, described below in more detail.

  
We will now consider the reception circuit in which the signals received on terminal 55 are applied to the input of reception register 22, then then to processing circuit 24 which includes a digital expander 54, a main reception filter

  
  <EMI ID = 9.1>

  
reception attenuation distortion correction 50,

  
two low-pass interpolator circuits 62 and 64, and one

  
impedance matching filter 66.

  
The expander 54 operates under command of the program (order applied on the input 57) so as to receive a code in law u or in law A and to convert it into

  
a 12 or 13 bit linear code, like the one used in the transmission circuit. If the control word indicates that the input word is linear, the expander

  
can be skipped. The input sampling rate

  
of the system is 8 kHz.

  
The receiving circuit aims to simplify

  
the reception filter which must here filter a component

  
at 8 kHz using a low pass filtering technique.

  
In addition, the reception filters of the invention must compensate for the distortion which is produced by the low sampling rate. This distortion is called sinX / X distortion and it produces an apparent attenuation of the signals when the frequency of the signals becomes

  
an appreciable percentage of the sampling rate.

  
For example, a 3.5 kHz signal in an 8 kHz sampling system has about 2 or 2.5 dB of attenuation that is required. correct.

  
According to the invention, there are two objectives. One is to use filtering techniques to

  
  <EMI ID = 10.1>

  
all the points that are necessary to achieve a much higher sampling rate, i.e. a sampling rate of 256 kHz (or 128 kHz).

  
At the higher sampling rate, there is a double advantage. First, the distortion in sinX / X is greatly reduced and it is in fact reduced to such an extent that it is so small that it is not necessary to correct it. Secondly, the only component that is present, in addition to the components of the voice band below 4 kHz, is the sampling component.

  
Using a sampling component

  
at a very high frequency, such as 256 kHz (or 128 kHz), the level of this component is greatly reduced and

  
it is much easier to filter it because

  
the reception filter 56 must be flat for voice band signals and must have a high attenuation at the sampling rate. Filter design

  
the easier the higher the sampling rate, because of the greater difference between the passband and the attenuated band of the filter.

  
According to the invention, the filtering is carried out using the three filters 56, 62 and 64. The main reception filter 56 is a low-pass device similar to the low-pass element of the filter 50 and it operates at 16 kHz, while the high pass section

  
of the filter 50 operates at 8 kHz. The filter 56 receives a signal at 8 kHz but it outputs a signal at

  
16 kHz. It must therefore have considerable attenuation in the band between 4.6 kHz and 8 kHz, in order to ensure the rejection of any folded frequency and of the 8 kHz component which is present, because of the sampling rate. While the emission filter
50 is both a low pass filter and a high pass filter, filter 56 is only a low pass filter.

  
The reason why the transmit circuit has low pass and high pass elements while

  
the reception filter -includes that a low-pass element consists in that in the transmission circuit

  
can very easily receive signals at 60 Hz in the USA and signals at 50 Hz in Europe, because the signal

  
is received by a telephone line and these lines typically extend along power lines. A fraction of these signals unfortunately enter the telephone system. The high pass filter section 50 is designed

  
so as to ensure rejection of the signals at 50 Hz and

  
once these signals have been rejected

  
and that the system works in digital form, the signals at 50 Hz can no longer be introduced into subsequent digital sections. Therefore, the filter

  
at 50 Hz is not necessary in the reception circuit.

  
Filter 56 output signal is applied

  
at the input of a gain adjustment circuit 58, then at a reception attenuation correction filter 60 and

  
these two elements will be described later in more detail.

  
The first low-pass interpolator circuit 62 receives an input signal at 16 kHz from the circuit

  
58 and it produces an output signal at 32 kHz. It constitutes a low-pass filter whose purpose is to strongly attenuate the component at 16 kHz. Because the output signal is at 32 kHz, this filter introduces a component

  
at 32 kHz.

  
The second low-pass interpolator circuit 64 is also a low-pass filter which outputs a signal at 256 kHz (or 128 kHz) in the system considered.

  
so as to perform a low-pass filtering of the components at 32 kHz and to introduce certain components of lower amplitude at the higher frequencies. The filters 62 and 64 essentially have the function of filtering the high frequency components. If they are not perfectly flat in the bandwidth, their characteristics can be predicted very precisely and can be compensated for by the filter 56, which is indeed the case in the system considered, since the filters 62 and 64 effectively attenuate some of the signals near the high end of the bandwidth, that is to say around 2 or 3 kHz. Consequently, the filter 56 includes a compensation network which compensates for the attenuation which is produced by the filters 62 and 64.

  
The output signal of the filter 64 is then applied to the digital-analog converter 26 which converts the signals into analog form and transmits them to the output filter 28. In telephone systems, the high frequency components must be attenuated by at least 28 dB relative to the components

  
low frequency. With a sampling rate

  
at 256 kHz, the signal at this frequency is 28 dB lower. to that of the 3.4 kHz component. Thus, no output or smoothing filter is theoretically necessary. However, the system considered comprises the filter 28 for security purposes.

  
Digital filters are complex arithmetic processors that implement the fundamental equation of a filter:

  

  <EMI ID = 11.1>


  
where X. represents the input samples and Y. represents the output samples.

  
FIG. 2 schematically represents an 8-tap finite impulse response filter, called a few. times transverse or non-recursive filter, and this filter comprises seven delay or memory elements, eight multipliers 69 and seven additive elements 70. As will be noted, this circuit realizes a filter of the form represented by the equation:

  

  <EMI ID = 12.1>


  
  <EMI ID = 13.1>

  
current and delayed de of X which must be multiplied by the respective tap coefficients. The device

  
with 8 taps which is represented is unconditionally stable insofar as it does not involve a reaction and since the output value is only a function of a previous set of input values.

  
FIG. 3 represents a filter with infinite impulse response of canonical form sometimes called a recursive second order filter, which comprises two delay elements 71, four addition elements 72 and four multiplier elements 73. This circuit can be used to schematically represent a responding filter to the equation:

  

  <EMI ID = 14.1>


  
and it is suitable for use as a low pass filter. In general, this filter, much more efficient than the finite impulse response filter (it has only two memory elements), exhibits an attenuation increasing more rapidly, etc.

  
FIG. 4 schematically represents a filter with infinite impulse response in coupled form. This device is suitable for 1, use as a high-pass filter corresponding to the equation:

  

  <EMI ID = 15.1>


  
in which :

  

  <EMI ID = 16.1>


  
and

  

  <EMI ID = 17.1>


  
note that this filter has two delay elements
74, six multipliers 75 and five adders 76.

  
We can consider that a filter has an infinite impulse response if in equation (1) above,

  
  <EMI ID = 18.1>

  
the filter is considered to have an infinite impulse response. Filters with infinite impulse response tend to be more efficient in that they allow a given filter characteristic to be achieved with fewer coefficients. The basic compromises when considering filters relate to the total number

  
multiplications and additions per second, the total memory capacity needed to save the input and output samples (RAM) and the total memory capacity needed to save the coefficients (ROM).

  
To achieve maximum efficiency, filters should operate with as low a sampling rate as possible. This applies to filters

  
with finite impulse response as with infinite impulse response filters. Finite impulse response devices require more coefficients to make the filter as the sampling rate increases. In fact, the number of coefficients approximately doubles when the sampling rate doubles. Thus, when the sampling rate increases, the RAM and ROM capacity increases linearly and the arithmetic rate increases as the square of the increase in the sampling rate (higher mathematical rate x number of calculations higher). Infinite impulse response filters do not require more coefficients as the sampling rate increases, but they require more words

  
Long, so that the computation takes more time (using serial / parallel multipliers) and the computation rate increases with the sampling rate.

  
The correct choice for architecture seems to be to try to reduce the system's sampling rate by using a low-pass filter whose attenuated band begins at a much lower frequency.

  
  <EMI ID = 19.1>

  
the sampling rate is achieved by using one in eight of the filter output samples and rejecting the other seven. It will be noted that in an analog-digital converter with interpolation, the data are sampled at a very high rate, that is to say 32 to 54 times the frequency with which one is interested; so that

  
the filter needed to limit the signal to F / 16 remains relatively simple. In the applications of

  
telephone type, the sampling rate can be reduced from 512 kHz to 32 kHz with a bandpass filter

  
whose attenuated band begins at 16 kHz. Because the bandwidth ends at 3.4 kHz, this filter is much simpler than the filter that is required

  
to perform real low pass filtering functions
(its attenuated band starts at 4. 6 kHz).

  
The most efficient way to achieve the low pass filter is to use a finite impulse response filter. This conclusion is based on the following reasoning. An infinite impulse response filter used as a low-pass sample rate reducer should operate at the sample rate, calculate the results at the initial sample rate, and then discard 7 of the

  
8 results. All results must be calculated since each result is necessary to calculate the next result. However, the low pass filter can be a second order filter but it requires 5 coefficients or 5 multiplications and 5 additions every 4 us, or a multiplication rate of 2.5 MHz and an addition rate of 2 MHz. A finite impulse response filter - must calculate only one result out of 8. It does not have to calculate the seven unused results because they are not necessary for the calculation of future samples. A filter with 20 coefficients can be produced which requires 20 multiplications and 10 additions at 32 kHz. The multiplication frequency is reduced to 1.28 MHz and the rate of addition is 1.204 MHz. It can also be shown that the memory capacity required is comparable

  
  <EMI ID = 20.1>

  
be realized with a simple series adder structure to save material.

  
  <EMI ID = 21.1>

  
risk is multiplication. The realization of the multipliers requires a lot of material and the multipliers can dissipate considerable power. As noted earlier, the sample rate reduction filter requires frame rates of

  
  <EMI ID = 22.1>

  
multiplication is normally accomplished in a fully parallel combinational circuit which requires a very large amount of hardware, or it is accomplished according to a series / parallel function with addition and offset. Serial / parallel multiplier requires N bit shift register, N + M adder

  
bits and N clock cycles to perform an N x M multiplication. However, none of these techniques is a good choice for a processor made in complex integrated circuits.

  
One promising technique is what is called short word optimization. Use

  
  <EMI ID = 23.1>

  
the coefficient and the multiplication only requires

  
esz

  
  <EMI ID = 24.1>

  
Being a ring shift and a 12-bit coefficient containing only three "1s", one can accomplish a multiplication in 3 clock periods by ignoring all the additions for which zeros appear in the coefficient. The techniques for simplifying the coefficients are very complex and require certain compromises on the design of the filter (this can be offset by an increase in the complexity of the filter). Finite impulse response filters that have more coefficients seem to be less sensitive to simplification of the coefficients, although infinite impulse response filters designed from real filters with low sensitivity can also have a good insensitivity to the simplification of the coefficients.

  
Because the interpolation analog-to-digital converter is a system whose sampling rate is much higher than the strictly necessary value, with the interesting information in a

  
frequency band lower than that of the system output signal, digital filters such as those shown at 40, 42, 46 and 50 in Figure 1 are required to remove the high frequency error components that are generated by the converter, to smooth and average the components of low frequency signals, as well as to accomplish

  
any other low frequency filtering required. Digital filtering can be accomplished with various different architectures using finite impulse response filters and / or infinite impulse response filters to implement the system.

  
In the preferred embodiment of the device which is generally represented in FIG. 1, the low-pass filter for reducing the sampling rate, 40, is constituted by a finite impulse response filter with four taps and by two filters

  
impulse response over three taps. The first of these reduces the signal to 512 kHz to 128 kHz, the second reduces the signal to 128 kHz to 64 kHz and the third reduces the signal to 64 kHz to 32 kHz. The second low-pass sampling rate reduction filter, 42 is implemented as a 5-tap finite impulse response filter which reduces the signal to 16 kHz.

  
32 kHz and the attenuation distortion correction filter for transmission, 46, is an 8-tap finite impulse response filter. The adjustment filter

  
emission gain 48 is a one-tap finite impulse response filter and the main emission filter 50 is a three-tap infinite impulse response filtering device which includes two low pass filters of canonical form and one high pass filter of the coupled form. The main emission filter reduces to

  
  <EMI ID = 25.1>

  
a 3-tap finite impulse response device.

  
The system allows the incoming audio signal as well as a fraction of the outgoing signal (reception signal) to pass to the input filter 14. However, since the generated outgoing signal is known, as well as the time it takes for it to return after passing through the system, the balancing filter 44 can be used to generate a cancellation signal which, added at 45 in the transmission circuit, will cancel

  
the return signal. In addition, although the characteristics of the line are not initially known, the characteristics of the system are known. The user can however determine the characteristics of the line and program the filter 44 to ensure proper balancing and since the filter 44 is programmable in digital form, such cancellation can be accomplished very precisely.

  
The main reception filter 56 includes two low-pass filters with infinite impulse response in anonic form which increase the frequency of the received signal from 8 kHz to 16 kHz. The reception gain adjustment filter 58 is a one-tap finite impulse response filter, the reception attenuation distortion correction filter, 60, is an 8-tap finite impulse response filter, and the interpolator lowpass 62 is a 5 tap finite impulse response filter which raises the signal to 32 kHz.
16 kHz coming out of filter 60. The second low-pass interpolator consists of three filters with finite impulse response with three taps which raise the signal to

  
32 kHz to bring it to 64 kHz, 128 kHz and
512 kHz.

  
The impedance matching filter 66 is a finite impulse response filter with four taps (or

  
with 8 sockets) which is used to adapt to the characteristics of the line. More specifically, the impedance matching filter 66 can be used to modify the system input impedance, seen at the 2-wire input access of the system. The filter 66 effectively returns the voltage which is generated in the incoming signal

  
at the entrance access. If this is done with appropriate amplitude and polarity, the value of the effective input impedance can be changed to match the characteristic impedance of the telephone line. The control of the impedance of the filter 66 thus makes it possible to ensure the rejection of the echoes and the adaptation to different input lines. However, changing the input impedance makes the system gain frequency sensitive. However, you can program the attenuation distortion correction filters in transmission and reception, 46 and 60, so as to compensate

  
any attenuation distortion thus created by the use of filter 66. Filters can also be used

  
gain control to add incorporated losses

  
in order to eliminate transmission problems such as parasitic oscillations.

  
The test loop 67 is intended to allow the testing of the device or of the line and can be used to facilitate the selection of the coefficients for various filters.

  
The audio frequency processing circuit of

  
subscriber line also includes a serial control interface 32 which is connected to a control computer for programming a number of functions

  
of the device. Interface has a serial control bus
33 which is used to program the transmission and control time slots for the subscriber line audio processing circuit, as well as to fix the gain of the device in transmission and in reception. It also includes a voltage cut-off function. Rhythm input signals include a DCLK data clock signal, a DIN data input signal, a DOUT data output signal, a select signal

  
CS chip for serial interface, MCLK main clock signal for timing control of arithmetic and logic units, CLKX and CLKR transmit and receive clock signals, synchronization pulses

  
FSX and FSR transmit and receive frame and one

  
TSC time slot sampling signal for interface with the MIC system. The time slot assignments are defined with respect to the FS frame synchronization pulses. When the transmission circuit goes to the active state, a time slot sampling pin (TSC) is brought to the low state so as to attack a three-state separator circuit if this

  
is required in the system. The transmitter and receiver MIC splitter circuits have separate clock inputs so as to be able to operate from

  
asynchronously, but in most systems, the transmit and receive clock inputs will be connected in common. The synchronization pulses of

  
frame are also separated for transmission and reception, but we will use a common pulse in

  
most systems and if different time slots are required, this feature can be programmed using the selection command input

  
time slice.

  
Using the serial control bus 33, the information in transmission and reception time slots is programmed into the device to determine the instants at which the device must transmit and receive data; the coefficients for the impedance matching filter 66, the balancing filter 44, the transmission attenuation distortion correction filter 46 and

  
the reception attenuation distortion correction filter 60 are all programmed one byte at a time; and the transmission and reception gain adjustment coefficients are also programmed in the device.

  
All this data can be sent back for reading on the DOUT line of bus 33, under an appropriate command. In addition, the device can be programmed using bus 33 to give it special configurations. We can for example give the device a configuration making it

  
  <EMI ID = 26.1>

  
with linear coding.

  
In addition, the parameters of all four programmable filters 44, 46, 60 and 66 can

  
be set to default values, i.e.

  
say that the impedance matching filter 66 and the balancing filter 44 can be set to zero and that the two attenuation distortion correction filters

  
46 and 60 can be set to a value equal to unity. The gain adjustment filters 48 and 58 have default values which can be set equal to unity. The reception gain adjustment filter 58

  
also has a second default value which is zero, to block the receiving circuit.

  
We set the test condition by programming

  
an order which modifies the input signal applied to the various filters, i.e. the output signal from the low-pass interpolator 64 is applied to the sampling frequency reduction low-pass filter, 40, to perform a digital loopback, while the output signal from the analog-digital converter 16 is sent back to the digital-analog converter 26 to perform an analog loopback. These operations are naturally accomplished under the control of the program. An additional feature of the device is that a flip-flop type TTL is connected to the outputs of the subscriber line interface circuit, whereby the outputs are programmable using command words applied on the bus. serial interface 33.

  
We will now consider FIG. 5 which represents a block diagram of a simplified version of an interpolation coder of the prior art, of the type used to make the analog-digital converter 16 which is represented in FIG. basic coding loop, a negative reaction is used to minimize the average difference between the analog input signal x (t) and its quantized representation q (t). An integrating amplifier 77 integrates the difference between

  
x (t) and q (t) and add up this difference and

  
the instantaneous difference between x (t) and q (t), and a comparator 78 detects the polarity of the result. The output signal from comparator 78 is applied to a logic shift control circuit 79 which controls an increase or a decrease in the quantized signal q (t) which is produced by a digital-analog converter 80. In the preferred embodiment, logic circuit 79 includes an 8-bit bidirectional shift register

  
which works like a digital accumulator

  
by filling with "1" at the bottom (least significant bit) and with "0" at the top. When the register is filled with logic "1", the absolute value of the quantized quantity increases. The logic circuit 79 also controls the polarity of the quantized quantity and it transmits the polarity on the line

  
81 in the form of a sign bit SB. The absolute value is issued on lines-781.

  
Additional details and operating characteristics of a similar circuit can be found

  
to that shown, in an article by Bruce A. Wooley and James L. Henry entitled "An Integrated Per-Channel PCM Encoder Based On Interpolation" pages 14-20, IEEE Journal

  
of Solid-State Circuits, Vol. SC 14, N [deg.] 1, February 1979.

  
Although the analog-to-digital converter

  
With interpolation described above and others described in the prior art can be used in a system corresponding to the invention, these converters have several drawbacks. Because the output signal

  
of the comparator is sampled at frequency F (which

  
is much higher than the input frequency range we are interested in) and that this signal is used to control the shift register so as to determine the new quantized output signal, the output signal of the digital-analog converter must change with each sample since a 1-bit code authorizes only two conditions, that is to say an increase or a decrease, and does not allow to have a state in which the output signal of the ' digital to analog converter remains constant. Specifically, the shift register control allows only the following values for the digital converter input signals -

  
  <EMI ID = 27.1>

  
As indicated in the article by Candy et al. titled "A Per-Channel A / D Converter Having 15-Segment u-255 Companding"; pages 33-42, IEEE Trans. on Communications, Vol. com-24, N [deg.] 1, January 1976, these codes were chosen to correspond to the fraction 4/3 of the end points of the characteristic defined by the strings

  
  <EMI ID = 28.1>

  
conch shell is the end point of a law rope

  
  <EMI ID = 29.1>

  
&#65533; Orise that 17 levels in the system, that is 8 positive levels, 8 negative levels and 0. The feedback loop causes the analog-digital converter to try to force the output signal of the integrator to zero, so that the integral of q (t) tends to become equal to the integral of x (t).

  
For continuous input signals, and with appropriate damping set by resistor R and capacitor C, the system will generate a configuration like that shown in Figure 6a which is a three-level oscillation around the input signal. Here we describe a 256 kHz system in which 32 samples are effectively subjected to an averaging by performing two operations each time. The mean of each set of two values read is calculated by taking the lower of these two values and neglecting the scale factor 4/3. For example, if a read value represents 4/3 of the end point n, the next lower read value represents 2/3 of the end point n, and the average is the end point n which corresponds to the code of the lower read value. This averaging

  
  <EMI ID = 30.1>

  
average these samples in a 12-bit parallel adder to give a 12-bit result. The resolution in the adder is a function of the number of samples
(n) to which the average and the resolution of

  
  <EMI ID = 31.1>

  
reading of an individual sample = resolution of the result.

  
Kawahara et al., And others have also described the use of a 512 kHz system in which

  
averaging is only performed up to 32 kHz. However, all these systems present several problems which will now be considered in the company of the solutions which are proposed, in accordance with the invention.

  
1. Variation in gain as a function of frequency. With regard to this problem, the sampling rate and the number of levels in the converter constitute the fundamental constraints at the system level. As the input frequency increases, the system has more difficulty tracking the signal, such as

  
shown in Figures 7a and 7b. As we notice

  
in Figure 7a, the system follows relatively well at

  
250 Hz. However, when the frequency is increased to 4 kHz, the tracking degrades, as shown in Figure 7b. The time required for a signal to pass from the positive full scale value to the negative full scale value is (2M-1) T, and the maximum frequency to the maximum amplitude that the system can generate is F / 2 (2M-1). For the 8-level system, this value is equal to F / 30. However, the system creates errors in the vicinity of these frequencies. Even at lower frequencies, the signal distortion is important. You can observe a variation of the gain as a function of the frequency by measuring the output component of the analog-digital converter at the frequency of the

  
input signal, and Figure 8 shows the results for

  
a sampling rate of 256 kHz and a

  
8 levels. Increasing the sampling rate to 512 kHz improves response at low frequencies

  
but the gain remains a function of the frequency for the high frequencies. This can lead to significant problems in the system if no correction is made. In FIG. 7a, FFT designates the Fourier transformation interval.

  
2. Continuous signals are limited according to the sampling rate. The limitation of the continuous resolution is due to the difference between the

  
levels and the number of samples to which the

  
averaging. In the system described above, a

  
level on two represents a level located in position

  
median between the two adjacent levels. In the technique used by Candy et al., Supra, the

  
average of 16 samples, so the resolution of the

  
signal is about 1/32, a similar resolution

  
to that obtained by following the practice which corresponds to

  
law p or law A. A sampling rate

  
higher, 512 kHz, would

  
averaging over twice as many samples and would provide higher resolution,

  
1/64. We can say that the resolution of these systems is

  
1 / (F- / F) by designating by F the sample rate-

  
output lonnage.

  
3. The dynamics are limited depending on the

  
sampling rate. Limiting the dynamics

  
is a problem similar to that of limiting resolution. Dynamics is the relationship between the most

  
great level and the smallest level that can be solved.

  
The smallest resolved level is close to zero and it is

  
  <EMI ID = 32.1>

  
denoting by M the number of levels (positive or negative) in the digital-analog converter. The dynamic

  
  <EMI ID = 33.1> <EMI ID = 34.1>

  
appear is diminished.

  
4. Limitation of possibilities for processing high frequency signals. When applying frequency converter signals which it cannot track, the output signal tends to collapse and take a phase shift of 180 [deg.] From the input signal. In certain circumstances, the mode of operation without signal tracking also causes signals to appear in the band (at low frequency) whose attenuation relative to the input level is less than -30 dB.

  
5. Out-of-band signals producing in-band signal components. The digital filter with averaging which is used in the circuit

  
described above is not the optimal configuration since it does not correctly eliminate all out-of-band signals and can cause aliasing of out-of-band signals in bandwidth. Out-of-band signals are generated not only by out-of-band input signals but also by analog-to-digital conversion at high sampling rate

  
256 kHz or 512 kHz. Signals between 4 and

  
8 kHz is not attenuated properly and will fall back into the bandwidth (assuming the bandwidth ranges from 0 to 3.4 kHz). The neighboring signals of
12 kHz will also fall back in bandwidth

  
  <EMI ID = 35.1>

  
it seems that this analog-to-digital converter requires a precision pre-filter to be useful for processing voice band signals.

  
Analog-to-digital conversion produces out-of-band signals in the range of -20 to -50 dB below the input level, and some of these signals will fall back with less than -30 dB of attenuation and will increase the noise in the band. They can also decrease the signal-to-noise ratio of the system. The interpolator operating with an input at 512 kHz and a filter performing an average calculation at 32 kHz has better performance: This filter requires complex filtering later on, but it eliminates everything except a simple pre-filter . Signals falling within the 32-36 kHz, 60-68 kHz, etc. bands always fall directly back into the bandwidth and higher attenuation is desirable in these bands.

  
We will now consider FIG. 9 which represents an improvement with respect to the analog-digital converter which is represented in FIG. 5. Although it is represented in a slightly simplified form, the part of the circuit which is framed by the lines in dotted lines 90 is essentially identical to the circuit which is represented in FIG. 5. In accordance with the invention, a second comparator 91, a flip-flop 92 and an additional control logic circuit 93 have been added to generate a 2-bit code instead 1-bit code produced by the embodiment of FIG. 2, and an automatic digital zero circuit has been added,
94, in order to add an offset voltage to the amplifier 77.

  
Additional comparator 91 is used to sample the instantaneous difference between the input signal x (t) and the quantized output signal q (t). The damping resistor R is no longer necessary and it is shown short-circuited by a line 95. As a result, the original comparator 78 compares only the integral of the difference signal
(x (t) -q (t)). The two comparator system has no. overshoot by higher or lower value (relative to a level) and it does not require analog damping.

  
With a single comparator, there were only two new possible states, that is to say an increase or a decrease compared to the previous value. With two comparators, there are four possible new states for q (t). The additional states can correspond to an increase (or decrease) of a greater (or less) quantity, or to the conservation of the same value. In the system under consideration, the only additional state used keeps the output signal constant. The ability to remain at a particular level means that for a continuous input signal, the system oscillates between the two levels which surround the input signal,

  
by changing level to. the sampling rate. This constitutes an improvement over the single comparator system which, as shown in FIG. 6b, can only be reduced to a two-level oscillation at

  
half the sampling rate. The second comparator provides an effective doubling of information
(for continuous signals) and it provides 6 dB more for dynamics and 6 dB more for resolution,

  
without increasing the sampling rate or the number of levels.

  
The second comparator also provides an additional 2.5 dB dynamic boost by allowing the signals from digital to analog converter 76 to be 2.5 dB lower. The single comparator system requires that the maximum output signal from the digital-to-analog converter be equal to the 4/3 fraction of the maximum input level, since

  
this level is represented by the oscillation of the system

  
  <EMI ID = 36.1>

  
the same full scale range, it can use levels corresponding to the fraction 3/4 of those of the system with a single comparator. This increases the dynamics by 2.5 dB. However, the digital signal processing must be modified in order to use the system with two comparators. You can no longer average every other sample using the numeric code of the lower read value, and therefore averaging (or

  
another signal processing algorithm) must be applied to all samples.

  
The automatic zero circuit 94 includes a digital-analog converter 96 and two reversible 6-bit counters, 97 and 98. The counters integrate

  
the sign bit of the 8 kHz signal which is produced in

  
the emission filter 50, upstream of its high-pass filter section and which is returned by the conductor 99. If there is an offset in the system, the counters 97 and

  
98 count in ascending or descending direction until the six-bit code (sign bit plus five absolute bits) applied to the digital converter 96 shows at the output of the latter

  
an appropriate level to be applied to the amplifier
70 to compensate for the offset. Then, the number of plus and minus bits will remain the same and counter 97 will simply oscillate one increment up and down. The lower six bits in counter 98 are used as damping bits to reduce the frequency of any oscillation to a value below the system bandwidth, so that if an oscillation exists, it has a low frequency and either eliminated by the next high-pass filter from the emission filter 50.

  
FIG. 10 represents another independent improvement made to the system which consists in using an adaptive method for controlling the shifting process, in order to allow the use of more levels to obtain greater dynamics, but by removing unnecessary levels to improve the frequency response. In addition to the components of the embodiment which is represented in FIG. 9, this embodiment comprises a peak value register 100, a comparator 102, a subtractor 104 and a comparator
106. The adaptive algorithm is based on the fact that the system cannot follow the signals of high amplitude when the frequency increases, because it has difficulties in following the signal. The biggest problem arises when the signal goes through

  
zero, i.e. in a position in which the quantizer has many low level signals and the input signal changes at its maximum speed. This problem is that shown in Figure 7b.

  
Levels close to zero contain limited information for large amplitude AC signals, and if they could be suppressed, the accuracy of the system would not be significantly reduced. The adaptive algorithm detects the absolute peak value during each cycle and removes an appropriate number of levels around zero to allow the system to track the input signal. More specifically, the peak value of the quantized signal, in register 98, is recorded

  
in the peak value register 100 and the comparator
102 compares the recorded peak value with the current value. Simultaneously, the subtractor 104 subtracts

  
the current value of the peak value and the difference, is compared with a reference input signal

  
which is applied at 108 to comparator 106. However,

  
the subtractor output signal is not just

  
the difference between the two input signals, but the difference between the number of "1" in each of

  
input signals A and B.

  
The output signal produced by the comparator
106 causes the sign bit (SB) to change. When the quantized value approaches zero, the levels around

  
zero are deleted by being skipped and changing the

  
bit of sign. The peak level determines the level at which the sign bit is changed. In the adaptation which is envisaged, this level is five levels below the peak level of the signal (unless the peak level is 00001111 'or less, in which case the adaptation returns to normal operation) and we remove a different number of levels depending on the input amplitude, so as to keep ten active levels.

  
The peak value should be able to decrease when the signal level changes. There are many ways to do this. For example, (a) by reducing one level on each zero crossing,
(b) by reducing the level if a particular level is not <EMI ID = 37.1>

  
a MIC system with a final output signal having a sampling rate of 8 kHz), or (c) by reducing the peak value to a fixed periodic rate. The embodiment which is currently used and which is represented in FIG. 11 reduces the peak level at each passage through zero. This adaptation technique

  
  <EMI ID = 38.1>

  
this maximum which can be followed is increased by

  
Fs / 32 to F / 18. the price to pay for this consists of a very slight increase in the signal-to-noise quantization ratio for the alternative signals. The increased noise is due to the suppression of levels close to zero. However, the suppressed levels represent signals which correspond to less than 1% of the period of a sine wave and the increase of the signal / noise ratio

  
is minimal.

  
The characteristic of variation of the gain as a function of the frequency is also modified and pushed higher in frequency, with much less effect on the low frequency signals, as shown in Figure 8. Figures 7b and 11 respectively show the response with and without adaptation for a signal to

  
0 dB, 4 kHz. This technique is advantageous with regard to the frequency response, without increasing the sampling rate and without any real penalty on

  
performance, in particular with regard to dynamics, resolution and signal-to-noise ratio.

  
The adaptation technique can increase the dynamics of the system without penalizing the frequency response. The digital-analog converter which is represented in figure 5 uses 17 levels and its dynamics and its resolution are just sufficient for the considered application. They can only be increased by increasing the sampling rate and / or by adding additional levels. However, adding levels would require the use of a higher sampling rate, since otherwise the frequency response characteristic would not be acceptable. With the adaptation technique which is represented on figure 10, one can add more levels around zero, without degrading the frequency response, because these levels will be used only for the very weak. wheat signals.

  
A system using a 10-bit analog digital converter with 21 levels from 0000000000 to

  
  <EMI ID = 39.1>

  
the highest, as indicated by the peak value register, and it would have an additional 12 dB of dynamic since the lowest level would now be Vin. instead of Vin / 256. Levels

  
  <EMI ID = 40.1>

  
read only one comparator). The number of neighboring levels

  
of zero that can be added is limited by the noise of the system and as long as there is always the same relative precision for all the levels of the digital-analog converter, the performance of the system is

  
increased to cover another 12 dB of dynamics.

  
Figure 12 shows the signal-to-noise ratios s / B for 17-level and 21-level systems using al- <EMI ID = 41.1>

  
The adaptive algorithm described above. improves frequency response and dynamics for a given sampling rate. It only works on the absolute value of the input signal and behaves identically, regardless of the frequency.

  
Another element can be added which allows the system to modify the adaptation on the basis of the input frequency. This additional element detects that the input frequency exceeds a frequency at which the analog-to-digital converter can follow the input signal precisely and it modifies the adaptation by suppressing more levels around zero. This will increase the noise for high frequency input signals but will allow the input signal to be tracked to higher frequencies. A modification making it possible to benefit from this possibility consists in adding to the circuit of figure 10 the circuit which is represented on figure 13. This circuit compares

  
the sign bit of the input signal (produced by a comparator 110) with the quantized sign bit (coming from the digital-analog converter 96) over a period of
32 samples, determined by a 4-bit counter

  
112. In the case where the compared bits are different for more than 50% of the samples, the system does not follow the input signal precisely and the adaptation is modified by the suppression of more levels. This system allows the analog-to-digital converter to track the input signal by first using

  
10 active levels, then reducing the number of levels to 8, 6 and 4, as determined by the 6-bit counter 114, the two-bit counter 116 and the decoder
118. See the table below:

  

  <EMI ID = 42.1>


  
This creates switching points in the vicinity of

  
  <EMI ID = 43.1>

  
teme stops following.

  
We could also modify the system so that it starts using all 17 (or

  
21) levels and then deletes levels when it detects that it is no longer following the signal. This dynamically modified adaptation has a fast "attack" time (32 samples) but must have a long "decay" time (defined by the 6-bit counter 114) so as to remain stable. Figure 14 shows the answer

  
  <EMI ID = 44.1>

  
Another area for possible improvement lies in the digital processing of the signal which is constituted by the results of the analog-to-digital converter. Candy et al., Supra, described the use of a calculation filter, of average to reduce the output frequency of the analog-digital converter and Kuwahara et al., In the article "Interpoiative PCM CODECS with Multiplexed Digital Filters ", page 174, Proceedings
1980 IEEE International- Solid-State Circuits Conference, February 1980, describes the use of an averaging filter to reduce the output frequency to

  
4 times the frequency of the final output signal, then

  
  <EMI ID = 45.1>

  
filter the lower frequencies. However, two key points are overlooked in these prior art techniques. The first is that the sampling rate is reduced by the sampling rate reduction filters and that the most important task of the filters is to ensure that the frequency components which are folded back into the bandwidth

  
are properly attenuated. If components located in the bandwidth have an attenuation distortion, this distortion can be corrected in a filter operating at the final sampling rate.

  
or in the vicinity thereof. Averaging filters do not actually provide adequate attenuation of out-of-band signals.

  
The second point is that the sampling frequency reduction filter which is used with the analog-digital converter must ensure an adequate attenuation of all the bands of width 2F pass. around all the aliasing frequencies. One way to achieve this performance is to place multiple transmit zeros at all aliasing frequencies. Figure 15 shows a filter capable of doing this. This filter includes an arithmetic processor 120, a read-only memory of coefficients

  
  <EMI ID = 46.1>

  
  <EMI ID = 47.1>

  
RS output. The equation of the filter is:

  

  <EMI ID = 48.1>


  
  <EMI ID = 49.1>

  
final digital filter to perform any signal shaping. This filter includes the combination of all of the sampling rate reduction stages that are necessary to reduce the sampling rate to
16 kHz.

  
This filter provides protection against out-of-band components which is considerably superior to that of an averaging filter and allows the use of only a single, single pole filter upstream of the analog-to-digital converter. Filter also processes more than N terms for reduction

  
of frequency of N and it makes it possible to obtain a resolution and a higher dynamic range for the same analog-digital converter. The idea of processing more than N terms in a frequency reduction filter requires that the filter has some memory, but this requirement can be kept to a minimum, as indicated by the embodiment which is shown in Figure 16 This embodiment comprises a single filter stage with an output signal at 16 kHz, in place of the circuit described above which operates with several simple filters reducing the sampling rate by means of several intermediate stages. The output signal from the analog-to-digital converter is used in three different summations which are stored in memory.

   In addition, the output signal of the analog-digital converter is multiplied by three different constants and it is added to each summation. Summons are completed at different times after the start of a new summation.

  
Thus, in summary, an analog-digital interpolation converter can be perfected using any of the following three independent techniques: (a) addition of a second comparator to obtain an additional 6 dB (8.5 dB) dynamics and an additional 6 dB of resolution at a given sampling rate, (b) addition of an adaptation technique, to allow better monitoring of high frequency signals and to obtain as much additional dynamics as necessary , the only limitation coming from the noise of the system; or (c) modifying the frequency reduction filter to replace an averaging filter with a filter that provides more attenuation around the aliasing frequencies and with a filter that processes more samples to improve dynamics and resolution and to reduce noise.

  
A finite impulse response filter can be designed for the output signal from an interpolated analog to digital converter using the fact that the output signal from the analog to digital converter can be converted to a code that contains only one "1 ". The filter can be achieved by using only additions and offsets and the number of additions is equal to the number of coefficients. The memory capacity is greatly reduced because each sample affects only a few output words. For example, in a 20 tap filter with a frequency reduction of 8, each input sample is used only to calculate two or three output samples, instead of twenty. Therefore, one can keep a revolving sum of a.Ax. and there is no need to save the input sample.

   The input sample is multiplied by a. for the sum n [deg.] l, by

  
  <EMI ID = 50.1>

  
When the summation contains 20 values it is presented as output and the corresponding memory register is erased. This multiplication can be done using a fully parallel shift network or a tap shift register.

  
A fully parallel offset using a parallel offset circuit and a parallel adder allows each multiplication to require only one clock period. A filter with 20 sockets

  
with an output frequency of 32 kHz requires an addition rate of 640 kHz. If a 2 MHz system clock were available, this offset circuit and this adder would be available to perform an additional 1,360,000 operations per second. A simple para) _lele structure using one-bit adders and a 10-gate network requires 2 shift registers and

  
one adder for each sum or 6 shift registers and 3 one-bit adders in total. A length

  
16-bit word processor would require a 4 MHz clock (assuming a 512 kHz sampling rate).

  
Digital processing basically performs a low-pass filtering function to remove

  
the high frequency error components in the output signal of the analog-digital converter,

  
without attenuation of the signals in the band. The signal processor output signal can have a much lower sampling rate than the converter if the high frequency components are removed. This sampling rate reduction filter function is generally accomplished by finite impulse response filters since the number of calculations can be reduced so as to calculate only the output samples at the output sampling rate. Although most systems use an averaging filter of one

  
simple type to average N samples and reduce the frequency by a factor of N, the technique

  
of the averaging filter does not provide adequate attenuation of out-of-band signals and it is necessary to use more complex filters which require certain multiplications in addition to the additions,

  
and there is a hardware problem.

  
The following is a description of techniques, in accordance with the invention, which use simple processing

  
and at low speed to accomplish complex filtering operations.

  
The analog-to-digital interpolation converter which is represented in FIG. 5 comprises a limited set of digital codes which are:

  
  <EMI ID = 51.1> a 17-level system. However, these codes are closely related and can be changed slightly to make them useful for special filter structures. The modification of the code calls for a modification of the digital-analog converter in the encoder so that the least significant bit (LSB) is doubled and has a value equal to that of the second bit. If this is done, the actual output signals from the digital-to-analog converter are equivalent to

  
  <EMI ID = 52.1>
- 100000000. The logic circuit intended to convert the codes of the shift register to the new digital format is represented at 156 in FIG. 17. This new code has the following advantages: (a) each code contains a single 1 (or a single 0) ) and (b) each code is exactly double the code immediately below
(except for the code above zero). These characteristics can lead to several original filter structures. Although filters are generally made using expensive multipliers and adders, this filter can be made with a simple serial adder, two shift registers and 8 AND gates, as shown in Figure 17.

   The coefficient word formed by 8 bits is loaded into the shift register 154 from the read-only memory 152 and it is effectively shifted by N bits by the gate network which takes a bit from the shift register as a function of the exit code. of the analog-to-digital converter. When the coefficient is shifted in the shift register 154, it is shifted by M positions by the gate network 156 and it is added to the previous summation which is recorded in the register 158. After M operations of this type, the multiplication and the accumulation of this sample is completed (with M = 8 bits plus the coefficient width
(W) plus any bits provided in case of overflow). If the registers are less than 8 + W in length, the results are truncated.

  
After n accumulations of this type, the register

  
  <EMI ID = 53.1>

  
in the register is then presented as output and the new summation is started by invalidating the reaction gate FG for the first accumulation of a new sample. This simple serial structure works well if the sample rate reduction filter

  
  <EMI ID = 54.1>

  
greater than or equal to n. However, for most general impulse response frequency reduction filters

  
  <EMI ID = 55.1>

  
each input sample must be part of several output samples. Figure 18 shows an example

  
  <EMI ID = 56.1>

  
n = 23. In this case, we must keep revolving sums

  
  <EMI ID = 57.1>

  
system uses 16-bit shift registers continuously receiving a clock signal at 2.048 MHz and each summation is performed out of phase with the others at a rate of 48 kHz, so that the total results are available at the rate of

  
16 kHz.

  
This filter structure can be realized in another way by using a parallel adder and a multiplexer / shift network. The shift multiplexer / shift network makes it possible to shift an input word by M positions. If the input word is the appropriate coefficient and if the shift network is controlled by the analog-to-digital converter, the output signal of the shift network

  
  <EMI ID = 58.1>

  
shift network is added to the sum of the previous values of a.x. until the required number of samples is summed. As with the serial adder technique, if n samples are used in the filter and the sampling frequency reduction ratio

  
  <EMI ID = 59.1>

  
be part of n / R summations. Thus, the example used for the serial technique can also be applied to a parallel technique, as shown in Figure 19. In

  
this case a parallel arithmetic and logic unit (UAL)

  
and the nSD shift network can be used for other arithmetic processing when they are not used for the filter considered. In this example, the processor must perform three shift operations

  
and addition which can be carried out in three clock cycles at a rate of 256 kHz, or at an addition rate of 760 kHz. If the shift and addition structure can operate for example at 2.048 MHz, its capacity is only used at 37.5% and it can perform

  
many other mathematical operations.

  
The output signal from the interpolation analog to digital converter drives an offset network

  
which simply consists of a multiplexer with M inputs.

  
A network bit is shown at 156 in Figure 17

  
which shows that the network can easily be attacked

  
by the code containing a 1. A conventional multiplexer can be used in the case where the output signal of the analog-digital converter is coded. This can be done by using a priority encoder which decodes the position of the unique 1 and which compresses the code to M bits to give a code with a width of logo M, i.e. a code of 9 15-bit is compressed into 4-bit code. This compressed code can attack conventional multiplexers.

  
Another type of filter can also be produced by noting that the successive output signals of the analog-digital converter are mutually linked. If the present code is known, the previous sample must necessarily have been half, double or the opposite of the present code, in the case of a system with a single comparator. For a system with two comparators, there is an additional possible state corresponding to the equality between the previous code and the present code. The only exception to this corresponds to the case where the code is adjacent to zero and we can eliminate this case by not allowing the existence of a code 0 in the analog-digital converter
(0 is not necessary, because it can be represented by an oscillation between equal positive and negative codes).

  
Because there are only a limited number of possible changes (3 or 4), the previous state may

  
be represented by a 2-bit code in which

  
  <EMI ID = 60.1>

  
only one comparator). Since the preceding samples can be recorded with only 2 bits, a series of samples can be recorded or processed in a simple manner. Two possibilities are to use a combinational logic circuit or a read-only table consultation.

  
The combinatorial circuit shown in Figure 20 is useful for small filters with finite impulse response, an example of which could correspond to a frequency reduction from two to one using a double 0 filter of the form:

  

  <EMI ID = 61.1>


  
We can make such a filter in a combinatorial way

  
  <EMI ID = 62.1>

  
  <EMI ID = 63.1>

  
2 or -1 (for interpolators with a single comparator), the summation has only 9 possible results, one of which cannot exist. We can calculate the result

  
  <EMI ID = 64.1>

  
k.values are generated by the logic circuit which controls the shift register and consist of a two-bit word in which one bit indicates a change of sign (if the sign changes, the other bit is ignored) and the other

  
bit indicates an increase (x2) or a decrease (xO, 5) in the value of the shift register. The combinatorial circuit requires little memory and is very fast but

  
it is limited to very simple filters. Sample value of zero causes problems due to

  
that an additional k value is necessary and that k products are distorted. Therefore, the analog-to-digital converter does not use the value zero and

  
it represents zero by oscillating between +1 and -1, instead

  
+1, 0, -1. There is however no degradation in performance.

  
This technique of using k values

  
can be greatly expanded using ROM. A general filter of the form:
  <EMI ID = 65.1>
 can be rewritten as follows:

  

  <EMI ID = 66.1>


  
The read only memory can be addressed by the k values and it can store the summations. The result is then shifted by n positions, in accordance with what is

  
  <EMI ID = 67.1> Figure 21 shows an example of a 5 tap finite impulse response filter. The ROM is only 49 words in length, since only 49 of the 81 combinations (34) are possible. However, the ROM does indeed have 8 address lines and a decoder is used to reduce the 256 states to 49.

  
  <EMI ID = 68.1>

  
  <EMI ID = 69.1>

  
use in arithmetic with complement to 1) or it is inverted and one adds 1 to it (complement to 2).

  
One can use a future improvement of the system for the filters with linear phase in which the coefficients are symmetrical, that is to say that one has:

  
  <EMI ID = 70.1> <EMI ID = 71.1> two halves. We do this by recording two

  
  <EMI ID = 72.1>

  

  <EMI ID = 73.1>


  
The logic translation circuit applies a

  
  <EMI ID = 74.1>

  
to bring them in a format that allows the same ROM to be used as for the first four coefficients. The ROM for this 8-outlet system is kept at 27 words, the memory capacity is 6 K values (12 bits) and 2 X values (8 to 10 bits) and an adder is required to sum two partial results. However, only one adder is required to make this filter.

  
In the various figures; we designate scales

  
  <EMI ID = 75.1>

  
calibration by RD, shift networks by RSD, registers

  
  <EMI ID = 76.1>

  
  <EMI ID = 77.1>

  
It goes without saying that many modifications can be made to the device described and shown, without departing from the scope of the invention.


    

Claims (1)

1. Analog-to-digital interpolation converter, characterized in that it comprises: an integrator (77) intended to integrate the difference between an analog input signal x (t) and a quantized signal q (t), to produce an integrated signal; a first comparator (78) for sampling the integrated signal at a first sampling frequency and producing first signals having a data state when the integrated signal is positive and another data state when the integrated signal is negative; a second comparator (91) for comparing the input signal x (t) with the quantized signal q (t) and for sampling the results comparison to the first sampling frequency to produce second signals of a data state when the input signal x (t) is greater than the quantized signal q (t) and of another data state when the input signal x (t) is less than the quantized signal q (t); a logic circuit (93) which responds to the first and second signals and which produces a plurality of signals including a sign bit signal, a left shift signal, a right shift signal and a no shift signal; a shift register (98) which reacts to the left shift signal, the right shift signal and the no shift signal and which produces a series of multi-bit binary words, each of these words having a predetermined number of bits and an absolute value which is determined by the signals lag and no lag; a digital to analog converter (80) which reacts to the binary words and the sign bit signal and which converts these binary words to give the quantized signals q (t), these quantized signals q (t) being positive or negative depending on the data state of the sign bit; and a digital signal processing circuit (101) for performing digital filtering of the series of binary words and producing binary output signals at a frequency at least twice the highest signal frequency. the input signal x (t). 2. Analog-digital interpolation converter according to claim 1, characterized in that it further comprises an element (100) intended to record the absolute peak value of the binary words which are produced during each cycle of the input signal x (t); a comparator (102) for comparing the absolute peak value with the absolute value has binary words and incrementing the absolute peak value each time the present absolute value exceeds the absolute peak value; and an adaptive circuit (104, 106) for determining the difference between the absolute peak value and the present value of binary words and for changing the state of the sign bit when the difference exceeds a reference level. 3. Analog-to-digital interpolation converter according to claim 2, characterized in that the adaptive circuit comprises a logic subtractor circuit (104) for subtracting the absolute value of the present value signal from the absolute peak value to produce a difference signal, and a comparator (106) for comparing the difference signal with a reference signal and producing a sign bit change signal intended to be applied to the input of the logic circuit (93) to produce a change of state of the sign bit, thereby improving the frequency response of the system. 4. Analog-digital interpolation converter according to any one of claims 2 or 3, characterized in that it further comprises a circuit (110, 112, 114, 116, 118) which is intended to determine the sign of the input signal, to compare this sign with the sign of each quantized signal q (t) during a predetermined sampling period and to change the value of the signal so that the number of active signal levels of the shift register (98) is changed accordingly. 5. Analog-to-digital converter with interpolation according to any one of claims 1, 2 or 3, characterized in that the signal processing circuit (101) includes a digital filter which includes multiple transmission zeros at all signal refrequency frequencies. S. Analog-to-digital interpolation converter according to claim 5, characterized in that the filter comprises a coefficient recording element, an arithmetic processor intended to multiply the binary words by predetermined coefficients recorded in the recording element of coefficients, an adder and an accumulator to sum and record the products corresponding to the multiplication operation. 7. Analog-digital interpolation converter according to claim 5, characterized in that it further comprises an automatic zero circuit (94) intended to produce an offset compensation signal which is applied to the input of the integrator (77) to compensate for the shifts present in the converter. 8. Analog to digital interpolation converter according to claim 7, characterized in that the automatic zero circuit comprises counters (97, 98) intended to integrate the sign bit of a binary signal which is produced by the signal processing circuit, and a digital to analog converter (96) for converting the output signal from these counters into analog form to produce the offset compensation signal. 9. Analog-to-digital interpolation converter, characterized in that it comprises: an integrator (77) for integrating the difference between an analog input signal x (t) and a quantized signal q (t) to produce an integrated signal; a comparator (78) for sampling the integrated signal at a first sampling frequency and for generating first signals of a data state when the integrated signal is positive and of another data state when the signal-integrates is negative; a logic circuit (93) which reacts to the first signals and which produces a sign bit signal and shift signals; a shift register (98) which reacts to the shift signals and which produces a series of binary words with several bits, each of these words having a predetermined number of bits and having an absolute value which is determined by the offset signals;  a digital to analog converter (80) which reacts to the binary words and the sign bit signal and which converts these binary words to give the quantized signals q (t), these quantized signals q (t) being positive or negative depending on the data state of the sign bit; an element (100) for recording the absolute peak value of the binary words which are produced during each cycle of the input signal x (t); a comparator (102) for comparing this absolute peak value with the present value of binary words and incrementing the absolute peak value each time the present value exceeds the absolute peak value; an adaptive circuit (104, 106) for determining the difference between the absolute peak value and the present value of binary words and for doing so that the sign bit changes state when the difference exceeds a reference level; and a digital signal processing circuit (101) for performing digital filtering of the series of binary words and producing binary output signals at a frequency at least twice the highest signal frequency present in the input signal x (t). 10. Analog to digital interpolation converter according to claim 9, characterized in that the adaptive circuit includes a logic subtractor circuit (104) for subtracting the absolute value of the present value signal from the absolute peak value to produce a difference signal, and a comparator (106) for comparing the difference signal with a reference signal and producing a sign bit change signal for application to the input of the logic circuit (93) to produce a change of state of the bit sign, thus improving the frequency response of the system. 11. Analog to digital interpolation converter according to claim 10, characterized in that it further comprises a circuit (110, 112, 114, 116, 118) which is intended to determine the sign of the input signal, to be compared this sign with- 1 "sign of each quantized signal q (t) during a predetermined sampling period and changing the value of the reference signal so that the number of active signal levels of the shift register (98) is correspondingly changed. 12. Analog-digital interpolation converter according to claim 9, characterized in that the signal processing circuit (101) includes a digital filter which carries multiple transmission zeros at all of the signal aliasing frequencies. 13. Analog-digital interpolation converter according to claim 12, characterized in that the filter comprises a coefficient recording element, an arithmetic processor intended to multiply binary words by predetermined coefficients recorded in the coefficient recording element, an adder and an accumulator for summing and recording the products corresponding to the multiplication operation. 14. Analog-digital interpolation converter according to claim 12, characterized in that it further comprises an automatic zero circuit (94) intended to produce an offset compensation signal which is applied to the input of the integrator (77) to compensate for the shifts present in the converter. 15. Analog-digital interpolation converter according to claim 14, caractéri.sé in that the automatic zero circuit comprises counters (97, 98) intended to integrate the sign bit of a binary signal which is produced by the signal processing circuit, and a digital-analog converter (96) intended to convert the output signal of these counters into an analog form for produce the offset compensation signal. 16.  Analog-to-digital interpolation converter according to any one of claims 10, 11, 13 or 15, characterized in that it further comprises: a second comparator (91) intended to compare the input signal x (t) with quantized signal q (t) and sampling the results of this comparison at the first sampling frequency to produce second signals of a data state when the input signal x (t) is greater than the quantized signal q (t ) and another data state when the input signal x (t) is less than the quantized signal q (t); and in that the logic circuit (93) also reacts to the second signals and can produce an absence of shift signal, the shift register (98) further reacting to this signal of absence of offset.