BE877835A - MULTI-LAYER PRINTED CIRCUIT BOARD AND PROCESS FOR DESIGNING THIS BOARD - Google Patents

MULTI-LAYER PRINTED CIRCUIT BOARD AND PROCESS FOR DESIGNING THIS BOARD

Info

Publication number
BE877835A
BE877835A BE0/196407A BE196407A BE877835A BE 877835 A BE877835 A BE 877835A BE 0/196407 A BE0/196407 A BE 0/196407A BE 196407 A BE196407 A BE 196407A BE 877835 A BE877835 A BE 877835A
Authority
BE
Belgium
Prior art keywords
board
designing
printed circuit
layer printed
circuit board
Prior art date
Application number
BE0/196407A
Other languages
French (fr)
Inventor
H J Reuter
Original Assignee
Contraves Ag
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Contraves Ag filed Critical Contraves Ag
Publication of BE877835A publication Critical patent/BE877835A/en

Links

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0286—Programmable, customizable or modifiable circuits
    • H05K1/0287—Programmable, customizable or modifiable circuits having an universal lay-out, e.g. pad or land grid patterns or mesh patterns
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0296—Conductive pattern lay-out details not covered by sub groups H05K1/02 - H05K1/0295
    • H05K1/0298—Multilayer circuits
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/09372—Pads and lands
    • H05K2201/09454—Inner lands, i.e. lands around via or plated through-hole in internal layer of multilayer PCB
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/095—Conductive through-holes or vias
    • H05K2201/09609—Via grid, i.e. two-dimensional array of vias or holes in a single plane
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/09654—Shape and layout details of conductors covering at least two types of conductors provided for in H05K2201/09218 - H05K2201/095
    • H05K2201/09681—Mesh conductors, e.g. as a ground plane
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09818—Shape or layout details not covered by a single group of H05K2201/09009 - H05K2201/09809
    • H05K2201/09945—Universal aspects, e.g. universal inner layers or via grid, or anisotropic interposer
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/42—Plated through-holes or plated via connections
    • H05K3/429—Plated through-holes specially for multilayer circuits, e.g. having connections to inner circuit layers
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
    • H05K3/4641—Manufacturing multilayer circuits by laminating two or more circuit boards having integrally laminated metal sheets or special power cores

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Structure Of Printed Boards (AREA)
BE0/196407A 1978-08-07 1979-07-23 MULTI-LAYER PRINTED CIRCUIT BOARD AND PROCESS FOR DESIGNING THIS BOARD BE877835A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CH837178A CH630211A5 (en) 1978-08-07 1978-08-07 Method for designing electrically conductive layers for producing printed circuits, as well as a multilayer base material for carrying out the method

Publications (1)

Publication Number Publication Date
BE877835A true BE877835A (en) 1979-11-16

Family

ID=4339288

Family Applications (1)

Application Number Title Priority Date Filing Date
BE0/196407A BE877835A (en) 1978-08-07 1979-07-23 MULTI-LAYER PRINTED CIRCUIT BOARD AND PROCESS FOR DESIGNING THIS BOARD

Country Status (5)

Country Link
BE (1) BE877835A (en)
CH (1) CH630211A5 (en)
DE (2) DE7920553U1 (en)
IT (1) IT1122415B (en)
LU (1) LU81559A1 (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3020196C2 (en) * 1980-05-28 1982-05-06 Ruwel-Werke Spezialfabrik für Leiterplatten GmbH, 4170 Geldern Multilevel printed circuit board and process for its manufacture
FR2512315A1 (en) * 1981-09-02 1983-03-04 Rouge Francois MULTI-LAYER ELECTRIC CIRCUIT BLANK AND METHOD FOR MANUFACTURING MULTILAYER CIRCUITS WITH APPLICATION

Also Published As

Publication number Publication date
IT1122415B (en) 1986-04-23
DE2929051A1 (en) 1980-02-21
CH630211A5 (en) 1982-05-28
DE7920553U1 (en) 1979-10-11
IT7924908A0 (en) 1979-08-03
LU81559A1 (en) 1979-10-31

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Legal Events

Date Code Title Description
RE Patent lapsed

Owner name: CONTRAVES A.G.

Effective date: 19850731