BE860015A - MICROPROCESSOR CONTROL DEVICE FOR TELEPHONE PICKUP - Google Patents

Description

       

    <EMI ID = 1.1> <EMI ID = 2.1>

  
Telephone switching devices today include

  
  <EMI ID = 3.1>

  
  <EMI ID = 4.1>

  
usually a single processor that performs multiple tachas, which

  
  <EMI ID = 5.1>

  
  <EMI ID = 6.1>

  
single processor is the need to use a director program, or a director processor, to control the operation of the

  
  <EMI ID = 7.1>

  
  <EMI ID = 8.1>

  
The aim is to provide a telecommunications switching device which comprises a control device with several processors capable of ensuring the processing of communications in a distributed structure, without requiring a director processor. The object of the invention is more precisely to distribute the functions of processing communications between the various

  
  <EMI ID = 9.1>

  
modular control functions and simplify programming. Such a configuration results in a reduction in the complexity of the switching device, and in an improvement in its reliability.

  
The aim of the invention is generally to simplify the tasks of controlling the control device of a telecommunications switching device, by dividing these tasks between different flights of

  
  <EMI ID = 10.1>

  
respective which belong to a configuration of the distributed type.

  
  <EMI ID = 11.1> <EMI ID = 12.1>

  
  <EMI ID = 13.1>

  
  <EMI ID = 14.1>

  
  <EMI ID = 15.1>

  
main. The invention therefore improves reliability, by replacing auto-

  
  <EMI ID = 16.1>

  
commando.

  
  <EMI ID = 17.1>

  
According to the invention, a control device with several processors

  
  <EMI ID = 18.1>

  
a microprocessor and an instruction memory are associated with each unit, The various instruction memories are programmed so that the associated microprocessors perform part of the overall function of the switching device, so that this global function is distributed among micro-processors. With this configuration, each unit of

  
  <EMI ID = 19.1>

  
are assigned to it, independently and asynchronously with respect to

  
  <EMI ID = 20.1>

  
  <EMI ID = 21.1>

  
global switching. To minimize the time spent on communications between processors, and to reduce the complexity of the <EMI ID = 22.1>

  
ordering statement. In the preferred embodiment, the asynchronous communication channels are defined by interprocessor interfaces which include a temporary data memory which is accessible separately by the two microprocessors of the pair associated with this interface.

  
Another aspect of the invention relates to a device for controlling a telephone exchange which comprises several processing functions.

  
  <EMI ID = 23.1>

  
  <EMI ID = 24.1>

  
dually the memories so that each associated processor responds to input commands by executing particular fractions of the functions

  
  <EMI ID = 25.1>

  
this execution; at least one of the input commands results from functions of the PABX which are performed by other processors, and one at

  
  <EMI ID = 26.1>

  
  <EMI ID = 27.1>

  
processors; the microprocessors are associated in pairs so that they exchange orders, the output orders of one of the microprocessors of the pair constituting the input orders of the other microprocessor; and these orders are transmitted asynchronously through specialized communication channels. between the processors of each pair, so that the processors interact with each other to perform the overall function of the PABX.

  
The invention will be better understood on reading the following description of an exemplary embodiment, and? with reference to the accompanying drawings in which:
Fig. 1 is a general block diagram of a telecommunications switching device which uses an advantageous embodiment of the invention; FIG. 2 is a block diagram which shows the configuration of the processors distributed in the control part of the device shown in FIG. 1; Figure 3 is a block diagram showing the redundant structure <EMI ID = 28.1>

  
control device 55 of the crimp 1; <EMI ID = 29.1> of bus lines for each processor; Figure 5 is a diagram c: which against the thefts of communication which <EMI ID = 30.1> <EMI ID = 31.1>

  
the switching device; FIG. 7 is a block diagram which shows the structure of an interprocessor interface, titled as an example of a special communication channel. Mutual <EMI ID = 32.1> between these elements;

  
  <EMI ID = 33.1>

  
processor; Figure 10 is a diagram. block diagram of a bus line multiplexer <EMI ID = 34.1>

  
bus; Figure 12 is a diagram; block diagram of a high level interface <EMI ID = 35.1>

  
Student; Figure 14 is a block diagram of a low level interface which connects a microprocessor to the switching device; and <EMI ID = 36.1> <EMI ID = 37.1>

  
switching device, as well as others.

  
  <EMI ID = 38.1>

  
  <EMI ID = 39.1>

  
killed by the line circuits 33, 34, the analog trunk circuits 35, and the digital trunk circuits 36. Since the switching device is of the "4 wire" type, the line circuits 33, 34 and the analog junction circuit 35 comprises hybrids, or different couplers.

  
  <EMI ID = 40.1>

  
of the "4-wire" type, usable by the switching device. Furthermore, as will be explained in more detail later, the line circuits
33, 34 and the junction circuits 35 have suitable detection points to indicate the state of the lines or junctions to which they are connected, as well as suitable control points which allow control of their state by the switching device. The digital junction circuits 36 are not used in the context of the invention and are shown only for the sake of completeness. These circuits are intended to provide the direct interface between a digital line of the Tl type and the

  
  <EMI ID = 41.1>

  
coded.

  
In addition to establishing and maintaining "standard communication" connections between lines and trunks, the device may provide additional functions, if desired, and the corresponding hardware is represented by sub-assembly 38. For example, the device can be configured to perform, optionally, functions such as paging people, sending coded calls, multi-port conference calls, etc. Sub-assembly 39 denotes the additional equipment required, for example audio-frequency equipment which is used for the paging function.

  
Appropriate devices receive and store the dialed digits which the controller uses to establish the necessary connections between lines and junctions. This material, designated global-

  
  <EMI ID = 42.1>

  
call dial sions, and coded dial signal receivers

  
  <EMI ID = 43.1>

  
also by the expression * numbering receivers. ”The equipment also includes registers which store the digits in memory as they are received.

  
  <EMI ID = 44.1>

  
it is necessary to use tones which, in the considered embodiment, are produced by the digital tone generators 41. The tones produced by these generators comprise the number tone.

  
  <EMI ID = 45.1>

  
code conversion, and are therefore directly compatible with the switching device.

  
  <EMI ID = 46.1>

  
has a 4-wire digital type configuration and therefore requires a conversion between the analog format present on the lines, the junctions,

  
  <EMI ID = 47.1>

  
  <EMI ID = 48.1>

  
relatively conventional, each converter having a capacity of 24 channels, and carrying out an analog / digital conversion in the direction going

  
  <EMI ID = 49.1>

  
maximum city of 3,088 channels, i.e. 3,072 active channels, and 16 channels devoted to the definition of the tail - Such a device requires about 128 code converters, each having a capacity of 24 channels, which gives

  
  <EMI ID = 50.1>

  
bus lines of this type, and each line consists of a pair of unidirectional bus lines.

  
To route correctly; the signal samples encoded between

  
  <EMI ID = 51.1>

  
network and lines, for the distribution of these samples, a pair of multiplexers is used which includes a multiplexer of the first

  
  <EMI ID = 52.1>

  
level, 49. The low level multiplexer, 48, distributes over time over the

  
  <EMI ID = 53.1> <EMI ID = 54.1>

  
silence in the opposite direction.

  
The 4 bus lines with 772 flights are connected to the switching resolution

  
  <EMI ID = 55.1>

  
  <EMI ID = 56.1>

  
make the connections between cos channels.

  
The configuration of the digital switching network itself is

  
  <EMI ID = 57.1>

  
  <EMI ID = 58.1>

  
line, and Conversely, to "connect" the two lines. Then, during the elementary interval which corresponds to the first channel, the data which come from this channel is recorded in the information memory, and the data contained in the information memory at the address established is also read. by the connection memory, which places the sample of the second vota in the elementary interval of the first channel, so that it

  
  <EMI ID = 59.1>

  
  <EMI ID = 60.1>

  
  <EMI ID = 61.1>

  
samples of the two votes, so that the first channel receives the samples

  
  <EMI ID = 62.1> <EMI ID = 63.1>

  
  <EMI ID = 64.1>

  
to ensure full availability, the information for each channel is written in each of four blocks.

Control device

  
  <EMI ID = 65.1>

  
dial receivers and registers 40, to cause these receivers to collect the dialed digits, and receive the collected digits to establish connections. The controller 55 is also connected to the digital tone generators 31, to the converters.

  
  <EMI ID = 66.1>

  
  <EMI ID = 67.1>

  
bucket 62, to be able to write addresses in the connection memories

  
  <EMI ID = 68.1>

  
operator 66, which generally include an array of indicators or display elements that inform an operator about the status of the device,

  
  <EMI ID = 69.1>

  
determined.

  
  <EMI ID = 70.1>

  
information in the device, for example to modify the assignment

  
  <EMI ID = 71.1>

  
device, comma dos traffic information, etc ... An interface for

  
  <EMI ID = 72.1>

  
  <EMI ID = 73.1>

  
tion of the switching device, can be operated for charging

  
  <EMI ID = 74.1>

  
through the reed, writing the corresponding addresses in the network connection memories. The MIC coded samples which are

  
  <EMI ID = 75.1>

  
between the calling subscriber and the called subscriber. When the processor has established a connection through the Network Intermediate, the network information memories accept the PCM encoded samples from subscriber A during.

  
  <EMI ID = 76.1>

  
at output the previously recorded sample of subscriber 8. The sample of subscriber A is kept in memory until the interval appears.

  
  <EMI ID = 77.1>

  
then presented as output, while a new sample is recorded <EMI ID = 78.1>

  
switching device which constitutes an important aspect of the invention,

  
  <EMI ID = 79.1>

  
functions of the switching device, divided these functions among several volumes of communication processing and distributed the functions divided between several microprocessor control units, In the

  
  <EMI ID = 80.1>

  
line command ot Junctions, to eliminate one of these units from

  
  <EMI ID = 81.1>

  
shown with dotted connections, indicating that it is optional, ot is only used if the operator's console has an auxiliary panel of occupancy lamps.

  
We will now consider an aspect of the importance of the configura-

  
  <EMI ID = 82.1>

  
  <EMI ID = 83.1>

  
  <EMI ID = 84.1>

  
with a program making it possible to accomplish all the communication processing functions * which are assigned to this control unit. The mic-

  
  <EMI ID = 85.1>

  
pace needed. The internal structure of the microprocessor typically includes an address and instruction register, an arithmetic and logic unit, an arithmetic / logic input register, and one or more. <EMI ID = 86.1>

  
  <EMI ID = 87.1>

  
  <EMI ID = 88.1>

  
  <EMI ID = 89.1>

  
jet of read or write operations via a data bus line, in response to the write or read signals R or W

  
  <EMI ID = 90.1>

  
logical sequence which corresponds to a program. the signals representing different instructions are read from the memory part 113a and fed into the processor to control the execution by the latter of a particular type of operation. For example, statements may indicate

  
  <EMI ID = 91.1>

  
data 113b must be read and transmitted to the microprocessor by the data bus line, that some operation must be performed with this data word, and the result must be re-recorded in a position of

  
  <EMI ID = 92.1>

  
are physically removed from memory proper. Likewise, memory areas 113d and 113e are reserved for the addressing of interprocessor interfaces, intended for communication between associated processors.

  
  <EMI ID = 93.1>

  
seur 130-180 has the configuration shown in Fig. 8, i.e. each control unit has its own program memory "comprising an instruction lamp and data memory, and its own memory areas for addressing. the switching device or associated processors.In addition, each control unit has its own

  
  <EMI ID = 94.1> <EMI ID = 95.1>

  
shave distinct, and it executes commands or similar task signals which are received from other processors (zone 113e), under the control of its own programs.

  
Returning to Figure 2, we see that, unlike conventional single-processor configurations, in which the subassemblies

  
  <EMI ID = 96.1>

  
Director, microprocessor control units 130-190 are interconnected by dedicated communication channels that link the associated microprocessors. so that the latter can exchange the necessary information, while operating asynchronously with respect to each other. Thus, each processor can be driven by its own clock which does not have to be phase-locked to the clocks of other microprocessors. In addition, the interactions between the programs of the various microprocessors are notably simplified.

  
In the embodiment shown, these communication paths are established by means of inter-processor interfaces which operate in conjunction with asynchronous simplex communication paths.

  
  <EMI ID = 97.1>

  
that the state control unit has a first inter-processor interface 141 for routing data between the line control unit

  
  <EMI ID = 98.1>

  
to route the data in the reverse direction. Since the interprocessor interfaces are controlled alternately by the sending and receiving control units, depending on whether they receive data from the sending processor, send data to the receiving processor, it can be considered that each interface comprises a sending interface and a receiving interface. By way of example, this configuration has been shown for

  
  <EMI ID = 99.1>

  
  <EMI ID = 100.1>

  
  <EMI ID = 101.1>

  
  <EMI ID = 102.1> <EMI ID = 103.1>

  
  <EMI ID = 104.1>

  
be processors associated by specialized channels, without requiring a master program. The inter-processor interfaces themselves can be designed and implemented in various ways. For example. they can have three parts, as described above and considered here. these three parts being made on a single printed circuit board.

  
In some cases, it may be convenient to design an interface comprising a transmit interface and a receive interface, both of which are

  
  <EMI ID = 105.1>

  
born between the sending interface of a first microprocessor and the receiving Tenterface of a second. The interface can be realized in this way, or by applying the principle of the three parts mentioned above. In the latter case, the omission interface comprises the transmission command and the intermediate memory, the reception interface comprises

  
  <EMI ID = 106.1>

  
transfer include the control circuit which transfers control of the interface between the transmit and receive microprocessors. The essential feature remains that the associated processors have individual access to the interfaces, under the control of their respective programs, while operating in an asynchronous manner with respect to each other.

Line control unit (LMP)

  
Considering now in more detail the architecture which is shown for the control device of FIG. 2, it can be seen that the line control unit 140 has two-way communication paths 141, 142, for communicating with the unit. control unit 130. In the configuration shown, the control unit

  
  <EMI ID = 107.1>

  
The function of a line controller is to provide service to the line circuits by detecting service requests, and transmitting these requests to other control units of the controller. and by exerting a certain control on the line circuits which consists,

  
  <EMI ID = 108.1>

  
  <EMI ID = 109.1>

  
speech mission. For this purpose, the line controller 140 is connected to the line circuits 33, 34 which are themselves connected to the telephone sets 30, 31. The soft line circuits and the two stations

  
  <EMI ID = 110.1>

  
  <EMI ID = 111.1>

  
  <EMI ID = 112.1>

  
memory. In other volumes, an address block of the line control unit 140 (zone 1130 in figure 8) is devoted to the line circuits,

  
  <EMI ID = 113.1>

  
respective lines, so as to indicate the state of the associated line.

  
  <EMI ID = 114.1>

  
ringing on the lines. When the controller determines that the ring signal is to be applied to a particular line, 11 transmit

  
  <EMI ID = 115.1>

  
  <EMI ID = 116.1>

  
the interprocessor interface 141. The line control unit 140 responds by addressing the word which comprises the line circuit considered, and by writing in this word the control point of the line circuit considered, which positions a flip-flop to connect an external ringtone generator

  
  <EMI ID = 117.1>

  
  <EMI ID = 118.1>

  
If the called party answers, the line control unit detects the transition between the on-hook state and the off-hook state during normal scanning.

  
  <EMI ID = 119.1>

  
  <EMI ID = 120.1>

  
  <EMI ID = 121.1>

  
  <EMI ID = 122.1>

  
virtually Instant.

Junction Control Unit (TMP)

  
In order to carry out operations analogous to those which the line control unit performs with respect to the junctions of the switching device.

  
  <EMI ID = 123.1>

  
two-way communication connections 161, 162, with the state control unit, and one two-way connection 163 with the

  
  <EMI ID = 124.1>

  
of the detection and control points of the line circuits, the detection and control points of the junction circuits are addressable as a memory. and control unit memory blocks are assigned to these detection and control points. The operation relating to the junctions being a little more complex than that relating to the lines, each

  
  <EMI ID = 125.1>

  
The junction controller 160 continuously scans the detection points "through the connections 163, to detect significant transitions of the detection points. Upon detection of such a transition, the control unit trunk 160 establishes an appropriate task message, and transmits this message to the control unit

  
  <EMI ID = 126.1>

  
variety of junction types and signaling procedures, the junction control unit shall reduce all the signals corresponding to all types of junction to a common set of standard messages, such as: junction occupation, junction disconnection; stop dialing, etc. On receipt of such a message, the state control unit 130 determines the appropriate action, establishes a command message

  
  <EMI ID = 127.1>

  
Junction 160 control unit, through the interprocessor interface
162. The junction control unit 160 performs its task by writing to the

  
  <EMI ID = 128.1>

  
connections 163.

  
  <EMI ID = 129.1>

  
tion, a register control unit 150 is employed, which includes

  
Bidirectional communication paths which are defined by the Interfaces

  
  <EMI ID = 130.1>

  
state control unit 130 determines that dialed digits are to be received, connects a free receiver to the calling station, and transmits

  
  <EMI ID = 131.1> registers accepts the expected ciphers, and once all the ciphers have been received, it transmits them to the database control unit, via the intorprocessor interface 153, together identification information. The database controller then communicates with the state controller 130 to complete the connection.

Database Control Unit (OMP)

  
The database controller 170 stores in its program memory all of the switching device service category and number translation tables. In response to the aforementioned task message which originates from the register control unit via the interprocessor interface 153 and which requests a translation of the

  
  <EMI ID = 132.1>

  
from case tables (which define the local numbering plan) the

  
  <EMI ID = 133.1> The database commando unit $ receives all digits from

  
  <EMI ID = 134.1>

  
to the tables mentioned above, to determine the interval number

  
  <EMI ID = 135.1>

  
  <EMI ID = 136.1>

  
database request produces an appropriate message that includes this

  
  <EMI ID = 137.1>

  
the interprocessor interface 171.

  
The 170 database commando unit showed that a group of

  
  <EMI ID = 138.1>

  
one of the distributed processors, without it being necessary for this processor to include connections allowing direct control of the switching device. The database commando unit does not have any detection point likely to introduce treatment-related stimuli

  
  <EMI ID = 139.1>

  
  <EMI ID = 140.1>

  
connections with the switching device, although dares are not

  
  <EMI ID = 141.1>

  
database command defines input ports for the introduction of external data into the switching device. These data can for example be entered by the status and maintenance panel 57, the

  
  <EMI ID = 142.1>

  
flexible disk 60, described in relation to FIG. 1. These connections are shown at 176, and the aforementioned elements 57-60 are generally referred to as data terminals.

State Control Unit (SMP)

  
As emerges from the large number of previous references to the state control unit 130, the latter constitutes a central element of the control device, insofar as it communicates with all the other units.

  
  <EMI ID = 143.1>

  
the current activity state of each line, junction and register of the device

  
  <EMI ID = 144.1> <EMI ID = 145.1>

  
switching device. In general, the command unit of consi-

  
  <EMI ID = 146.1>

  
  <EMI ID = 147.1>

  
category of service valid to determine the next state to be

  
take the organ considered. After determining this next state, she

  
  <EMI ID = 148.1>

  
messages from appropriate inter-processor interfaces to associated processors, or by establishing connections in the network. The unit of

  
  <EMI ID = 149.1>

  
their network 162 acts as an interface between the output lines of

  
  <EMI ID = 150.1>

  
connection memories. In the example embodiment considered, the state control unit uses its high level interface area (113c in FIG. 8) to access the network, in order to establish or break connections. The state control unit writes two types of data to the network controller, addressing its high level interface area. The <EMI ID = 151.1>

  
data corresponding to a new connection must be written. The

  
  <EMI ID = 152.1>

  
address. The network controller 152 accepts this information and establishes the connection at the appropriate point in the network cycle. The state control unit can therefore access the network, and address it as a memory, in order to establish connections between the ports of the switching device.

Console control unit (CMP)

  
To create the interface between the control device and one or more operator consoles (16 maximum), the connections indicated <EMI ID = 153.1> <EMI ID = 154.1>

  
operation of the device, and are only installed when desired. The console control unit receives messages that correspond to the operator console pushbuttons, via connections 183, analyzes the messages, and sends back messages that illuminate the appropriate operator console lamps via the connections

  
  <EMI ID = 155.1>

  
control, by the interprocessor interface 180, to maintain

  
  <EMI ID = 156.1> <EMI ID = 157.1>

  
appropriate. The console control unit 180 also receives messages from the state control unit 130 through the interprocessor interface 182, and these messages constitute commands which are issued by the state control unit for The console control unit supports some communications.

  
The console control unit also communicates with the database control unit 170 through the interprocessor interface 174, for example to request category of service information from the desks and receives messages from the control unit. database via the interprocessor interface 175, these messages constituting for example responses to requests for category of service.

Occupancy Lamp Control Unit (BMP)

  
It was previously indicated that the operator's console could optionally include an occupancy panel, to indicate the status and

  
  <EMI ID = 158.1>

  
is effected through the inter-processor interface 191, which communicates to the console control unit requests from the occupancy lamp control unit, and through the inter-processor interface 192, which. communicates requests or messages in the opposite direction. In addition, the occupancy lamp control unit has a simplex communication connection with the state control unit, through the interprocessor interface 193, to enable the state control unit to issue

  
  <EMI ID = 159.1>

  
connect the Busy Lamp Control Unit to the Deskset Busy Lamp Panel (Busy Lamp Panel / Direct Station Selection), and connections 194 show that there can be up to 16 desks corresponding to the occupancy lamp panels.

  
It will be noted in summary that the architecture of the control device which

  
  <EMI ID = 160.1>

  
between processors in the distributed structure, thanks to the existence of

  
  <EMI ID = 161.1>

  
state control. In this case, it is necessary to use two inter-processor interfaces, that is to say one to convey the information in each without.

  
  <EMI ID = 162.1>

  
data, and states, show that there is no more complex situation, in which register and database control units must communicate not only with the state control unit, but also

  
  <EMI ID = 163.1>

  
this function. Note also the existence of the interprocessor interfaces 172 and 173, both of which pass data from the state control unit to the database control unit, indicating that it may be necessary use multiple inter-processor interfaces to ensure proper communication over a path that may be busy. It should also be noted the simplex communication which is established between the state control unit and the occupancy lamp control unit by the interprocessor interface 193, which shows that the interprocessor interfaces can be used. when you want to establish a one-way communication.

  
  <EMI ID = 164.1>

  
state 130, line control unit 140, register control unit 150, trunk control unit 160, control unit

  
database 170, console control unit 180, and busy lamp control unit 190. Each of these control units includes a processor 200 which constitutes the control element of the switching device, a memory 201 which is programmed so that the processor performs the functions assigned to it, and an interprocessor interface 203, to establish communication paths with the associated processors. To increase the overall reliability, each control unit is doubled, as is the structure of the bus lines, so that in the event of failure of the main processor, a corresponding module of the secondary processor can be automatically switched in its place, which ensures continuous operation of the switching device.

   The redundant copy of each 4 microprocessor control unit has elements which are identical to the corresponding elements of the main copy.

  
  <EMI ID = 165.1>

  
a defective item, as needed. Accordingly, the elements of redundant copy 1 have been assigned part numbers which are derived from those of the corresponding elements of copy 0 by adding

  
  <EMI ID = 166.1>

  
  <EMI ID = 167.1>

  
represented by the interprocessor interface 202 <1>. To detect device malfunctions, each processor control unit has two integrated circuit microprocessors. Thus, the integrated circuits 207, 208 constitute the processor 200, and the integrated circuits

  
  <EMI ID = 168.1>

  
integrated are themselves commercially available devices, such as

  
  <EMI ID = 169.1>

  
Sitives can be associated in pairs for the purpose of control, as shown in Figure 3, or used as a single copy in a less complicated device. In the case of use in pairs, each integrated circuit microprocessor of a processor is driven by the same

  
  <EMI ID = 170.1>

  
permanence. As soon as the comparator detects a mismatch, it produces a signal that indicates a potential malfunction of the monitoring device.

  
  <EMI ID = 171.1>

  
Microprocessor 200 (0) has a bus line 212, which is shown as a bidirectional bus line for convenience, which connects it.

  
  <EMI ID = 172.1>

  
213 represents the connections between the interprocessor interfaces 202

  
  <EMI ID = 173.1>

  
associated processors. There is also a second bus line 214, connected between the interprocessor interfaces 202 (copy 0) of the control unit in question, and copy 1 of the associated processors. Thus, if copy 1 of an associated processor is in operation, the bus line structure shown allows this processor to communicate with copy 0 of the processor considered. This redundancy is established processor by processor, so that in the event of a fault in a single processor, it is the only one to be replaced. which leaves spare processors for the remaining part of the controller. We see that the processor 200 '(example 1) has a similar bus line 212'

  
  <EMI ID = 174.1>

  
output bus lines 213 ', 214', which connect it to the respective copies of the associated processors. We can now clearly see the flexibility afforded by this structure of bus lines.

  
  <EMI ID = 175.1>

  
as in processor 200 '(example 1).

  
Figure 4 shows further details of this line structure <EMI ID = 176.1>

  
  <EMI ID = 177.1>

  
note that using this structure, copies 0 and 1 of the memories are replaceable card by card) so that in the event that only one memory card is defective, it can be automatically replaced.

  
  <EMI ID = 178.1>

  
  <EMI ID = 179.1>

  
  <EMI ID = 180.1>

  
  <EMI ID = 181.1>

  
  <EMI ID = 182.1>

  
  <EMI ID = 183.1>

  
  <EMI ID = 184.1>

  
the structure of bus lines that interconnect, the redundant copies of the processors, and the associated processors. By way of example, FIG. 5 shows the structure of bus lines which interconnects the state control unit, generally designated by the reference 130, and the line control unit, generally designated by the reference 140. On saw in relation to Figure 2 that the line control unit communicates only with the state control unit. Therefore, FIG. 5 only shows this part of the structure of the bus lines, and it is obviously understood that the state control unit has additional elements for communicating with other associated processors.

  
Figure 5 shows the redundant copies of the row controller 140, 140 ', and the state controller $ 130, 130', each row and state controller occupying different drawers. in a hardware bay. These drawers are connected by inter- <EMI ID = 185.1>

  
send messages between the do line control unit 140 (copy 0) and the state control unit, the transmission part 141a of the interface

  
  <EMI ID = 186.1>

  
interface 141, has an intermediate memory "in the preferred embodiment, although this memory is not shown in Fig. 5, for simplicity. The receiving part 141'b of the interface 141 is connected to the unit. state control unit 130 by a bus line structure which can be configured to communicate with either of the state control units. Thus, the receiving part
141'b is connected to a bus line extension 22 (example 0), so <EMI ID = 187.1>

  
bus lines are connected to the respective state control units 130,
130 '(copy 0 or copy 1). The bus line extenders222,222 'are simply interface circuits which provide direct current isolation between the microprocessor control units, and will therefore not be described in detail. To allow 31 'control unit

  
  <EMI ID = 188.1>

  
interprocessor face 141 'is connected to the control unit 140' (example 1), and the receiving part 141'b of the interprocessor interface

  
  <EMI ID = 189.1>

  
Interprocessor interfaces 141, 142 ', which transmit information between the state control unit and the line control unit are connected in a similar fashion. Thus, the two copies of each unit

  
  <EMI ID = 190.1>

  
res of the associated control unit, which makes it possible to obtain a configuration capable of functioning, even in the presence of faulty circuits.

  
Processor control of the switching device

  
  <EMI ID = 191.1>

  
each microprocessor and the associated program memory, as well as the structure of bus lines which interconnects the associated processors, we

  
  <EMI ID = 192.1>

  
  <EMI ID = 193.1> <EMI ID = 194.1> figures 3 and 4, a redundant pair is available for the 200 processors, <EMI ID = 195.1> <EMI ID = 196.1>

  
respective processors 200, 200 <1>, to check the operation of

  
  <EMI ID = 197.1>

  
If the latter does not reset timer 4 within the predetermined interval, the timer expires its delay time, indicating that the processor is not operating properly, and applies an appropriate input signal to the processor. fault detection and maintenance results.

  
Figure 6 shows that several bus line extenders con- <EMI ID = 198.1>

  
Interprocessor faces as well as external elements are addressed as memory words. Specific memory address blocks are designated.

  
  <EMI ID = 199.1>

  
addresses, it is in communication with other organs, and not with real memory.

  
Bus line extenders 230, 230 'allow the active microprocessor, among the two redundant units, to communicate with the switching device, through the high level interface 231, 231' which is in the active state , and through the low level interfaces 233-235. The address bits which are generated by the microprocessor are decoded in this circuit chain to bring the processor into contact with the detection and control points 237-
239 which are distributed throughout the switching device. For example, the address bits can be decoded partly in the bus line extender, partly in the high level interface, and partly in the low level interface, which allows the processor to selectively address groups of 8 detection or control points.

   The processor can associate the address with a read signal to monitor the state of a group of detection points through <EMI ID = 200.1>

  
Similar high level interfaces in other hardware bays. Of

  
  <EMI ID = 201.1>

  
  <EMI ID = 202.1>

  
233-231 in drawer 1, or similar groups in other drawers, for example

  
  <EMI ID = 203.1>

  
lower level which are transmitted to the low level interfaces 233-235 actuate one of these interfaces which then chooses one of the groups of 8 CD1-CDY detection or control points.

  
Thus, if a processor is in read mode, a detection point

  
  <EMI ID = 204.1>

  
  <EMI ID = 205.1>

  
high-level face 231 is addressed, and while the appropriate bits address a particular word served by the low-level interface 234, the data that comes from the detection points addresses in group 238 is

  
  <EMI ID = 206.1>

  
  <EMI ID = 207.1>

  
microprocessor is in write mode, it transmits data to the control points by the circuits considered in order to write the desired information at these control points. Thus, in exploration mode, the pro

  
&#65533; Cessor generates the appropriate address to operate the bus line extender 230 and the high level interface 231, and it manipulates the lower order address bits to sequentially operate the low level interfaces 233-235, thereby allows you to explore all the detection points of the considered drawer. The processor then manipulates the appropriate bit of the address to enable a next drawer, and performs a similar operation to explore the points of that drawer. Writing is carried out in the same way, the processor simply implementing the write line instead of the read line.

  
The bus line extenders 240, 240 'show that the processor can communicate with other devices as well. In the example considered, these bus line extenders communicate with an input / output device
241, and with a 242 maintenance display panel. These items are located in the hardware bay, and the 242 maintenance panel provides an indication of the switching device status, while the I / O panel 241 allows a specialist to perform certain actions of

  
  <EMI ID = 208.1>

  
Koran "it was noted from the beginning of the description, the global function of the PBX is distributed among the different microproces-

  
  <EMI ID = 209.1>

  
necessary measure to coordinate their actions. Further details on these mutual relationships will be found later. In order for the description of the invention to be complete, we will first of all proceed to a more detailed description of the elements which have just been considered in relation to FIGS. 2 to 6. In general, the description will proceed taking into account everything. first a more detailed synoptic diagram then a developed diagram of a particular embodiment. However, it should be noted that these details only constitute exemplary embodiments of the elements considered, and that these foods can be produced in various ways, without departing from the scope of the invention.

  
  <EMI ID = 210.1>

  
Reference will now be made to FIG. 7 which represents a more detailed block diagram of an interprocessor interface. Due to the fact that all the interprocessor interfaces, represented in FIG. 2 may be identical, in FIG. 7 only the interprocessor interface 141 is considered, that is to say that which transmits the data between the line control unit 140 and the state control unit 130. As has been described previously generally, the interprocessor interface 141

  
  <EMI ID = 211.1>

  
  <EMI ID = 212.1>

  
connections with the associated copy of the state control unit 140, and these connections include address and parity lines 250, cor-

  
  <EMI ID = 213.1>

  
data and parity lines 251, corresponding to data bits D1-D8, and a DP parity bit. The control signals 252 which pro-

  
  <EMI ID = 214.1>

  
and a write signal. There is also an active item signal
253 which activates the sending part when the microprocessor unit which is connected to this sending part is the active example

  
  <EMI ID = 215.1>

  
  <EMI ID = 216.1> <EMI ID = 217.1>

  
applied on 250 address lines.

  
The receiving part 141b is connected to the two copies of the

  
  <EMI ID = 218.1>

  
  <EMI ID = 219.1>

  
separate lines 258, 258 ', which correspond respectively to the active state of copy 0 and copy 1.

  
We will now consider the intermediate memory, which is divided into two parts which correspond respectively to an intermediate memory

  
  <EMI ID = 220.1>

  
Intermediate memory 260 is random access memory which has a capacity of 15 words, each word comprising 9 bits, that is to say 8 data bits and 1 parity bit. Status word 261 also has 9 bits and in addition to recording

  
  <EMI ID = 221.1>

  
Ready / finished indicator function for the transfer of the command between case processors. Finally, an intermediate memory address multiplexer,

  
  <EMI ID = 222.1>

  
to access particular addresses of this intermediate memory, from the transmission and reception parts.

  
With the exception of the points indicated below, the issuing party
141a generally writes task signals to intermediate memory 141c, while receiving part 141b generally reads

  
  <EMI ID = 223.1>

  
The transmitting part through the connections 251 are applied to the data inputs 264 of the state memory 261 croak of the Intermediate message memory 260. A write signal 265, decoded from the incoming control signals 252, controls the writing. in the state memory 261. Reading or writing in the 15-word Intermediate memory 260, takes place under the control of a read / write signal 266, which is

  
  <EMI ID = 224.1> <EMI ID = 225.1>

  
selected passes through the multiplexer to address the words in memory.

  
  <EMI ID = 226.1>

  
  <EMI ID = 227.1>

  
  <EMI ID = 228.1>

  
interprocessor ready to receive data from the transmitting processor

  
  <EMI ID = 229.1>

  
  <EMI ID = 230.1>

  
appear in the status word.

  
Both sending and receiving parties can read the word contained in state memory, and the corresponding output data 270

  
  <EMI ID = 231.1>

  
  <EMI ID = 232.1>

  
state to determine if the interprocessor interface is available to transfer an order, while the processor of the receiving party can

  
  <EMI ID = 233.1>

  
dres awaiting treatment.

  
The receiving party does not have the ability to write

  
  <EMI ID = 234.1>

  
a command positioning line 272 and a command restore line 273. The restore line 273 allows the receiving processor to restore the status word memory 261, after reading a message in this memory, to retransmit the command to the sending processor. Positioning capability is used primarily in maintenance mode. Finally, a parity check is carried out for both the transmitting part and the receiving part, and there are for each of these parts correct operating lines on which a pulse appears in the event of detection of a parity error. The transmitting part has a single correct functioning line 274, while the receiving part has two, 275, 275 ', which correspond respectively to copy 0 and copy 1.

  
As indicated previously, the interprocessor interfaces constitute asynchronous communication channels which connect the associated processors, and are intended to transfer task signals between

  
  <EMI ID = 235.1>

  
tion. It is now seen that each of the associated processors connected by an inter-processor interface can separately access this interface so that the sending processor can write a message while the receiving processor performs other functions, after which the processor

  
  <EMI ID = 236.1>

  
devoted to recording spot signals. Depending on the complexity of the message, the length of these signals can vary from 2 to 16 words.

  
If the messages are short, a group of messages can be loaded into the interprocessor interface, before transfer to the receiving processor.

  
The first word of each task signal specifies the order which corresponds exactly to a task executed in the receiving microprocessor.

  
The order itself corresponds to a reference code. This order is followed by one or more information words. The number of these words varies from one order to another, but is known by the receiving processor, for each particular type of order. Special order orders and formats are unambiguously defined for issuing microprocessors

  
and receivers. This has the advantage of facilitating the decoding and checking of errors in the command words, as well as of facilitating the debugging and maintenance functions of the switching device. The order code
00 is used system-wide as a stop / no order indicator. The appearance of a word 00 when waiting for a command code means

  
  <EMI ID = 237.1>

  
Transfer of spot signals

  
The normal operation of the controller for transferring a task signal between a sending microprocessor and a receiving microprocessor is as follows. After a sending microprocessor executes a program that outputs a task signal for an associated processor, it reads status word 261 to determine whether the interface

  
  <EMI ID = 238.1>

  
it loads the interface, starting with the intermediate memory of

  
  <EMI ID = 239.1>

  
status word memory 261. The intermediate memory address multiplexer then committees address control of memory 260 between the sending microprocessor and the receiving microprocessor. During its normal cycle of treatment of the parts of the PABX which are

  
  <EMI ID = 240.1>

  
whether there are task signals waiting to be executed. When this micro-

  
  <EMI ID = 241.1> <EMI ID = 242.1>

  
processor is ready to transfer another message.

  
  <EMI ID = 243.1>

  
lower select particular words in the interface.

  
Due in part to the distributed architecture of the

  
  <EMI ID = 244.1>

  
in the interprocessor interfaces are the same for all microprocessors. In a transmitting microprocessor, the recording or writing operation is performed by a subroutine, once a queue

  
  <EMI ID = 245.1>

  
programs. When a microprocessor routine creates task signals for an associated processor, those task signals are loaded into an Interprocessor interface queue in its data memory.

  
  <EMI ID = 246.1>

  
tnterprocessor interface to look for messages awaiting transmission. If such messages exist, this subroutine checks the

  
  <EMI ID = 247.1>

  
bits contained in this memory are at 0 (interface available), the sub- <EMI ID = 248.1>

  
  <EMI ID = 249.1>

  
valid) the order analyzer analyzes the order that corresponds to this word and skips

  
  <EMI ID = 250.1>

  
  <EMI ID = 251.1>

  
previously indicated. If the order is valid, the analyzer processes it as described above. This treatment continues until all

  
  <EMI ID = 252.1>

  
exhausted, after which the receiving processor restores the status word and then returns control to the main program.

  
  <EMI ID = 253.1> <EMI ID = 254.1> of intermediate memory 262 this attacked by a circuit of

  
  <EMI ID = 255.1>

  
responsive to the output states of status word register 292, On

  
  <EMI ID = 256.1>

  
when all bits of the status word register are &#65533; ' 0. Under these conditions, the NAND gate 297, whose output is connected

  
  <EMI ID = 257.1>

  
  <EMI ID = 258.1>

  
transmits the lower order address signals SA1-SA4 which come from the microprocessor ('! transmitter.

  
  <EMI ID = 259.1>

  
that it transmits the address signals of the receiving part RA1-RA4, which will be considered below. In both cases, the address signals are transmitted; \ the intermediate memory 260,

  
  <EMI ID = 260.1>

  
bind with the :, four lower order address bits, and

  
  <EMI ID = 261.1>

  
  <EMI ID = 262.1>

  
the selected word from the message buffer. For the last step of loading an interprocessor interface, the transmitting microprocessor addresses the status word by showing the value uOOO for the four order address bits

  
  <EMI ID = 263.1>

  
  <EMI ID = 264.1>

  
  <EMI ID = 265.1>

  
  <EMI ID = 266.1>

  
detects the presence of a non-zero status word, and then switches the control of the intermediate memory address multiplexer 262, to pass it from the transmitting microprocessor to the receiving microprocessor.

  
We will now consider the receiving part which is <EMI ID = 267.1>

  
  <EMI ID = 268.1>

  
on the inputs of a group of 2/1 300 multiplexers, which act as selectors to transmit the signals coming from

  
  <EMI ID = 269.1>

  
selection is made by the output signal of a driver circuit 301, which receives as input the signal ACT * / 1, which reflects the active state of copy 1. The active transmitter signal SACT * provides a general validation signal, and is produced

  
  <EMI ID = 270.1>

  
sister. The SACT * signals are applied by a changeover switch 302 on

  
  <EMI ID = 271.1>

  
receive the ACT * signals for copies 0 and 1, inverted respectively by gates 309 and 301. The output of NAND gate 304 drives the enable input of the selectors

  
  <EMI ID = 272.1>

  
SACT * corresponds to the active state, and if either of the

  
  <EMI ID = 273.1>

  
As in the case of the transmitting part, the bits

  
  <EMI ID = 274.1>

  
  <EMI ID = 275.1>

  
transmitted on input A of a type 1/4, 307 decoder (figure gel. This decoder is validated by a low state signal applied

  
  <EMI ID = 276.1>

  
receives the RPL reading pulse which comes from the microprocess

  
  <EMI ID = 277.1>

  
When the treatment comparator bind; communications 305 indicates a coincidence, and assuming the comparator of

  
  <EMI ID = 278.1>

  
selector 307 is enabled, which enables an AND gate 314 which

  
  <EMI ID = 279.1>

  
  <EMI ID = 280.1>

  
the transmission of data signals between the interprocessor interface and the copy data output lines 0, D1 / 0-D7 / 0 and DP / 0. On the contrary, when the control signal corresponding to copy 1 is active, an AND gate 316 is enabled, to enable the drivers 317, corresponding to the data of copy 1.

  
Data to be transmitted by circuits

  
  <EMI ID = 281.1>

  
which receive on a first group of inputs the 8 bits of

  
  <EMI ID = 282.1>

  
  <EMI ID = 283.1> a second group of inputs the output signals of a register

  
  <EMI ID = 284.1>

  
primary and secondary status word will be described later-

  
  <EMI ID = 285.1>

  
  <EMI ID = 286.1>

  
mayor 292.

  
The multiplexer selection input 318 is connected.

  
  <EMI ID = 287.1>

  
controlled by Ion four lower order address bits, inverted in selector 300. Thus, when all these bits are

  
  <EMI ID = 288.1>

  
data from; from the secondary status word register to the

  
  <EMI ID = 289.1>

  
  <EMI ID = 290.1>

  
commanded by: a selection entry "the way to transmit the received addresses, to address the words chosen in the memories 288.

  
  <EMI ID = 291.1>

  
Intermediate Message Memory and Status Word Memory), as well as the structure which allows the receiving microprocessor to read the data contained in this interface. It is clear that address control of the interprocessor interface memory is transferred by hardware, within the interprocessor interface, between the sending microprocessor and the receiving microprocessor. This transfer takes place more particularly under the command of the decoding circuit.
296 which is sensitive to the conditions of the status word register
292. When the register contains a zero value, the addresses <EMI ID = 292.1>

  
error.

  
  <EMI ID = 293.1>

  
  <EMI ID = 294.1> <EMI ID = 295.1> <EMI ID = 296.1> <EMI ID = 297.1> <EMI ID = 298.1>

  
  <EMI ID = 299.1>

  
write signal applies a clock signal to the. rocker

  
  <EMI ID = 300.1>

  
also possible to apply a clock signal to these lows

  
  <EMI ID = 301.1>

  
  <EMI ID = 302.1>

  
As it was indicated previously, when the flip-flop 344 receives a clock signal while its input D is in the high state "it partially validates the NAND gate

  
  <EMI ID = 303.1>

  
  <EMI ID = 304.1>

  
  <EMI ID = 305.1>

  
  <EMI ID = 306.1>

  
  <EMI ID = 307.1>

  
  <EMI ID = 308.1>

  
positive power supply, it reacts by passing its output Q to the low state. Flip-flop 337 is associated with inverters

  
  <EMI ID = 309.1>

  
constitutes a monostable circuit. Near the end of the period of the monostable multivibrator; the output of the inverter

  
  <EMI ID = 310.1>

  
  <EMI ID = 311.1>

  
  <EMI ID = 312.1>

  
reset, which indicates to the transmitting microprocessor that

  
  <EMI ID = 313.1>

  
note that the monostable multivibrator which includes flip-flop 337 cannot receive a clock signal when

  
  <EMI ID = 314.1>

  
  <EMI ID = 315.1>

  
  <EMI ID = 316.1> <EMI ID = 317.1>

  
erroneous transients.

  
Maintenance circuits

  
  <EMI ID = 318.1>

  
  <EMI ID = 319.1>

  
that automatic fault isolation is not an element

  
  <EMI ID = 320.1>

  
receiving part, we see that the incoming address signals

  
  <EMI ID = 321.1>

  
clock every time a parity error is detected during a read or write cycle, and when the micro-

  
  <EMI ID = 322.1>

  
  <EMI ID = 323.1>

  
tifs.

  
To allow the receiving microprocessor to access

  
  <EMI ID = 324.1>

  
  <EMI ID = 325.1>

  
maintenance. The maintenance address for the interprocessor interfaces is defined by an interprocessor interface displacement address for the higher order address bits,

  
  <EMI ID = 326.1>

  
interprocessor considered in address bits A1-A4. A

  
  <EMI ID = 327.1>

  
  <EMI ID = 328.1>

  
rator compares the wired address signals ST5-ST8 with the address bits A1-A4, to produce an enable signal which is applied to the decoding circuit 362, as well as to the decoder 307, of the 4/2 type. When comparator 312 is validated,

  
  <EMI ID = 329.1>

  
function of the active copy of the receiving microprocessor. Thus, the MNTRD maintenance read signals for exam-

  
  <EMI ID = 330.1> <EMI ID = 331.1>

  
  <EMI ID = 332.1>

  
clock of a parity error flip-flop address 373, It

  
  <EMI ID = 333.1>

  
  <EMI ID = 334.1>

  
maintenance comparator described in relation to the reception circuit. When this comparator recognizes the maintenance address, it provides a high output signal which, in combination with an SRPL * receive pulse for the receiving part, enables an AND gate 381 which actuates the

  
  <EMI ID = 335.1>

  
data which is recorded in the error latches of

  
  <EMI ID = 336.1>

  
maintenance mode, in combination with a.-send write signal SMWK * partially validates a pair of NON- gates

  
  <EMI ID = 337.1>

  
and SD2, in order to reset the parity error flip-flops to zero
373, 378.

  
  <EMI ID = 338.1> <EMI ID = 339.1>

  
  <EMI ID = 340.1>

  
  <EMI ID = 341.1>

  
  <EMI ID = 342.1>

  
  <EMI ID = 343.1>

  
this is the case for the transmitting part. "To this extent, the circuit of FIG. 9g can be considered to constitute part of the interprocesscur interface.

  
  <EMI ID = 344.1>

  
these conditions, the gate 389 is enabled so as to transmit the write signal SWR *, when it is produced by the microprocessor, in order to partially enable another pair of

  
  <EMI ID = 345.1>

  
  <EMI ID = 346.1>

  
that it is present, in order to partially validate another pair

  
  <EMI ID = 347.1>

  
The particular gate which transmits the signal is determined by the state of the A9 address bit of the microprocessor. This bit

  
  <EMI ID = 348.1> <EMI ID = 349.1> <EMI ID = 350.1> do give.

  
  <EMI ID = 351.1> <EMI ID = 352.1>

  
  <EMI ID = 353.1>

  
  <EMI ID = 354.1> <EMI ID = 355.1>

  
face which allow a microprocessor to access the parts of the switching device for which it is responsible for processing.

  
As previously indicated generally, the switching device has detection points which provide input stimuli to the controller, and control points by which the controller can produce the desired action in the controller. switching device. In general, it can be said that a processor accesses the associated control and detection points (if there are

  
  <EMI ID = 356.1>

  
  <EMI ID = 357.1> figure G. More precisely "the microprocessor can access <EMI ID = 358.1>

  
high level face 231 or 231 ', and can be accessed through these

  
  <EMI ID = 359.1>

  
from the associated microprocessor, in order to address one of the various lower order circuits, and which conducts the data signals between the microprocessor and the gold circuit.

  
  <EMI ID = 360.1>

  
that more detail of the high level interface, and the grouping of the various circuits, and the assignment of the reference numbers of these figures are in correspondence with the figure

  
  <EMI ID = 361.1> figure IL ", which makes it possible to understand the overall functioning and in figures 13a-13b, which make it possible to study the structure which performs this functioning.

  
It has been indicated in relation to figure 6 that the two examples of a high level interface circuit can <EMI ID = 362.1>

  
  <EMI ID = 363.1>

  
  <EMI ID = 364.1>

  
  <EMI ID = 365.1> <EMI ID = 366.1>

  
  <EMI ID = 367.1>

  
control signals can only pass through selector 505

  
  <EMI ID = 368.1>

  
  <EMI ID = 369.1>

  
  <EMI ID = 370.1>

  
xeurs described previously ..

  
An address parity check circuit 513, and

  
  <EMI ID = 371.1>

  
as word received, to detect possible parity errors.

  
If a parity error is detected, a signal appears. <EMI ID = 372.1>

  
530, and which also controls the correct functioning encoder 511, so that it applies a pulse to the li-

  
  <EMI ID = 373.1>

  
satisfied, the bay enable signal appears on the

  
  <EMI ID = 374.1>

  
which then allows the control signals coming from the active microprocessor to heal. The higher order address bits

  
  <EMI ID = 375.1>

  
  <EMI ID = 376.1>

  
FLE1-FLK8 drawer enable signals, which actuate the respective sub-assemblies of the low level hardware. A detection

  
  <EMI ID = 377.1>

  
drawer validation is active at a given time. If more

  
  <EMI ID = 378.1>

  
a 1 of 8 error signal appears which is returned to a 1 of 8 error flip-flop belonging to the rump of condition word flip-flops, 530. The lower order bits Al- <EMI ID = 379.1>

  
appear as address signals LA1-LA5, which are decoded in internal order circuits. In addition, a level bus interface address parity generator, 535, outputs an appropriate parity bit with each address word.

  
  <EMI ID = 380.1>

  
maintenance access decoding circuit 531, in which they are decoded "to give a MAC maintenance access signal, as well as to a condition word write circuit 532 which controls writing to the flip-flops. word of conditions in

  
  <EMI ID = 381.1>

  
appropriate appears: in the high level interface circuit, it operates this circuit, causes signals to appear

  
  <EMI ID = 382.1>

  
  <EMI ID = 383.1>

  
drawer to lower order circuits, in order to address

  
  <EMI ID = 384.1>

  
After :; have considered the addressing in the interface

  
  <EMI ID = 385.1>

  
when the fault latch is not positioned (signal TRBL), and when the read pulse is absent. To this

  
  <EMI ID = 386.1>

  
gate 518, and appear as low level data LD1-LD8 and LDP on the low level interface. A door

  
  <EMI ID = 387.1>

  
pass the read signal R, the write signal WR and the

  
  <EMI ID = 388.1>

  
  <EMI ID = 389.1>

  
will be described in more detail below, this data is received and processed in accordance with the drawer enable signal, lower order address bits and control bits. <EMI ID = 390.1>

  
valid. Co circuit selects a word among soft, for the trans-

  
  <EMI ID = 391.1> <EMI ID = 392.1> <EMI ID = 393.1>

  
  <EMI ID = 394.1>

  
los words recorded. You can use other for-

  
  <EMI ID = 395.1> <EMI ID = 396.1> <EMI ID = 397.1>

  
The selected address signals which pass through selector 56i are parity checked in the circuit.

  
  <EMI ID = 398.1>

  
  <EMI ID = 399.1>

  
card validation and file address 569. When

  
  <EMI ID = 400.1>

  
maintenance "it causes an active signal to appear on the

  
  <EMI ID = 401.1>

  
  <EMI ID = 402.1>

  
  <EMI ID = 403.1>

  
writing by the associated microprocessor. In cases where the low-level interface does not have to handle a large

  
  <EMI ID = 404.1>

  
the drawer address signals directly, without decoding, to select one of the groups of these points, among five. For this purpose, the drawer address signals FA1-FA5 also appear at the output of the card validation circuit.

  
  <EMI ID = 405.1>

  
selected by multiplexer 561 are also applied to card and drawer address enable circuit 569, so that the drawer read output signals FR and

  
  <EMI ID = 406.1>

  
and in particular at the detection and control points considered.

  
The data which is transferred between the high level interface and the switching device is routed

  
  <EMI ID = 407.1> <EMI ID = 408.1>

  
circulation of "data in the opposite direction does not

  
  <EMI ID = 409.1>

  
  <EMI ID = 410.1>

  
  <EMI ID = 411.1>

  
  <EMI ID = 412.1>

  
active of the associated high-level interface. Data that is contained in condition flip-flops 567 can also be returned from the high-level interface, and

  
a 570 bus line which connects the condition flip-flops to the low-level data memory, to transmit this data

  
  <EMI ID = 413.1>

  
Figures 15a-lbb show the circuits of a particular embodiment corresponding to the block diagram

  
  <EMI ID = 414.1>

  
  <EMI ID = 415.1>

  
  <EMI ID = 416.1>

  
  <EMI ID = 417.1>

  
active high level originating from the respective copies are transmitted through an array of EXCLUSIVE-OR gates, and the output of the EXCLUSIVE-OR gate of copy 1 controls the inputs

  
  <EMI ID = 418.1>

  
EXCLUSIVE OR gate of the final stage produces an HLA signal when one of the high level interface signals is active,

  
  <EMI ID = 419.1>

  
  <EMI ID = 420.1>

  
active.

  
  <EMI ID = 421.1>

  
address signals, we see that the level bus addresses

  
  <EMI ID = 422.1>

  
  <EMI ID = 423.1>

  
  <EMI ID = 424.1>

  
card considered When the input conditions of the Maintenance decoding circuit:; have been satisfied, the output of the

  
  <EMI ID = 425.1>

  
584 (figure 15b). In this gate, the F / M signal is combined

  
  <EMI ID = 426.1>

  
  <EMI ID = 427.1>

  
that this signal is active, the microprocessor can place data on the data line, in order to carry out a

  
  <EMI ID = 428.1>

  
  <EMI ID = 429.1>

  
  <EMI ID = 430.1>

  
appropriate address signal on its address bus line, and this signal passes through the bus line extender, the high level interface and the low level interface, to appear.

  
  <EMI ID = 431.1>

  
  <EMI ID = 432.1>

  
data bus line, to control the status of the eight control points it is addressing. The transition to the active state of a validation signal from: particular card connects <EMI ID = 433.1>

  
  <EMI ID = 434.1>

  
tent in the form of simple flip-flops that data lists can position and reset. Thus, the microprocessor places appropriate 1 or 0 bits in the data word, so that the appropriate flip-flops are set.

  
  <EMI ID = 435.1>

  
on selected lines.

  
Detection points are addressed in the same way, although they are usually constantly explored.

  
  <EMI ID = 436.1>

  
  <EMI ID = 437.1>

  
line circuit board, can be constituted by the outputs of respective loop current detectors, or,

  
  <EMI ID = 438.1>

  
  <EMI ID = 439.1>

  
loop.

  
  <EMI ID = 440.1>

  
  <EMI ID = 441.1>

  
the card and drawer address validation circuit 569 which is shown in the upper right corner of the figure

  
  <EMI ID = 442.1>

  
card tion. To determine whether the detection points should

  
  <EMI ID = 443.1>

  
the object of a write operation, the control signals

  
  <EMI ID = 444.1>

  
works correctly. Under these conditions, the LR read signal or the write signal is passed to the lower order circuits to connect the data lines to the <EMI ID = 445.1> <EMI ID = 446.1>

  
  <EMI ID = 447.1>

  
  <EMI ID = 448.1> <EMI ID = 449.1>

  
  <EMI ID = 450.1>

  

  <EMI ID = 451.1>


  
  <EMI ID = 452.1> <EMI ID = 453.1>

  
a program that moves data between part of a

  
  <EMI ID = 454.1>

  
  <EMI ID = 455.1>

  
  <EMI ID = 456.1>

  
queue must do the following:

  
  <EMI ID = 457.1>

  
outgoing, during the "periods in progress .; the receiving control unit unloads the interprocessor interface (don-

  
  <EMI ID = 458.1>

  
  <EMI ID = 459.1>

  
  <EMI ID = 460.1> may temporarily overload the interprocessor interface to

  
  <EMI ID = 461.1>

  
  <EMI ID = 462.1>

  
command periodically triggers the interface loader program. The interface control circuit periodically checks the queue to see if there are any messages waiting to be sent, and if so, it checks if

  
  <EMI ID = 463.1>

  
  <EMI ID = 464.1>

  
face is available, the drive circuit loads the largest possible number of messages into the face; the facts. followed by a 0 in the immediately next memory position (unless all 16 interface bytes are used).

  
  <EMI ID = 465.1>

  
ready.

  
  <EMI ID = 466.1> <EMI ID = 467.1>

  
order analyzer examines the interprocessor interface to determine neither have it loaded and, if so, analyzes the first order (in byte n "l of the interface), then

  
  <EMI ID = 468.1>

  
which deals with this particular order. This is shown in Table 2 for the database program. This program shows that during the execution of the order analyzer program, the order "number dials normal", corresponding to the

  
  <EMI ID = 469.1>

  
  <EMI ID = 470.1>

  
order has been called. After processing the order, the command returns to the order analyzer program, so that it analyzes the next order contained in the interprocessor interface. All subsequent orders that require processing are processed in this manner.

  
The main program of the receiving control unit

  
  <EMI ID = 471.1>

  
  <EMI ID = 472.1>

  
  <EMI ID = 473.1>

  
When a ready interface is detected, the analyzer rereads the order byte, to ensure its integrity. The byte is the subject of a check which detects whether it only contains 0s (stop / no order) and in the char: where the byte only contains 0s, the analyzer program returns the command in the main program. The parser program uses valid order bytes to call the processing routine

  
  <EMI ID = 474.1>

  
les) which follow the order byte, and perform the function

  
desired, then return the command to the analyzer program, with

  
an address pointer which designates the next order, if any

  
exists one. The parser checks whether the next order byte position is still in the interprocessor interface, and, if so, it reads the order considered * This processing continues until all the messages from order contained in the interprocessor interface, then the parser returns the command

  
in the main program.

  
  <EMI ID = 475.1> <EMI ID = 476.1>

  
Surgery";

  
  <EMI ID = 477.1>

  
  <EMI ID = 478.1>

  
command which are exchanges with the line circuits. For

  
  <EMI ID = 479.1>

  
  <EMI ID = 480.1>

  
  <EMI ID = 481.1>

  
the control unit 140 determines the on-hook / off-hook state of the

  
  <EMI ID = 482.1>

  
control information only from that same state control unit. For all the information that is issued,

  
  <EMI ID = 483.1>

  
line riel considered (equipment position) in a corresponding network elementary slot number. Likewise,

  
  <EMI ID = 484.1>

  
state control 130, the line controller 140 converts the elementary reneau slot number to a hardware address.

Line control and detection points

  
There is a control point and a detection point.

  
  <EMI ID = 485.1>

  
Commando and detection points are the object of opera-

  
  <EMI ID = 486.1>

  
  <EMI ID = 487.1> <EMI ID = 488.1>

  
below:

  

  <EMI ID = 489.1>


  
  <EMI ID = 490.1>

  
detection) and writing (for the command) that we use

  
  <EMI ID = 491.1>

  
  <EMI ID = 492.1>

  
tee below:

  

  <EMI ID = 493.1>
 

  

  <EMI ID = 494.1>


  
  <EMI ID = 495.1> <EMI ID = 496.1> <EMI ID = 497.1>

  

  <EMI ID = 498.1>


  
  <EMI ID = 499.1>

  

  <EMI ID = 500.1>


  

  <EMI ID = 501.1>


  
  <EMI ID = 502.1> <EMI ID = 503.1>

  
switch in the presence of data in the corresponding register

  
  <EMI ID = 504.1>

  
  <EMI ID = 505.1>

  
registers 150 to carry out continuous signaling and

  
  <EMI ID = 506.1>

  
The three bits on the right a tone

  
  <EMI ID = 507.1>

  
reception / transmission. When this tone is emitted, the

  
  <EMI ID = 508.1>

  
  <EMI ID = 509.1>

  
tion checked the detection byte of each register, and

  
  <EMI ID = 510.1>

  
pray, which is determined by the state of the detection byte and

  
  <EMI ID = 511.1>

  
  <EMI ID = 512.1>

  
tion. These programs are called by interruptions.

  
  <EMI ID = 513.1>

  
register numbering sions. These programs are: preparation for pulse omission; passage of the pulses to the high level; return of pulses to low level.

  
  <EMI ID = 514.1>

  
  <EMI ID = 515.1>

  
all significant state changes on the junctions and, regardless of the junction type, indicates these changes in a unique format to the state control unit 130. Analysis of incoming dial pulses and output of the pulses outgoing dialers are not a task of the trunk control unit 160.

  
  <EMI ID = 516.1>

  
four detection points and four control points for each Junction. The meaning of the detection points and

  
  <EMI ID = 517.1>

  
procedures for using these points therefore vary correspondingly "To properly treat each junction,

  
  <EMI ID = 518.1> <EMI ID = 519.1>

  
  <EMI ID = 520.1>

  
Be and interpret the following conditions: occupation of an incoming junction, disconnection of a Junction, stop / authorization of dialing, response of the request, and call to the hook-switch on a Junction. The functions performed

  
by the control unit and Junctions include: occupancy

  
  <EMI ID = 521.1>

  
response, authorization to transmit dialing signals, handset attenuation, recognition or rejection

  
  <EMI ID = 522.1>

  
on hook switch calls. The control unit

  
  <EMI ID = 523.1>

  
  <EMI ID = 524.1>

  
  <EMI ID = 525.1>

  
  <EMI ID = 526.1>

  
a network elementary interval number which must be translated into a junction hardware number (location of

  
  <EMI ID = 527.1>

  
  <EMI ID = 528.1>

  
  <EMI ID = 529.1>

  
  <EMI ID = 530.1>

  
  <EMI ID = 531.1>

  
detection for each junction of the device. These points are the subject of two-ring read and write operations.

  
  <EMI ID = 532.1>

  
memory reserved for this purpose, and access to these addresses is made using the hardware address of the junction in question, as shown below:

  

  <EMI ID = 533.1>
 

  
  <EMI ID = 534.1>

  
Note that each address allows the points corresponding to soft junction "each card material-

  
  <EMI ID = 535.1>

  
  <EMI ID = 536.1>

  
A double reading, or equivalent technique, should be used to read the detection points, in order to eliminate noise due to contact bounce.

  
The four control points and the four control points

  
  <EMI ID = 537.1>

  
and are only differentiated by the read (for a detection point) or write (for a control point) instruction

  
  <EMI ID = 538.1>

  
dant is the following:

  

  <EMI ID = 539.1>


  
  <EMI ID = 540.1>

  
of varies depending on the type of Junction. The control unit

  
  <EMI ID = 541.1>

  
  <EMI ID = 542.1>

  
  <EMI ID = 543.1>

  
the appropriate data at the control points.

  
Attenuator control points:

  
A variable attenuator is associated with each junction, and is placed in the audio-frequency path which connects the junction to the network. This attenuator must be set to a particular level of eight during the initial period of each call. The state control unit 130 determines the level and transmits it to the trunk control unit 160. The latter in turn controls the variable attenuator. by writing two command bytes on the "command tags <EMI ID = 544.1> <EMI ID = 545.1>

  
  <EMI ID = 546.1>

  
  <EMI ID = 547.1>

  
  <EMI ID = 548.1> <EMI ID = 549.1>

  

  <EMI ID = 550.1>


  
  <EMI ID = 551.1> <EMI ID = 552.1>

  
  <EMI ID = 553.1>

  
  <EMI ID = 554.1>

  
such as determining the validity of conditions for authorizing connections, specifying third-party connections, maintaining console call states, placing calls on hold, blocking calls, and time supervision operations.

  
The console control unit 180 maintains bidirectional communication via the., 3 interpro-interfaces

  
  <EMI ID = 555.1>

  
The information exchanged corresponds to the orders of

  
  <EMI ID = 556.1>

  
order 130.

  
  <EMI ID = 557.1>

  
and the activity of "selection buttons on operator consoles (which represent the indications given by the operator).

  
  <EMI ID = 558.1>

  
  <EMI ID = 559.1>

  
operator to determine a nativity of the selection buttons

  
  <EMI ID = 560.1>

  
level of this battery, the buttons due "ejection are represented by 8-bit codes, and a particular code represents

  
  <EMI ID = 561.1>

  
lamps on each operator's desk are controlled by a single exit port per desk. Due to the large number of lamps placed on the operator's desk, and the need

  
  <EMI ID = 562.1>

  
flash, correct operation of any particular lamp requires the transmission of two bytes.

  
The console control unit 180 processes the

  
  <EMI ID = 563.1>

  
  <EMI ID = 564.1>

  
tre 180 must make it possible to assign and process communications in the user group :! correct.

  
Cutting-edge control and detection of desks:
The different entrance and exit accesses of the pupil

  
  <EMI ID = 565.1>

  
detection and control. Each entry / exit access

  
  <EMI ID = 566.1>

  
  <EMI ID = 567.1>

  
memory address is used to send or receive the byte which corresponds to the alley data. To communicate with the corresponding operator panel, the predetermined code bytes are written and read at the level of each access.

  
  <EMI ID = 568.1>

  
1. Ladle reading program: The button reading program explores all the :; input and transmits the command to the appropriate subroutine in the event of detection at the access level of a new action on a pushbutton of an operator panel.

  
2. Call assignment program: The call assignment program considers the operator queue (for each user group), and if there are any waiting calls, it assigns these calls to the operator who has remained free the longest, in the correct user group.

  
3. Time supervision program: The time supervision program periodically checks all the communication states of the consoles, and triggers the appropriate action if the time allowed for the particular state considered is exceeded.

  
4, Desk lamp writing program: This program transmits control information to the desks

  
  <EMI ID = 569.1>

  
the logical operations that must be performed for each particular key pressed, and for each particular state encountered.

  
  <EMI ID = 570.1>

  
allowing the expression of a large part of the work in the form of a tabla called the commando table. The command table defines the :; following states * ;, on :; interpro- interface commands

  
  <EMI ID = 571.1>

  
which are indicated by the order considered.

  
Occupancy lamp control unit Operations ;:

  
The busy lamp controller 190 processes input and output information for one or more Optional operator consoles which include; a panel of occupancy lamps and allow direct selection of station. The control unit 190 detects requests from operator consoles, for the status display of a particular group of telephone sets (hundreds group), and provides the display data for the operator console. operator from which the request originates. The occupancy lamp control unit 190 also detects connection requests made by an operator, by selectively pressing a selector pushbutton which is located next to a particular telephone set lamp located on the operator's desk. operator.

  
The control unit 190 stores in the associated memory <EMI ID = 572.1>

  
190 organized Occupied / Free Information by corresponding groups

  
  <EMI ID = 573.1>

  
write and read nothing predetermined code bytes at each access.

  
  <EMI ID = 574.1>

  
sisters:

  
The busy lamp control unit 190 receives a single command * to process communications by

  
  <EMI ID = 575.1>

  
status request 130. This command contains information that puts

  
  <EMI ID = 576.1>

  
occupation 190. Commando unit 190 issues a single order

  
  <EMI ID = 577.1>

  
contains the DU telephone number which is obtained from- .;

  
  <EMI ID = 578.1> <EMI ID = 579.1> <EMI ID = 580.1> <EMI ID = 581.1>

  
  <EMI ID = 582.1> <EMI ID = 583.1> <EMI ID = 584.1>

  
  <EMI ID = 585.1>

  
(reference code 72) for which the control unit

  
  <EMI ID = 586.1>

  
first-digit translation of the database memories, to obtain the requested data, and then return

  
  <EMI ID = 587.1>

  
One of the main operations "performed by

  
  <EMI ID = 588.1>

  
under the control of a US-order processing program,

  
  <EMI ID = 589.1>

  
and upon receipt of the "normal dialed number" command (74).

  
  <EMI ID = 590.1>

  
the diagram in the table ?. , as it carries over from the legend

  
  <EMI ID = 591.1>

  
after accessing the call number table 300 and reading the

  
  <EMI ID = 592.1>

  
triggers 3 'fulfillment of the function of the switching device which is designated by the instruction part of the word

  
  <EMI ID = 593.1>

  
  <EMI ID = 594.1>

  
  <EMI ID = 595.1>

  
  <EMI ID = 596.1>

  
Table 12 represents the operations performed

  
  <EMI ID = 597.1>

  
on reading the instruction (000) which designates the "standard communication" from an identifier word position

  
  <EMI ID = 598.1>

  
  <EMI ID = 599.1>

  
  <EMI ID = 600.1>

  
conference cation ", in an identification word which is

  
  <EMI ID = 601.1>

  
in the argument part of the identification word specifies whether the

  
  <EMI ID = 602.1>

  
  <EMI ID = 603.1>

  
  <EMI ID = 604.1>

  
Group search function (table 14)

  
  <EMI ID = 605.1>

  
group search, we are looking for a position or a

  
  <EMI ID = 606.1>

  
  <EMI ID = 607.1>

  
database command receives the dialed digits. Table 14 shows the operations that are performed in response

  
  <EMI ID = 608.1>

  
identification that contains the search instruction for

  
  <EMI ID = 609.1>

  
Conversely, we ask the question "is there a free NSN number in the rump". If there is no vacant position in the <EMI ID = 610.1>

  
is returned to the state control unit. If there is a

  
  <EMI ID = 611.1>

  
  <EMI ID = 612.1>

  
  <EMI ID = 613.1>

  
and prepares and sends a call collection order message
(CB), using the basic network slot number of a station that was discovered during the previous operation.

  
  <EMI ID = 614.1>

  
  <EMI ID = 615.1>

  
performed by the database control unit, under the

  
  <EMI ID = 616.1>

  
instruction (011) of an identification word from the

  
  <EMI ID = 617.1>

  
These operations end with the preparation and transmission by the database control unit of a message.

  
  <EMI ID = 618.1>

  
  <EMI ID = 619.1>

  
dialing an abbreviated call number allows you to define a number with several - longer digits, in a table which

  
  <EMI ID = 620.1>

  
  <EMI ID = 621.1> <EMI ID = 622.1>

  
  <EMI ID = 623.1>

  
  <EMI ID = 624.1>

  
numbering signals on the Junction, and completes

  
  <EMI ID = 625.1>

  
  <EMI ID = 626.1>

  
  <EMI ID = 627.1>

  
We will now consider Table 17 which shows the operations performed by the basic control unit of

  
  <EMI ID = 628.1>

  
  <EMI ID = 629.1>

  
  <EMI ID = 630.1>

  
  <EMI ID = 631.1>

  
  <EMI ID = 632.1>

  
  <EMI ID = 633.1>

  
  <EMI ID = 634.1>

  
frequently, or which are performed directly by the unit

  
DMP database order, without further exchange of orders

  
  <EMI ID = 635.1>

  
use the elementary elementary interval number of the call redirection network. This brings into play the direct operation of canceling "heading of (the transitional zone",

  
  <EMI ID = 636.1>

  
  <EMI ID = 637.1>

  
the cancellation of the corresponding section of the transit zone <EMI ID = 638.1> <EMI ID = 639.1>
  <EMI ID = 640.1>
 
  <EMI ID = 641.1>
  <EMI ID = 642.1>

  
tif switching.

  
  <EMI ID = 643.1>

  
standard tion ", we see that the following order message which is

  
  <EMI ID = 644.1>

  
Among the orders omitted by the state control unit <EMI ID = 645.1> <EMI ID = 646.1>

  
busy. The "order message format" column of table 3

  
  <EMI ID = 647.1>

  
  <EMI ID = 648.1>

  
database keeps an occupancy plan which constitutes

  
  <EMI ID = 649.1>

  
busy of the basic network slot number is stored in the database memory and provides data, accessible by the database control unit, concerning the availability of the station or of the link in question, for the reception of calls.

  
Table 4 represents in the form of a flowchart

  
the two segmented operations which are identified by the

  
  <EMI ID = 650.1>

  
standard described above. Thus, the order A2 is discovered and analyzed during the exploration of the interprocessor and receiver interface 141. The order processing subroutine which is called generates and sends the order 6E to the control unit database and occupancy lamps control unit. As shown in Table 4, the subpro-

  
  <EMI ID = 651.1>

  
of states of transmitting to the transmitting interprocessor interface 173 the reference code 62 (by the communication connection established with the database control unit 170). Reference code 162 represents request information

  
  <EMI ID = 652.1>

  
category of service is coded information relating to

  
  <EMI ID = 653.1>

  
comes the call. The format given for the complete order message

  
  <EMI ID = 654.1>

  
previously stated, the second term of this message is the original line network elementary slot number which is supplied by the line controller as part of the original order message . The control unit

  
  <EMI ID = 655.1>

  
sender interprocessor interface 173.

  
Operation "of the basic control unit

  
data table 5) <EMI ID = 656.1> occupancy table that is in a different yardstick of database memory is updated to indicate

  
  <EMI ID = 657.1>

  
me which corresponds to this order, and receives the message "original COS request". The flowchart of table 5 shows that the following steps are: "consultation of the NSN / COS table

  
for the determination of original COS for PI ", and" return

  
of the original COS information by the command message C8 ". This last step triggers the assembly of the command message which is identified by the reference code" C8 ", in the base control unit The latter operates under the dependency of the interprocessor interface loader program, to load the command message into the interproccs- interface.

  
  <EMI ID = 658.1>

  
SMP associated states.

  
State control unit operations

  
(Table 6)

  
The program segment followed shown on the

  
  <EMI ID = 659.1>

  
order which is identified by the reference code "CB", and calls the order processing subroutine to analyze

  
  <EMI ID = 660.1>

  
register available, connects the line circuit to this register, and places the line and tone receivers in "loaded on register" states. Finally, the state control unit loads into a sending interprocessor interface 152 an order message which is identified by the reference code 22, and which represents a "connection for normal call" order.

  
  <EMI ID = 661.1>

  
RMP register land. The format of the full order message that <EMI ID = 662.1>

  
  <EMI ID = 663.1>

  
We will now consider Table 7 whose par-

  
  <EMI ID = 664.1>

  
  <EMI ID = 665.1>

  
  <EMI ID = 666.1>

  
RMP register explores the receiving interprocessor interfaces, and detects the message that is stored in the interface

  
  <EMI ID = 667.1>

  
  <EMI ID = 668.1>

  
for normal call ", is received, and during the command processing routine which is called in response, the specified register is occupied and is prepared to receive the digits

  
  <EMI ID = 669.1>

  
dial tone is returned to the line or

  
  <EMI ID = 670.1>

  
The upper right part of Table 7 shows the program segment that represents the action that is taken next.

  
  <EMI ID = 671.1>

  
of the program, after a short period of time. Under the control of the register exploration program, the control unit

  
  <EMI ID = 672.1>

  
register that has been occupied. When the first digit dialed has been received, the dial tone stops being applied

  
  <EMI ID = 673.1>

  
reference 72 is sent to the database control unit DMP, to request a translation of the first digit. The command message which corresponds to the reference code 72 is then loaded into the sending interprocessor interface 153. The format of the command message which is identified by the reference code 72 is: R / digit / LS8 / MS4.

  
Considering the example of a station-to-station call sequence given above, we see that the list of

  
  <EMI ID = 674.1>

  
programmed rations which are represented schematically by the flowcharts of tables 3 to 6, and of the two parts <EMI ID = 675.1>

  
  <EMI ID = 676.1>

  
  <EMI ID = 677.1>

  
Table 7 is a flow chart of pro

  
  <EMI ID = 678.1>

  
under the control of the interprocessor interface analyzer program, and to make a branch to the order processing subroutine, in response to the reception of the order message which is identified by the reference code 72. The steps of the table 7 correspond to the reference code

  
3B of the station-to-station calling sequence, which

  
  <EMI ID = 679.1>

  
In order to be able to provide information on the expected number of digits, the database control unit DMP has, in the database memory, a first digit translation table 314. Under the control of a subprogram of order processing, the NSN / COS table is addressed with the network elementary interval number (NSN), to provide the user group number

  
  <EMI ID = 680.1>

  
dialer which is thus found, and the first digit dialed, the database control unit determines the expected length of the telephone number, by consulting the

  
  <EMI ID = 681.1>

  
case, based on the user group number and the first digit translation table, the database controller can provide a firm response which indicates that

  
  <EMI ID = 682.1>

  
fres, or more. Any telephone call number whose length is not firmly determined is marked for "hesitation dialing". The database control unit then returns to the register control unit

  
  <EMI ID = 683.1>

  
maximum number of digits in the numbering plan. The register control unit is programmed to

  
  <EMI ID = 684.1>

  
fres, but recognizes a telephone number with <EMI ID = 685.1>

  
One of the characteristics of the switching device

  
  <EMI ID = 686.1>

  
  <EMI ID = 687.1>

  
1)

  
  <EMI ID = 688.1>

  
which zone of the numbering plan, since, according to the invention, a call number dôcigno a function of the switching device. When the set of digits which are assigned as a call number has a function such

  
  <EMI ID = 689.1>

  
and stored in one of the registers of the RMP register control unit, these digits are transferred as a "number

  
  <EMI ID = 690.1>

  
  <EMI ID = 691.1>

  
  <EMI ID = 692.1>

  
switching (standard communication, and other functions <EMI ID = 693.1>

  

  <EMI ID = 694.1>


  
  <EMI ID = 695.1>

  
levels in which the various levels are connected by pointers. Lower level positions record closed

  
  <EMI ID = 696.1>

  
bits, and one byte and two bits that represent an argument

  
  <EMI ID = 697.1>

  
for all function categories of the switching device. The three-bit instruction word II designates by its binary configuration one of the main categories of functions of the switching device. The byte and a half represents an argument of the instruction, and. In the case of the "standard communication function, this argument represents the interval number

  
  <EMI ID = 698.1>

  
group search, abbreviated dialing, and call pickup, the argument part of the identification word <EMI ID = 699.1>

  
  <EMI ID = 700.1>

  
used to establish conference communication connections.

  
  <EMI ID = 701.1>

  
vice, or the argument part of the identification word which corresponds to various functions one uses the byte and a half to register a standard access code which.. constitutes a reference of the particular function to be performed, For example, in the

  
  <EMI ID = 702.1> <EMI ID = 703.1>

  
RMP (which is already connected to receive the digit "of the dial number * 6 previously) must now collect the

  
  <EMI ID = 704.1>

  
"normal dialed number". As in the case of other units

  
  <EMI ID = 705.1>

  
database is controlled by an analyzer program

  
  <EMI ID = 706.1>

  
receiving interprocossor faces, to detect and read the order message "normal dialed number" which is identified by the reference code 72. This order message includes the digits of the dialed number, along with the reference code

  
  <EMI ID = 707.1>

  
  <EMI ID = 708.1>

  
Table 9 shows the development of the order processing routine which controls the database control unit, in response to receipt of the identified order message <EMI ID = 709.1>

  
  <EMI ID = 710.1>

  
to the block of the intermediate level 000/00 (thousands / hundreds).

  
Looking again at Table 9, it can be seen that the designated function which is represented by the binary configuration of the three high-order bits of the identification word corresponds to one of the functions of the switching device which appear in the 6 blocks placed at the bottom of the table
9.

  
In the case of the "standard communication" function, the argument of the instruction consists of the basic network interval number (NSN) of the called party P2.

  
The database control unit assembles the order message which is identified by the reference code

  
standard communication "C9", and loads into the transmitting interprocessor interface 171, under the command of the interprocessor interface loader program, the command message which includes this reference code. As a preliminary operation

  
  <EMI ID = 711.1>

  
the database controller also determines, as shown in Table 12, whether the call diversion feature is in use for the called party. Among the tables and memory areas of the database memory, there is a table called the "transient COS table", which includes a list of all the stations that are in the state of. <EMI ID = 712.1>

  
The transitional table situation makes it possible to determine whether the call diversion function is in service for the called party P2. If this function is not in use, the subroutine that controls the database control unit this branch

  
  <EMI ID = 713.1> <EMI ID = 714.1>

  
In addition to the basic network interval number

  
  <EMI ID = 715.1>

  
  <EMI ID = 716.1>

  
elementary network interval number of the station to which

  
  <EMI ID = 717.1>

  
by the DMP database control unit requires certain service category information on both pos-

  
  <EMI ID = 718.1>

  
Survival category statements, using the called party's reed elementary interval number P2. This information from

  
  <EMI ID = 719.1>

  
command message, and are then used by the state controller to determine whether the category of service that is assigned to the requestor or to the request restricts the establishment of standard communication between aux.

  
State control unit operations

  
(table 10)

  
We will now consider Table 10 which represents in flowchart form the operations of the control unit

  
  <EMI ID = 720.1>

  
  <EMI ID = 721.1>

  
receiving processors, for searching for messages. These operations detect and read the Message that the Database Control Unit previously loaded.

  
  <EMI ID = 722.1>

  
  <EMI ID = 723.1>

  
, state control controls the service category of both <EMI ID = 724.1>

  
  <EMI ID = 725.1>

  
As it was indicated on the occasion of the sequence

  
  <EMI ID = 726.1>

  
a ringing transmission order "intended for the line control unit. The state control unit sends the message payment.

  
  <EMI ID = 727.1>

  
P2 in the busy state. :

  
Line control unit operations

  
  <EMI ID = 728.1>

  
Table 11 illustrates the operation of the line control unit, under the dependence of a program, and more precisely of the interprocessor interface analyzer program which determines the exploration of the interprocessor interfaces.

  
  <EMI ID = 729.1>

  
looking for messages. As indicated on the ta-

  
  <EMI ID = 730.1>

  
receiver 142, the line control unit unloads the command message corresponding to the reference code "03",

  
and recognizes this message as an order of application, from

  
ringing signal on line P2. The line control unit receives the interval number, elementary of the called party's network (either set P2, or the set to which calls originally directed to set P2 are diverted by the function.

  
  <EMI ID = 731.1>

  
network information is converted into a hardware address under the control of a subroutine intended for this use, which

  
  <EMI ID = 732.1>

  
  <EMI ID = 733.1>

  
  <EMI ID = 734.1>

  
  <EMI ID = 735.1>

  
station illustrates the establishment of the bidirectional conversation circuit by the line control unit, and the transmission of orders.

  
The following is a summary of the basic functions of each microprocessor control unit 130,

  
  <EMI ID = 736.1>

  
Functions of the Status Control Unit (SMP)

  
1. Keeping a record of the status of each NSN on the device:
- current situation
-NSN to which it is connected
- connection time
2. Determination, from the current state, of an order, and of the category of service information, of the next state to be assumed by the NSN.

  
3. Issue of orders corresponding to the new states;
- triggering and stopping of ringing to LMP
- busy and disconnection of junction to TMP
- attenuation information to TMP and LMP
- flashing and signaling control <EMI ID = 737.1>
- connection for a certain function, to RMP
- issue of numbers to RMP
- trigger / stop transmission to RMP
- operator call to CMP
- confirmation and status updates for opera- <EMI ID = 738.1>

  
group waiting request to DMP
- category of service request to DMP
- network connection control
4. Keep a table of available registers, and assign registers.

  
5. Maintain a communications queue, for particular NSNs.

  
6. Control of conference networks.

  
  <EMI ID = 739.1>

  
tone pulses.

  
8. Collection of counts and elapsed times relating to traffic and usage counters.

  
  <EMI ID = 740.1>

  
i iy <EMI ID = 741.1>

  
  <EMI ID = 742.1>

  
  <EMI ID = 743.1>

  
frequency pairs).

  
A, Normal numbering. * Number of digits determined

  
  <EMI ID = 744.1>

  
  <EMI ID = 745.1>

  
fixed and variable rates).

  
C. Billing Restriction.

  
  <EMI ID = 746.1>

  
  <EMI ID = 747.1>

  
mined * by an algorithm registered in RMP.

  
2. Apply and cut off the appropriate dial tone "

  
3. End of numbering detection, by hesitation of the requester.

  
4. Detection of calls on the switch hook, and reset of the corresponding register.

  
  <EMI ID = 748.1> <EMI ID = 749.1>

  
  <EMI ID = 750.1>

  
C. Normal end of numbering

  
  <EMI ID = 751.1>

  
(SMP for the suffix)

  
  <EMI ID = 752.1>

  
  <EMI ID = 753.1>

  
A. Repetition of figures collected

  
  <EMI ID = 754.1>

  
C. Recording and authorization of omission by

  
  <EMI ID = 755.1>

  
  <EMI ID = 756.1>

A. SA / NSN

  
  <EMI ID = 757.1>

  
4. Occupation or release of Junctions under

  
  <EMI ID = 758.1>

  
  <EMI ID = 759.1>

  
  <EMI ID = 760.1>

  
  <EMI ID = 761.1>

  
under the commando of SMP.

  
7. Performing the handshake procedure with a remote trunk.

  
8. Translation in a uniform format of the signaling logic.

  
9. Standardization of the interface of all types of junctions in a single uniform format, at the input and output of the control device.

  
  <EMI ID = 762.1>

  
service and characteristics for each component (lines, <EMI ID = 763.1>

  
read groupa searches,

  
13. Retention of repealed numbering information.

  
  <EMI ID = 764.1>

  
of group.

  
15. Ordering automatic identification equipment

  
  <EMI ID = 765.1>

  
  <EMI ID = 766.1>

  
original.

  
  <EMI ID = 767.1> <EMI ID = 768.1>

  
the operator.

  
3. Reading of wing switch closures * -

  
  <EMI ID = 769.1>

ANNEX

  
Table 1
  <EMI ID = 770.1>
 
  <EMI ID = 771.1>
 
  <EMI ID = 772.1>
 Table 3
  <EMI ID = 773.1>
 Table 4
  <EMI ID = 774.1>
 Table 5
  <EMI ID = 775.1>
  <EMI ID = 776.1>
  <EMI ID = 777.1>
 . Table 7
  <EMI ID = 778.1>
  <EMI ID = 779.1>
  <EMI ID = 780.1>
  <EMI ID = 781.1>
  <EMI ID = 782.1>
 Table, 10
  <EMI ID = 783.1>
  <EMI ID = 784.1>

  

  <EMI ID = 785.1>


  
  <EMI ID = 786.1>
  <EMI ID = 787.1>
   <EMI ID = 788.1>

  

  <EMI ID = 789.1>


  
Table 14 <EMI ID = 790.1>

  

  <EMI ID = 791.1>


  
  <EMI ID = 792.1>

  
  <EMI ID = 793.1>

  

  <EMI ID = 794.1>


  
Table 16 <EMI ID = 795.1>

  

  <EMI ID = 796.1>


  
Table 17.


    

Claims (1)

SUMMARY <EMI ID = 797.1> positive Microprocessor control of a PBX, which controls the completion of the this PBX "characterized by the following points, taken alone or in various combinations: <EMI ID = 798.1> processor each comprising a microprocessor; units of separate memories that are associated with the microprocessors respective so that each microprocessor executes par- <EMI ID = 799.1> although these functions are distributed among the units of microprocessor control; and elements that transfer order messages between selected pairs of microprocessors, asynchronously with respect to at least one of a pair of microprocessors. 2. The transfer elements are made up of specialized communication connections between pairs microprocessors, and by elements that allow each processor in a pair to individually access communication connection. 3. Communication connections include temporary memories that receive orders from of one of the microprocessors of a pair, and which transfer then these orders to the other microprocessor of the pair. 4. Communication connections have connection elements with data lines and lines address of the two microprocessors of the associated pair, and elements for decoding the signals of at least one of the address lines, for selective addressing of temporary memories. 5. Communication connections include control elements for choosing address lines one or the other microprocessor of a pair, to effect <EMI ID = 800.1> switching control elements between address lines - <EMI ID = 801.1> <EMI ID = 802.1> data. 9. The different microprocessors include microprocessors of lines, junctions, registers and <EMI ID = 803.1> telephone server linked respectively to lines, junctions, registers and desks; a microprocessor of states which performs the functions of the PBX <EMI ID = 804.1> keeping a record of the current states of the various organs; and a database microprocessor which performs the functions of the PBX which are related <EMI ID = 805.1> 10. It includes several interproceservice interfaces which are intended to transfer order messages <EMI ID = 806.1> database "" and between the database microprocessor, <EMI ID = 807.1> <EMI ID = 808.1> <EMI ID = 809.1> as one * of the main or backup units; him, <EMI ID = 810.1> service and unit out of service, main units and backup being associated with main and backup inter-processor interfaces, to transmit order messages with the respective primary and backup units of the other <EMI ID = 811.1> <EMI ID = 812.1> <EMI ID = 813.1> primary and backup do not require switching <EMI ID = 814.1> <EMI ID = 815.1> and a reed that establishes connections between these accesses, characterized by following painted Ion taken in isolation or in various combinations: ! .. It comprises several programmable microprocessors, each one being programmed so as to perform a respective part of the functions of the switching device; the various microprocessors include a state microprocessor which has its own clock to operate asynchronously with respect to the other microprocessors of the control device, an instruction memory which is <EMI ID = 816.1> the current state of the accesses of the switching device, and modifies this current state in response to the command signals which come from the control device, and which is programmed <EMI ID = 817.1> command "to execute particular functions of the device - <EMI ID = 818.1> <EMI ID = 819.1> <EMI ID = 820.1> <EMI ID = 821.1> <EMI ID = 822.1> <EMI ID = 823.1> <EMI ID = 824.1> <EMI ID = 825.1> <EMI ID = 826.1> <EMI ID = 827.1> <EMI ID = 828.1> <EMI ID = 829.1> <EMI ID = 830.1> <EMI ID = 831.1> <EMI ID = 832.1> properties check the correct operation of each control unit in service, to detect any faults; and <EMI ID = 833.1> The respective sensor is replaced individually and automatically, which ensures the continuity of the operation of the switching device. 3. The microprocessor of each redundant pair of microprocessor control units is connected to the associated inter-processor interface, and the respective microprocessors of a pair are cross-interconnected with <EMI ID = 834.1> that dedicated communication connections connect the two pairs of redundant microprocessors, and the control unit of each pair that is in use can communicate through that connection. IX. A microprocessor-based PBX, characterized by the following points taken individually or in combination: <EMI ID = 835.1> processor operating asynchronously; elements which distribute the functions of the PABX between the different control units, and interconnection elements between pairs of control units which <EMI ID = 836.1> telephone operator. 2 &#65533; Each microprocessor control unit includes a microprocessor, and a memory which controls the microprocessor to perform the functions that are affected; and the interconnection elements include inter-processor interfaces which provide dedicated communication connections between pairs of control units. <EMI ID = 837.1> <EMI ID = 838.1> dre from the latter; the receiving part is connected <EMI ID = 839.1> the latter the order messages received; and each inter-processor interface comprises elements which transfer control between the sending part and the receiving part, to transmit command messages between the respective microprocessors, <EMI ID = 840.1> <EMI ID = 841.1> bidirectional communication between the microprocessors of the pair. <EMI ID = 842.1> there is a line unit which controls line circuits, a junction unit which controls junction circuits, a register unit which processes information <EMI ID = 843.1> translations of call numbers, and a status unit which <EMI ID = 844.1> orders to other units. X. Microprocessor control device for a telephone switching device which comprises a switching network supervised by a reed controller, and which comprises detection and control points which respectively make it possible to receive information relating to the switching network, and to apply information to this network, characterized by the following points taken individually or in various combinations: It includes a first microprocessor which has a memory which is programmed so that the first microprocessor constitutes a state recording device. current communication for all lines, junctions and registers of the switching device, this member further providing the following communication states for the switching device; a second microprocessor which has a second memory which is programmed so that the second microprocessor constitutes a control unit of the detection points, and of writing for the control points of the switching device; a third microprocessor which has <EMI ID = 845.1> <EMI ID = 846.1> <EMI ID = 847.1> <EMI ID = 848.1> microprocessors, in order to coordinate the work done :: by the different microprocessors. <EMI ID = 849.1> <EMI ID = 850.1> <EMI ID = 851.1> and which has "erection and control points that <EMI ID = 852.1> to this network, characterized by the following points taken individually or in various combinations; <EMI ID = 853.1> <EMI ID = 854.1> recording of the current state for all lines, Junctions and registers of the switching device, this <EMI ID = 855.1> vent for the switching device; a second processor which has a second memory which is programmed so that this processor constitutes a controller of a group of registers, so that the latter accept and process the numbering information; a third microprocessor which has a third memory which is programmed so that this microprocessor constitutes a unit for translating call numbers; and several specialized communication channels which are interposed respectively between the first and second, first and third, and second and third microprocessors, to transmit command messages, and thus to coordinate the work which is accomplished by the various microprocesses- <EMI ID = 856.1> <EMI ID = 857.1> <EMI ID = 858.1> had in various combinations: It comprises a state microprocessor which has a memory which is programmed in such a way that this microprocessor constitutes an organ which, in response to the command signals <EMI ID = 859.1> tion; a line microprocessor which has a memory which is programmed in such a way that this microprocessor constitutes a unit for exploring the detection points of several line circuits of the device;) switching, to detect the state of these lines, and to confirm in response to the command signals to the state microprocessor, the memory of the row microprocessor being further programmed so that this microprocessor executes command signals which come from the state microprocessor, by carrying out operations of writing on the control points of the line circuits; a junction microprocessor which has a memory which is programmed so that this microprocessor constitutes a device for exploring the detection points of several junction circuits, in order to detect the state transitions of the junction circuits, and to transmit in response of the command signals to the state microprocessor, the memory of the junction microprocessor being further programmed so that this microprocessor executes command signals which come from the state microprocessor by carrying out write operations on junction circuit control points; <EMI ID = 860.1> <EMI ID = 861.1> <EMI ID = 862.1> <EMI ID = 863.1> <EMI ID = 864.1> <EMI ID = 865.1> <EMI ID = 866.1> <EMI ID = 867.1> <EMI ID = 868.1> in which she can write, when there is a place <EMI ID = 869.1> processor is connected to detection and control points associated with the respective telephone lines, and the <EMI ID = 870.1> instructions that allow him to explore the detection points -.ion and produce spot signals, in response to the passing <EMI ID = 871.1> allows writing to control points of signals <EMI ID = 872.1> <EMI ID = 873.1> be applied on the line considered; and at least one second microprocessor unit has data memory words which can be written to <EMI ID = 874.1> the instruction memory of this second microprocessor unit contains a sequence of instructions which determines a <EMI ID = 875.1> ros interface that correspond to two lines, when it is necessary to establish a connection between these lines. 2. It has several registers, and the memory <EMI ID = 876.1> loaded so that this unit constitutes an organ which, in response to spot signals which come from the first microprocessor unit and which indicate that a given line has just gone off-hook, writes signals in the words of data memory which constitutes the network interface, so that this network establishes a connection between the given line and a free register. 3. It has a dial tone generator, and the instruction memory of the second microprocessor unit is loaded so that this unit constitutes a component which, in response to the spot signals from the first microprocessor unit and that indicate that a given line has just gone off-hook, writes signals to the data memory words that make up the network interface, for that network to establish an <EMI ID = 877.1> numbering " <EMI ID = 878.1> <EMI ID = 879.1> <EMI ID = 880.1> <EMI ID = 881.1> <EMI ID = 882.1> of the distributed type for a telephone switching device, characterized by the following points taken in isolation or in various combinations: A first microprocessor has its own <EMI ID = 883.1> <EMI ID = 884.1> is the only one able to address, as well as second and third <EMI ID = 885.1> <EMI ID = 886.1> can address to read spot signals; the first one <EMI ID = 887.1> ble by another Microprocessor, to read there the task signals which have been written in this client in the form of commands <EMI ID = 888.1> second inter-processor interface comprises an element which is addressable by another microprocessor, to write to it task signals, constituting orders intended to be executed by the first microprocessor. XVI. A telephone switching device, characterized by the following points taken individually or in various combinations: It has several microprocessor control units, each unit having its own clock which operates asynchronously with respect to the clocks of the other units; the device's call handling tasks are broken down into a number of handling functions - <EMI ID = 889.1> <EMI ID = 890.1> <EMI ID = 891.1> <EMI ID = 892.1> <EMI ID = 893.1> <EMI ID = 894.1> <EMI ID = 895.1> transmitting the task signals between the units:.; control <EMI ID = 896.1> <EMI ID = 897.1> <EMI ID = 898.1> <EMI ID = 899.1> <EMI ID = 900.1> respective memories; each memory is loaded separately from <EMI ID = 901.1> input by executing determined parts of the functions of the automatic telephone switch, and produce output orders under the effect of this execution, and at least some of the input commands result from functions of the automatic switch that are performed by other microprocessors, while at least some of the output commands constitute input commands for the other microprocessors, so that all the functions of the automatic switch are distributed among the various microprocessors; the microprocessors are associated two by two in order to apply to a microprocessor input orders constituted by the output orders of the associated microprocessor, and these orders are transmitted asynchronously by specialized communication channels, between the associated microprocessors, in pairs, so that the latter react on each other to accomplish all of the functions of the PABX. XVIII. A method of operating a telephone switching device to perform the processing of <EMI ID = 902.1> in various combinations: Cn splits the functions of this switching device into several parts; we use several units of <EMI ID = 903.1> ves of these microprocessor commando units so as to assign them dos respective parts of split tasks; cn operates the different microprocessor control units mutually asynchronously, to accomdes the respective fractional tasks; we order <EMI ID = 904.1> produce task signals, form of input commands <EMI ID = 905.1> so that it responds to orders from another control unit, <EMI ID = 906.1> <EMI ID = 907.1> of the switching device; and we transmit these orders to <EMI ID = 908.1> microprocessor control " XIX. A method of controlling a telephone switching device which has multiple lines and trunks, registers for collecting the dialed dialing information, and a digital switching network for establishing connections, characterized by the following taken individually or in combinations various: We process all the lines with a first control unit, all the junctions with a second control unit, all the registers with a third control unit, and the network with a fourth control unit; the control units are operated independently so that they continuously process the parts of the switching device which are assigned to them; orders are generated which result from the processing operations; we transmit these <EMI ID = 909.1> <EMI ID = 910.1>