BE692831A - - Google Patents
Info
- Publication number
- BE692831A BE692831A BE692831DA BE692831A BE 692831 A BE692831 A BE 692831A BE 692831D A BE692831D A BE 692831DA BE 692831 A BE692831 A BE 692831A
- Authority
- BE
- Belgium
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
- G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
- G06F7/50—Adding; Subtracting
- G06F7/504—Adding; Subtracting in bit-serial fashion, i.e. having a single digit-handling circuit treating all denominations after each other
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
- G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
- G06F7/50—Adding; Subtracting
- G06F7/501—Half or full adders, i.e. basic adder cells for one denomination
- G06F7/502—Half adders; Full adders consisting of two cascaded half adders
Landscapes
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computational Mathematics (AREA)
- Mathematical Analysis (AREA)
- Pure & Applied Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Computing Systems (AREA)
- Mathematical Optimization (AREA)
- General Engineering & Computer Science (AREA)
- Complex Calculations (AREA)
- Logic Circuits (AREA)
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US52193666A | 1966-01-20 | 1966-01-20 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| BE692831A true BE692831A (US07223432-20070529-C00017.png) | 1967-07-03 |
Family
ID=24078743
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| BE692831D BE692831A (US07223432-20070529-C00017.png) | 1966-01-20 | 1967-01-18 |
Country Status (4)
| Country | Link |
|---|---|
| US (1) | US3454751A (US07223432-20070529-C00017.png) |
| BE (1) | BE692831A (US07223432-20070529-C00017.png) |
| FR (1) | FR1509399A (US07223432-20070529-C00017.png) |
| GB (1) | GB1159978A (US07223432-20070529-C00017.png) |
Families Citing this family (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE1957302A1 (de) * | 1969-11-14 | 1971-05-19 | Telefunken Patent | Volladdierer |
| US4052604A (en) * | 1976-01-19 | 1977-10-04 | Hewlett-Packard Company | Binary adder |
| JPS5557948A (en) * | 1978-10-25 | 1980-04-30 | Hitachi Ltd | Digital adder |
| DE3035631A1 (de) * | 1980-09-20 | 1982-05-06 | Deutsche Itt Industries Gmbh, 7800 Freiburg | Binaerer mos-paralleladdierer |
| US4435782A (en) | 1981-06-29 | 1984-03-06 | International Business Machines Corp. | Data processing system with high density arithmetic and logic unit |
| US4439835A (en) * | 1981-07-14 | 1984-03-27 | Rockwell International Corporation | Apparatus for and method of generation of ripple carry signals in conjunction with logical adding circuitry |
| US4449197A (en) * | 1982-03-10 | 1984-05-15 | Bell Telephone Laboratories, Incorporated | One-bit full adder circuit |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| FR1320034A (fr) * | 1960-12-19 | 1963-03-08 | Ibm | Dispositifs de calcul numérique utilisant un seul type de circuit logique |
| US3075093A (en) * | 1960-12-19 | 1963-01-22 | Ibm | Exclusive or circuit using nor logic |
| US3074640A (en) * | 1960-12-19 | 1963-01-22 | Ibm | Full adder and subtractor using nor logic |
| US3291973A (en) * | 1964-09-22 | 1966-12-13 | Sperry Rand Corp | Binary serial adders utilizing nor gates |
| US3388239A (en) * | 1965-12-02 | 1968-06-11 | Litton Systems Inc | Adder |
-
1966
- 1966-01-20 US US521936A patent/US3454751A/en not_active Expired - Lifetime
- 1966-10-31 GB GB48623/66A patent/GB1159978A/en not_active Expired
-
1967
- 1967-01-18 BE BE692831D patent/BE692831A/xx unknown
- 1967-01-20 FR FR92015A patent/FR1509399A/fr not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| US3454751A (en) | 1969-07-08 |
| FR1509399A (fr) | 1968-01-12 |
| GB1159978A (en) | 1969-07-30 |
