BE679470A - - Google Patents

Info

Publication number
BE679470A
BE679470A BE679470DA BE679470A BE 679470 A BE679470 A BE 679470A BE 679470D A BE679470D A BE 679470DA BE 679470 A BE679470 A BE 679470A
Authority
BE
Belgium
Application number
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Publication of BE679470A publication Critical patent/BE679470A/xx

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/60Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D10/00 or H10D18/00, e.g. integration of BJTs
    • H10D84/611Combinations of BJTs and one or more of diodes, resistors or capacitors
    • H10D84/613Combinations of vertical BJTs and one or more of diodes, resistors or capacitors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/30604Chemical etching
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76Making of isolation regions between components
    • H01L21/762Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76297Dielectric isolation using EPIC techniques, i.e. epitaxial passivated integrated circuit
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10STECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00Metal treatment
    • Y10S148/085Isolated-integrated
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10STECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00Semiconductor device manufacturing: process
    • Y10S438/928Front and rear surface processing

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Element Separation (AREA)
BE679470D 1965-04-14 1966-04-13 BE679470A (en:Method)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US448119A US3411200A (en) 1965-04-14 1965-04-14 Fabrication of semiconductor integrated circuits

Publications (1)

Publication Number Publication Date
BE679470A true BE679470A (en:Method) 1966-09-16

Family

ID=23779076

Family Applications (1)

Application Number Title Priority Date Filing Date
BE679470D BE679470A (en:Method) 1965-04-14 1966-04-13

Country Status (4)

Country Link
US (1) US3411200A (en:Method)
BE (1) BE679470A (en:Method)
GB (1) GB1121334A (en:Method)
NL (1) NL6604875A (en:Method)

Families Citing this family (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3575740A (en) * 1967-06-08 1971-04-20 Ibm Method of fabricating planar dielectric isolated integrated circuits
US3490140A (en) * 1967-10-05 1970-01-20 Bell Telephone Labor Inc Methods for making semiconductor devices
US3844858A (en) * 1968-12-31 1974-10-29 Texas Instruments Inc Process for controlling the thickness of a thin layer of semiconductor material and semiconductor substrate
US3619739A (en) * 1969-01-16 1971-11-09 Signetics Corp Bulk resistor and integrated circuit using the same
US3892033A (en) * 1970-02-05 1975-07-01 Philips Corp Method of manufacturing a semiconductor device
US3716425A (en) * 1970-08-24 1973-02-13 Motorola Inc Method of making semiconductor devices through overlapping diffusions
US3953255A (en) * 1971-12-06 1976-04-27 Harris Corporation Fabrication of matched complementary transistors in integrated circuits
US3979237A (en) * 1972-04-24 1976-09-07 Harris Corporation Device isolation in integrated circuits
JPS5222516B2 (en:Method) * 1973-02-07 1977-06-17
CA1003122A (en) * 1973-04-30 1977-01-04 Lewis H. Trevail Method of making multiple isolated semiconductor chip units
US3911562A (en) * 1974-01-14 1975-10-14 Signetics Corp Method of chemical polishing of planar silicon structures having filled grooves therein
US3969749A (en) * 1974-04-01 1976-07-13 Texas Instruments Incorporated Substrate for dielectric isolated integrated circuit with V-etched depth grooves for lapping guide
JPS5718341B2 (en:Method) * 1974-12-11 1982-04-16
US4095330A (en) * 1976-08-30 1978-06-20 Raytheon Company Composite semiconductor integrated circuit and method of manufacture
US4925808A (en) * 1989-03-24 1990-05-15 Sprague Electric Company Method for making IC die with dielectric isolation
DE4334515C1 (de) * 1993-10-09 1994-10-20 Itt Ind Gmbh Deutsche Verpolungsschutz für integrierte elektronische Schaltkreise in CMOS-Technik
US6476445B1 (en) 1999-04-30 2002-11-05 International Business Machines Corporation Method and structures for dual depth oxygen layers in silicon-on-insulator processes

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3300832A (en) * 1963-06-28 1967-01-31 Rca Corp Method of making composite insulatorsemiconductor wafer
US3290753A (en) * 1963-08-19 1966-12-13 Bell Telephone Labor Inc Method of making semiconductor integrated circuit elements

Also Published As

Publication number Publication date
GB1121334A (en) 1968-07-24
US3411200A (en) 1968-11-19
NL6604875A (en:Method) 1966-10-17

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