BE657858A - - Google Patents
Info
- Publication number
- BE657858A BE657858A BE657858DA BE657858A BE 657858 A BE657858 A BE 657858A BE 657858D A BE657858D A BE 657858DA BE 657858 A BE657858 A BE 657858A
- Authority
- BE
- Belgium
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
- G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
- G06F7/491—Computations with decimal numbers radix 12 or 20.
- G06F7/492—Computations with decimal numbers radix 12 or 20. using a binary weighted representation within each denomination
- G06F7/493—Computations with decimal numbers radix 12 or 20. using a binary weighted representation within each denomination the representation being the natural binary coded representation, i.e. 8421-code
- G06F7/494—Adding; Subtracting
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
- G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
- G06F7/50—Adding; Subtracting
- G06F7/505—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination
- G06F7/506—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination with simultaneous carry generation for, or propagation over, two or more stages
- G06F7/508—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination with simultaneous carry generation for, or propagation over, two or more stages using carry look-ahead circuits
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Computing Systems (AREA)
- Computational Mathematics (AREA)
- Mathematical Analysis (AREA)
- Pure & Applied Mathematics (AREA)
- Mathematical Optimization (AREA)
- General Engineering & Computer Science (AREA)
- Complex Calculations (AREA)
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| GB35664A GB1017314A (en) | 1964-01-03 | 1964-01-03 | Improvements in or relating to adders |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| BE657858A true BE657858A (enrdf_load_html_response) | 1965-07-05 |
Family
ID=9702949
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| BE657858D BE657858A (enrdf_load_html_response) | 1964-01-03 | 1965-01-04 |
Country Status (3)
| Country | Link |
|---|---|
| BE (1) | BE657858A (enrdf_load_html_response) |
| GB (1) | GB1017314A (enrdf_load_html_response) |
| NL (1) | NL6500034A (enrdf_load_html_response) |
-
1964
- 1964-01-03 GB GB35664A patent/GB1017314A/en not_active Expired
-
1965
- 1965-01-04 NL NL6500034A patent/NL6500034A/xx unknown
- 1965-01-04 BE BE657858D patent/BE657858A/xx unknown
Also Published As
| Publication number | Publication date |
|---|---|
| NL6500034A (enrdf_load_html_response) | 1965-07-05 |
| GB1017314A (en) | 1966-01-19 |