BE1023989B1 - Camera set with slow motion system - Google Patents

Abstract

A set for a camera with an image capture system, advantageously slowed down, or a camera for taking pictures, advantageously slowed down, comprising such an assembly, said set comprising: an integrated circuit RAM memory with a high data rate (flux greater than 80 Gigabit / second, especially 85 Gigabit / second at 200 Gigabit / second or more) (B); at least a first programmable logic network for controlling said high data rate RAM integrated circuit memory.

Description

Camera set with slow motion system

The subject of the present invention is a camera assembly with an imaging system, advantageously slowed down, preferably super slowed (SSM) or ultra slow motion (USM), or camera for taking pictures, advantageously slowed down, preferably super slowed down. (SSM) or ultra slow motion (USM) comprising such an assembly, said set being adapted to allow at least both the recording of an image in real time and the vision of a prerecorded image, in particular of the idle type

Cameras are known with slow motion capture systems and live broadcast broadcasting. Such cameras require servers with particular programs. A single Servern is generally unable to control more than one camera in SSM mode with the possibility of live broadcast or substantially live super or slow motion images. In addition, with existing systems, searching for a slowed-down video clip prevents live slow motion. These existing cameras often include memories of the type retranscriptible a few seconds, which can not find on the basis of this memory only slowed images for example after 60 minutes of continuous recording of images. The invention relates to a set or camera to address these problems. The invention thus relates to a camera assembly with an image pickup system, advantageously slowed, preferably super slowed (SSM) or ultra slow motion (USM), or camera for taking images, advantageously slowed, preferably super slowed (SSM) or ultra slow motion (USM) comprising such an assembly, said set being adapted to allow at least both the recording of an image in real time and the vision of a prerecorded image, in particular of the idle type . Said set according to the invention comprises: a high data rate RAM integrated circuit memory (flows greater than 80 Gigabit / second, in particular from 85 Gigabit / second to 200 Gigabit / second or more); At least one first programmable logic network for controlling said high data rate RAM integrated circuit memory (flow greater than 80 Gigabit / second, in particular from 85 Gigabit / second to 200 Gigabit / second or more), said least one programmable logic control network comprising at least the following functions: reception function (A) for receiving uncompressed or substantially uncompressed, possibly amplified RAW format digital image files or raw digital negatives; uncompressed or substantially uncompressed RAW or raw images, optionally amplified, and for conditioning said digital files in a form useful for recording in the high data rate integrated circuit RAM (over 80 Gigabit / second stream) in particular from 85 Gigabit / second to 200 Gigabit / second or more); - digital image signal transformation function (in RAW format or raw uncompressed or substantially uncompressed) at least substantially live (C) to condition the digital image files (in RAW or raw uncompressed or substantially unencrypted format) compressed) into digital image signal / signals (in RAW format or raw uncompressed or substantially uncompressed) transformed or readable at least substantially live, said programmable logical transformation network transferring the digital image signal (s) (into RAW format or raw uncompressed or substantially uncompressed) transformed or readable at least partially directly to a programmable logic output network (F) and to a high data rate RAM integrated circuit memory (over 80 Gigabit / second stream, especially 85 Gigabit / second at 200 Gigabit / second or more) (B) for self recording ns temporary in said memory (B); transcription function (D) receiving transformed / read image signals stored temporarily in the high data rate RAM integrated circuit memory (flow greater than 80 Gigabit / second, in particular 85 Gigabit / second at 200 Gigabit / sec or more), said programmable transcriptional logic network including a function for dividing or chopping, at least as a function of time, the digital image signals (in RAW format or raw uncompressed or substantially uncompressed) transformed or readable into at least one time slot comprising a successive series of digital image signals (in RAW format or raw uncompressed or substantially uncompressed) transformed or readable, said programmable transcriptional logic network (D) further comprising an output adapted to be connected to a memory nonvolatile (34), and -reading function (E) of at least temporal slices of ima signals digital gages (in RAW or raw uncompressed or substantially uncompressed) transformed, said read programmable logic array comprising a read and transfer function of the slice read or slices read to the high-speed RAM integrated circuit memory data (flow greater than 80 Gigabit / second, in particular from 85 Gigabit / second to 200 Gigabit / second or more) (B) to at least store the slice read temporarily, and at least one plug or connection adapted for the connect to the nonvolatile memory (34), and ♦ an output programmable logic array (F), possibly forming part of the first programmable logic control network, but preferably separate from said first programmable logic control network, said programmable logic network of output controlling the image signal (s) / output image signals, including a plug or connection adapted to be connected to a communication unit camera control for transferring the image signal (O); wherein the output programmable logic array (F) includes a function for recovering in the integrated circuit memory (B) the slice (s) read, so that depending on a signal from a camera control unit , the output programmable logic array (F) transmits either one or more signals of the read slice (s), or one or more uncompressed or substantially uncompressed digital image signals (in RAW or raw uncompressed format) from the first programmable logic array via the transformation function (C).

The RAM chip with a high data rate (flows greater than 80 Gigabit / second, in particular from 85 Gigabit / second to 200 Gigabit / second or more) is in particular with a data rate of at least twice, in particular DDR (B)

According to an advantageous embodiment, said assembly according to the invention comprises at least: a high data rate RAM integrated circuit memory (flow greater than 80 Gigabit / second, in particular from 85 Gigabit / second to 200 Gigabit / second , see more); A first programmable logic network for high-speed data memory integrated circuit RAM control (flows greater than 80 Gigabit / second, in particular 85 Gigabit / second at 200 Gigabit / second or more), said first programmable logic network control system comprising at least the following functions: reception function (A) for receiving the digital image files (in RAW format or raw uncompressed or substantially uncompressed), possibly amplified, or digital digital image negatives ( in RAW format or raw uncompressed or substantially uncompressed), possibly amplified, and for conditioning said digital files in a form useful for recording them in the high data rate RAM integrated circuit memory (flow greater than 80 Gigabit / second, in particular from 85 Gigabit / second to 200 Gigabit / second or more); and - at least substantially live signal transformation function (C) for conditioning the digital image files (in RAW format or uncompressed or substantially uncompressed raw) and transforming them into digital image signal / signals (in RAW format or raw uncompressed or substantially uncompressed) transformed or readable at least substantially live, said programmable logical transformation network transferring the digital image signal (s) (in RAW format or raw uncompressed or substantially uncompressed) transformed or readable at least partially live to a programmable logic output network (F) and to the high data rate RAM IC (over 80 Gigabit / second stream, in particular from 85 Gigabit / second to 200 Gigabit / second, or more ) (B), for its at least temporary recording in said high data rate integrated circuit RAM memory (stream greater than 80 Gigabit / second, in particular from 85 Gigabit / second to 200 Gigabit / second or more) (B); A second programmable logic control network for a high data rate RAM integrated circuit memory (flows greater than 80 Gigabit / second, in particular 85 Gigabit / second at 200 Gigabit / second or more), said second programmable logic network control system comprising at least the following functions transcription function (D) receiving digital image signals (in RAW format or raw uncompressed or substantially uncompressed) transformed or read temporarily stored in the integrated circuit memory RAM at high data rate (B), said programmable logic transcription network comprising a function for dividing or cutting, at least as a function of time, the transformed or readable image signals into at least temporal slices comprising a successive series of digital image signals (in RAW or raw uncompressed or substantially uncompressed) transformed or readable, said programmable transcriptional logic network (D) further comprising an output adapted to be connected to a nonvolatile memory (34), and - reading function (E) of at least temporal slices of transformed image signals, said programmable logic array of reading comprising a read and transfer function of the slice read or slices read to high data rate RAM integrated circuit memory (flow greater than 80 Gigabit / second, in particular from 85 Gigabit / second to 200 Gigabit / second, or more) (B) to at least store the slice read temporarily, and at least one plug or connection adapted to connect it to the non-volatile memory (34), and ♦ a programmable output logic network (F) controlling the / image signal / output image signals, comprising a plug or connection adapted to be connected to a camera control unit for transferring the image signal (s) (O). wherein the output programmable logic array (F) includes a function for retrieving high data rate RAM in the integrated circuit RAM (streams greater than 80 Gigabit / second, in particular 85 Gigabit / second at 200 Gigabit / second, or more) (B) the slice (s) read, so that depending on a signal from a camera control unit, the output programmable logic array (F) transmits one or more signals from the read slices, one or more digital image signals (in RAW format or raw uncompressed or substantially uncompressed) transformed from the first programmable logic network via the transformation function (C).

According to a preferred embodiment, said set according to the invention comprises at least: a high data rate RAM integrated circuit memory (flow greater than 80 Gigabit / second, in particular from 85 Gigabit / second to 200 Gigabit / second , or more), advantageously an integrated circuit memory with at least two data rates, in particular of the DDR (B) type; A first programmable receive logical network (A) for receiving the digital image files (in RAW or raw uncompressed or substantially uncompressed), possibly amplified, or digital negatives of images, possibly amplified, and for conditioning said digital image files (in RAW format or raw uncompressed or substantially uncompressed) in a form useful for storing them in the high data rate integrated circuit RAM memory (flows greater than 80 Gigabit / second, in particular 85 Gigabit / second at 200 Gigabit / second or more) (B); A second programmable logic network for transforming the at least substantially live signal (C) to condition the digital image files (in RAW format or raw uncompressed or substantially uncompressed) and transform them into digital image signal / signals (in RAW format or raw uncompressed or substantially uncompressed) transformed or readable at least substantially live, said programmable logical transformation network transferring the digital image signal (s) (in RAW format or raw uncompressed or substantially uncompressed) transformed or at least partially readable directly to a programmable logic output network (F) and to the high data rate RAM integrated circuit memory (over 80 Gigabit / second flow, in particular from 85 Gigabit / second to 200 Gigabit / second , or more) (B) for its at least temporary recording in said memory (B); A third output programmable logic array (F) controlling the one or more image signals / output image signals, comprising a plug or connection adapted to be connected to a camera control unit for transferring the image signal (O); ; A fourth programmable logic transcription network (D) receiving transformed / readable image signals temporarily stored in the high data rate RAM integrated circuit memory (flows greater than 80 Gigabit / second, in particular 85 Gigabit / second at 200 Gigabit / second or more), said programmable logic transcription network including a function for splitting or splitting, at least as a function of time, the digital image signals (in RAW format or raw uncompressed or substantially uncompressed) transformed or readable into at least temporal slices comprising a successive series of digital image signals (in RAW format or raw uncompressed or substantially uncompressed) transformed or readable, said programmable transcriptional logic network (D) further comprising an output adapted to be connected to a non-volatile memory (34), ♦ a fifth logical network prog rammable reading (E) of at least temporal slices of digital image signals (RAW format or raw uncompressed or substantially uncompressed) transformed, said read programmable logic array comprising a read and transfer function of the slice read or slices read to the high data rate integrated circuit RAM memory (flows greater than 80 Gigabit / second, in particular 85 Gigabit / second at 200 Gigabit / second or more) (B) to at least memorize the slice read from temporarily, and at least one plug or connection adapted to connect it to the non-volatile memory (34), wherein the third output programmable logic array (F) includes a function for recovering in the integrated circuit memory (B) the or slices read, so that depending on a signal from a camera control unit, the output programmable logic array (F) transmits one or more the slice or slices read, ie one or more transformed image signals from the second programmable logic transformation network (C). The assembly or camera according to the invention advantageously has one or more of the following characteristics, preferably a plurality of following characteristics: the assembly or camera comprises at least one non-volatile memory 34, advantageously a series of non-volatile memories mounted in parallel. And / or the set or camera comprises a digital adaptive equalizer system (30), said digital adaptive equalizer system advantageously comprising a waveform sampler. And / or - the digital adaptive equalizer system (30) is adapted to ensure a variable gain at least in the frequency range from 500 MHz to 1 GHz, the gain being advantageously between -2 dB and 10 dB. And / or - the assembly or camera comprises one or more line amplifiers (16) adapted to transfer amplified RAW format digital image files or uncompressed or substantially uncompressed raw digital image files amplified to a programmable logic network adapted to condition the image files into a form useful for recording them in the high-rate integrated circuit (B) memory, in particular at at least double data rate, the said line amplifiers having a function or circuit for suppressing and pre-emphasizing the signal. And / or - the line amplifier (16) is / are adapted to ensure a substantially constant gain, advantageously between -2 and OdB independently of the frequency, at least for the frequency range between 100 MHz and 5 GHz. and / or the set or camera comprises a digital adaptive equalizer system (30) receiving signals from one or more line amplifiers (16) via a connection with transmission rates greater than 1 Gbits per second, said connection advantageously comprising one or more optical fibers. And / or the assembly or camera comprises at least one non-volatile memory, advantageously a series of non-volatile memory. And / or the assembly or camera further comprises a connection adapted to connect it to one or a series of nonvolatile external memories. And / or a combination of these features The invention also relates to: a camera according to the invention further comprising one or more CMOS sensors, one or more optical / electrical interfaces, and a connection for a control device of camera signals; a video signal transmission center comprising a device for controlling camera signals from a plurality of cameras according to the invention; the use of a camera according to the invention, or a center according to the invention for the retransmission or broadcasting of images in real time, and slow motion images, in particular comprising images broadcast in super , ultra and / or slowed down.

Features and details of preferred embodiments of the invention will become apparent from the following detailed description in which reference is made to the accompanying drawings. In these drawings, - Figure 1 is a schematic view of an assembly according to the invention; Figure 2 is a view of a camera according to the invention associated with a control unit; FIG. 3 is a view of a camera connected to an assembly according to the invention and to a control unit; FIG. 4 is a graph giving the gain of a line amplifier advantageously used, and FIG. 5 is a graph giving the reception gain of the signal coming out of an equalizer, as a function of the characteristics of this equalizer. The subject of the invention is a camera assembly with an image pickup system, advantageously slowed down, preferably super slowed (SSM) or ultra slow motion (USM), or camera for taking images, advantageously slowed down, preferably super slowed down. (SSM) or ultra slow motion (USM) comprising such a set, said set being adapted to allow at least both the recording of a digital image (RAW format or raw uncompressed or substantially uncompressed) in real time and the vision of a digital pre-recorded image (in RAW or uncompressed or substantially uncompressed raw form), in particular of the idle type, characterized in that said set comprises: an integrated circuit memory with at least double data rate, in particular of the type DDR (B); At least one first programmable logic network for controlling said at least dual data rate integrated circuit memory, said at least one programmable logic control network comprising at least the following functions: reception function (A) for receiving the digital image files (in RAW or uncompressed or substantially uncompressed raw), optionally amplified, or digital negatives of digital images (in RAW format or uncompressed or substantially uncompressed raw), optionally amplified, and for packaging said digital files in a form useful for storing them in at least dual data rate integrated circuit memory; - at least substantially live signal transformation function (C) for conditioning digital image files (in RAW format or raw uncompressed or substantially uncompressed) and transforming them into digital image signal / signals (in RAW or raw format) uncompressed or substantially uncompressed) transformed or readable at least substantially live, said programmable logical transformation network transferring the digital image signal (s) (in RAW format or raw uncompressed or substantially uncompressed) transformed or readable at least partially directly to a programmable logic output network (F) and to the integrated circuit memory at least double data rate (B) for its at least temporary recording in said memory (B); transcription facility (D) receiving unencrypted or digitally converted (or raw uncompressed or substantially uncompressed) raw digital image signals (or images) stored in the at least dual data rate integrated circuit memory, said network programmable transcription logic comprising a function for dividing or cutting, at least as a function of time, the digital image signals (in RAW format or raw uncompressed or substantially uncompressed) transformed or readable into at least temporal slices comprising a successive series of signals transformed or readable images, said programmable transcriptional logic network (D) further comprising an output adapted to be connected to a nonvolatile memory (34), and - reading function (E) of at least temporal slices of digital image signals ( in RAW format or raw uncompressed or substantially uncompressed) transformed, said read programmable logic array comprising a read and transfer function of the read slice or read slices to the at least dual (B) data rate integrated circuit memory for at least storing the slice read temporarily, and at least one plug or connection adapted to connect it to the non-volatile memory (34), and ♦ a programmable output logical network (F), possibly forming part of the first programmable logic control network, but preferably distinct from said first logical network programmable control system, said output programmable logic array controlling the one or more image signals / output image signals, comprising a plug or connection adapted to be connected to a camera control unit for transferring the one or more image signals (O); wherein the output programmable logic array (F) includes a function for recovering in the integrated circuit memory (B) the slice (s) read, so that depending on a signal from a camera control unit , the output programmable logic array (F) transmits either one or more signals of the read slice (s), or one or more uncompressed or substantially uncompressed digital image signals (in RAW or raw uncompressed format) from the first programmable logic array via the transformation function (C).

Such an assembly is shown schematically in FIG.

In fact, the assembly of FIG. 1 is a unit (32) comprising at least: an integrated circuit memory with at least two data rates, in particular of the DDR (B) type; A first programmable logic network for controlling said at least dual data rate integrated circuit memory, said first programmable logic control network comprising at least the following functions: reception function (A) for receiving the image files raw numerals, optionally amplified, or digital negatives of images, possibly amplified, and for conditioning said digital files in a form useful for recording them in the integrated circuit memory with at least double data rate; and at least substantially live signal transformation function (C) for conditioning the digital image files and transforming them into at least substantially live transformed or readable signal / image signals, said programmable logic transformation network transferring the one or more / the image signals transformed or readable at least partially directly to an output programmable logic array (F) and to the at least dual data rate integrated circuit memory (B) for its at least temporary recording in said memory (B) ); A second programmable logic network for controlling said at least two-bit data rate integrated circuit memory, said second programmable logic control network comprising at least the following functions: transcription function (D) receiving transformed / readable image signals; temporarily stored in at least two-bit data rate integrated circuit memory, said programmable transcriptional logic network including a function for splitting or cutting, at least as a function of time, the transformed or readable image signals into at least temporal slices comprising a successive series of transformed or readable image signals, said programmable transcriptional logic network (D) further comprising an output adapted to be connected to a non-volatile memory (34), and - reading function (E) of at least two slices time of transformed image signals, said logical network prog a readable readout comprising a read and transfer function of the slice read or slices read to the integrated circuit memory at least double data rate (B) to at least store the slice read temporarily, and at least one plug or connection adapted to connect it to the nonvolatile memory (34), and ♦ an output programmable logic array (F) controlling the image signal (s) / output image signals, including a plug or connection adapted to be connected to a camera control unit for transferring the image signal (O). wherein the output programmable logic array (F) includes a function for recovering in the integrated circuit memory (B) the slice (s) read, so that depending on a signal from a camera control unit , the output programmable logic array (F) transmits either one or more signals of the read slice (s), or one or more transformed image signals from the first programmable logic array via the transformation function (C).

And even more specifically a set comprising at least: ♦ an integrated circuit memory with at least two data rates, in particular of the DDR (B) type; A first programmable receive logical network (A) for receiving the raw digital image files, possibly amplified, or digital negative images, possibly amplified, and for conditioning said digital files in a form useful for recording them in the integrated circuit memory with at least double data rate; A second programmable logic network for transforming the at least substantially live signal (C) for conditioning the digital image files and transforming them into image signals / signals transformed or readable at least substantially directly, said programmable logical transformation network transferring the at least partially read-processed or read-out image signal to an output programmable logic array (F) and at least two-bit (B) data-rate integrated circuit memory for its at least temporary registration in said memory (B); A third output programmable logic array (F) controlling the one or more image signals / output image signals, comprising a plug or connection adapted to be connected to a camera control unit for transferring the image signal (O); ; A fourth programmable logic transcription network (D) receiving transformed / readable image signals temporarily stored in the at least two-bit data rate integrated circuit memory, said programmable transcriptional logic network including a function for dividing or at least as a function of time, cutting the transformed or readable image signals into at least temporal slices comprising a successive series of transformed or readable image signals, said programmable transcriptional logic network (D) further comprising an output adapted to be connected to a nonvolatile memory (34); ♦ a fifth programmable logic array for reading (E) at least one time slot of transformed image signals, said readable programmable logic array comprising a read and transfer function of the read slice or slices; read to the data rate integrated circuit memory at least double (B) to at least store the slice read temporarily, and at least one plug or connection adapted to connect it to the non-volatile memory (34), wherein the third programmable logic output network (F) comprises a function for recovering in the integrated circuit memory (B) the slice (s) read, so that, as a function of a signal from a camera control unit, the programmable output logical network (F) transmits either one or more signals of the read slice (s), or one or more transformed image signals from the second programmable transformation lattice (C). The assembly or unit 32 of the invention is advantageously mounted close to the camera 1 or the sensor 1. Preferably, the distance separating the double memory B from the image sensor 10 will be less than 10 cm, in particular less than 10 cm. 5cm. By comparing the output of the image sensor and the double memory B, it was noted that it was possible to ensure a consequent and appropriate processing of the images, this allowing a better quality of the images both instantaneous but also recorded. to be rebroadcast in idle, even in idle.

Said assembly 32 is associated with a radio television transmission camera with ultra or slow motion images. This camera is capable of taking images at the rate of more than 75 images per second, preferably at a rate of more than 500 images per second, for example from 1000 to 10,000 images per second. The frame rate can be controlled if necessary.

The sensor of the camera is advantageously a sensor comprising more than one million pixels, in particular more than 2 million pixels, for example 5 to 20 million pixels or more. The assembly allows the recording, for example, of more than 100, in particular more than 200 images / second in one or more non-volatile memories, in particular a rotating memory. The assembly according to the invention 32 may be associated with additional elements or components.

Thus the assembly 3 according to the invention shown in FIG. 3 comprises, in addition to the unit 32: a digital adaptive equalizer system (30), said digital adaptive equalizer system advantageously comprising a waveform sampler, said adaptive equalizer system digital (30) being advantageously adapted to provide a variable gain at least in the frequency range of 500MHz to 1GHz, the gain being advantageously between -2 dB and 10dB. A nonvolatile memory 34 or a series of non-volatile memories connected in parallel; At least one optical and / or electrical interface 36 making it possible, for example, to continuously display the images taken by the camera, and a connection 38 adapted to ensure, via a transmission cable 350, for example of the fiber-optic or quality type; equivalent, digital signals to a control unit 4.

The video signal of high bit rate raw digital images I from the camera 1 or the high speed CMOS sensor (s) 10.

The adaptive equalizer system will preferably be of the variable type and will respond for example with a variable gain as a function of the frequency of the signal, and a regulation parameter of the equalizer. This parameter will essentially modify the gain of the equalizer for frequencies above 300 MHz (for example from 300 MHz to 3 GHz) with gains ranging from -2 to +10 or more.

This equalizer 30 "is advantageous for compensating for the loss of image signal due to the cable 20 (see FIG. 4). However, the cable 20 will be chosen to limit the signal loss to a minimum for frequencies of more than 200 MHz. The equalizer thus makes it possible to obtain a response coming out of the equalizer with a substantially constant gain and this for frequencies from 100 MHz to 2 GHz.

These soft digital signals I are received by the first programmable reception digital network A for sending them in a double memory B, which then serves as an image buffer to process this double memory B is segmented / divided to allow multiple streams of input signals. and exit, all at high speed. The logic network C is in charge of conditioning the high-speed image stream to generate the live video signal to be broadcast via the logic network F. The logic network C also sends the conditioned video signal to the double memory B, before this conditioned video signal is processed by the logic network D. This logical network D cuts in successive slices, possibly with overlapping or partial superposition of slices of images, and transfers these conditioned image signals in one or more non-volatile memories 34 mounted in parallel. 34 in Figure 1 shows a series of nonvolatile memories mounted in parallel.

The logical network E is in charge of recovering the image signals in RAW format or in uncompressed or substantially uncompressed raw format, conditioned stored in the nonvolatile memories 34, according to the request of an operator, and for speeds retransmission variables, and for variable modes ranging from simple idle to hyper idle, allowing even accelerated stored conditioned images.

The output logical network F is adapted to ensure integration of the live image signals and images of the buffer memory B, possibly from one or non-volatile memories 34 via the logic network E.

All the logical networks of the assembly according to the invention 32 operate in parallel. They are programmed accordingly to ensure the transfer of signals between them and / or to the double memory B.

It is clear that the logical networks are preferably distinct from each other according to their function, this to facilitate their programming and speed up the processing speed of the images. In this case, the cables for signal transfer will be as short as possible and adapted to ensure very fast transfer speeds.

In embodiments, more than one logical network may form a single logical network.

The camera module 1 of FIG. 3 comprises: a high-speed CMOS sensor 10; a device for controlling the operation of the sensor 10, said device generating images in RAW format or raw images (uncompressed or substantially uncompressed) digitized for logical network; a video bus for digital images in RAW format 14; and a connection 16 for cable 20 for fast transfer of logical data to the assembly 3, said cable comprising quick connections 110 and 300. The assembly 3 is associated with a control unit CCU 4 via a cable 350 ensuring the power supply of the camera and the fast transfer of digital data corresponding to the request for searching by the user of one or more video image data, and data resulting either from the live digital video signal or the video signal of searched images in one or non-volatile memories 34 or the buffer memory 32. This cable 350 is connected to the control device 4, via the fast connection 40.

The CCU 4 includes a central processing and control unit 42 associated with remote control devices (JOG or OCP) 50,60 via ethernet connections 500,600.

The CCU 4 has at least two parallel outputs, the output 410 being for the live video signal, while the output 420 is for the idle signal, in particular super, hyper or ultra slow.

The camera module 1 of FIG. 2 integrates the unit 32.

This camera comprises: a high-speed CMOS sensor 10; a device for controlling the operation of the sensor 10, said device generating scanned raw images for a logical network; a video transfer (transfer) bus for digital images, advantageously in RAW format or in uncompressed raw format 14; a connection 100 between the bus 14 and the unit 32; a series of nonvolatile memories 34 connected to the unit 32 by means of a bus (transfer) of data in RAW or fast raw format to the logical networks D and E of the unit 32; an interface 36 for controlling and displaying video images O originating from the unit 32 (of the logic network F) via the fast transfer bus 320; a connection 38 connected to the control device 36 by the cable 340, this cable serving for the power supply of the control device 36 and the camera 1, and comprising means for fast transfer (for example optical fibers) of the data digital images O;

The camera 1 is associated with a control unit CCU 4 via a cable 350 ensuring the power supply of the camera and the fast transfer of digital data corresponding to the request for research by the user of one or more data. video images, and data resulting either from the digital live video signal or the video signal of searched images in one or non-volatile memories 34 or the buffer memory 32. This cable 350 is connected to the control device 4, via the fast connection 40.

The CCU 4 includes a central processing and control unit 42 associated with remote control devices (JOG or OCP) 50, 60 via ethernet connections 500,600.

The CCU 4 has at least two parallel outputs, the output 410 being for the live video signal, while the output 420 is for the idle signal, in particular super, hyper or ultra slow. The control unit CCU 4, which may possibly be part of the camera 1, but which is preferably a unit external to the camera, comprises: an optical demultiplexer of the video signals coming from the intermediate assembly 3; an optical / electrical conversion module of the SDI SFP type; a programmable logic processing network 42 which controls the incoming and outgoing signal flow; an output interface for providing the studio with the required signals, in particular in high definition (SDI type), for example live or instantaneous, in re-vision; slow-motion, video feedback, locked signals, audio, acoustic, intercom, etc. ; - The current arrival to the camera and / or to the assembly 3; - intercom functions (input and output); - Control functions (computer) that control the system and which advantageously allows remote control of the camera and the assembly 3, while allowing Internet connections for maintenance and updates.

The CCU 4 advantageously has a video processing unit which processes the flow of images from and transmits an output image signal, for example high definition instantaneous image signal (SDI), a signal in high definition re-vision, and signals Ethernet video.

The remote control devices 50,52 (JOG or OCP) allow an operator to navigate the data present in the memories 34, via the interface 3. They include for example one or more push buttons and / or rotary and / or or pivoting, for example a ball. They make it possible to control, for example, the speed of the images to be ironed (re-vision), but also the very operation of the camera, for example of the lens, the number of images taken, the position of the camera, the field vision, etc.

The instantaneous colorimetric parameters will advantageously also be stored in the memories 34. These parameters can then be found during the replay of images in slow motion when required.

To ensure instantaneous or substantially instantaneous image processing, the data transfer connections and cables will advantageously be of the type enabling very fast data flows, in particular allowing incoming and / or outgoing data flows in parallel. Such cables and connections are for example optical fiber connections or cables, copper, etc. The recording of the image data advantageously in RAW format or uncompressed raw or substantially uncompressed crude in the memory 34 is advantageously continuous or substantially continuous. This memory 34 may be a series of flash type memory or remote parallel memories. The size of the memories will be adapted as needed, but may be several TB (Tera bytes or terabytes). The recording will advantageously be looped and indexed in elementary blocks. For example, indexing will indicate whether the block is empty (to avoid replaying an empty block or without images), if the block contains one or more images ("protected" block to avoid an overwriting of another image; then to preserve images and to be able to return them in hyper-idle mode), if the block contains erroneous images or presents a defect (block is then marked "error").

The blocks advantageously include colorimetric parameters defined by the operator during the taking of snapshots. The invention allows in advantageous embodiments one or more of the following advantages: - Protection against the re-registration of images on part of the memory for a sufficient time; - Instant access to each single image (block) contained in the memory 34, thus allowing a smooth or adapted variation of the ironing speed of images; - Reduced cost since it is no longer necessary to have a dedicated server for each camera, and only one server can very well search for the desired image taken by a camera; - High speed or high frequency recording of images substantially at the same output of the sensor; - Etc.

Claims (15)

claims 1. Set for a camera with an image capture system, advantageously slowed, preferably super slowed (SSM) or ultra slow motion (USM), or camera for taking pictures, advantageously slowed, preferably super slowed (SSM) or ultra a set, said set being adapted to allow at least both the recording of an image in real time and the vision of a prerecorded image, in particular of the idle type, characterized in that said set includes: ♦ high data rate RAM IC (over 80 Gigabit / second, especially 85 Gigabit / second to 200 Gigabit / second or greater) (B); At least one first programmable logic network for controlling said high data rate RAM integrated circuit memory (flow greater than 80 Gigabit / second, in particular from 85 Gigabit / second to 200 Gigabit / second or more), said at least one programmable logic control network comprising at least the following functions: reception function (A) for receiving the digital image files (in RAW format or raw uncompressed or substantially uncompressed), possibly amplified, or digital negatives digital images (in RAW or uncompressed or substantially uncompressed raw form), possibly amplified, and for conditioning said digital files in a form useful for recording them in a high data rate RAM (high flux) Gigabit / second, especially from 85 Gigabit / second to 200 Gigabit / second or more); - at least substantially live signal transformation function (C) for conditioning digital image files (in RAW format or raw uncompressed or substantially uncompressed) and transforming them into digital image signal / signals (in RAW or raw format) uncompressed or substantially uncompressed) transformed or readable at least substantially live, said programmable logical transformation network transferring the at least partially converted live or read image signal (s) to a programmable logic output network (F) and to the high data rate RAM integrated circuit chip (flow greater than 80 Gigabit / second, in particular 85 Gigabit / second at 200 Gigabit / second or more) (B) for its at least temporary recording in said memory (B ); transcription function (D) receiving transformed / read image signals stored temporarily in the high data rate RAM integrated circuit memory (flow greater than 80 Gigabit / second, in particular 85 Gigabit / second at 200 Gigabit / second or more) (B), said programmable logic transcription network comprising a function for dividing or cutting, at least as a function of time, the digital image signals (in RAW format or raw uncompressed or substantially uncompressed) transformed or readable in at least a temporal slice comprising a successive series of digital image signals (in RAW format or raw uncompressed or substantially uncompressed) transformed or readable, said programmable transcriptional logic network (D) further comprising an output adapted to be connected to a non-volatile memory (34), and - reading function (E) of at least temporary signal slots x digital images (in RAW or raw uncompressed or substantially uncompressed) transformed, said read programmable logic array comprising a read and transfer function of the slice read or slices read to the high-speed RAM integrated circuit memory of data (flows greater than 80 Gigabit / second, in particular 85 Gigabit / second at 200 Gigabit / second or more) (B) to at least memorize the slice read temporarily, and at least one plug or connection adapted for connecting it to the nonvolatile memory (34), and ♦ an output programmable logic array (F), possibly forming part of the first programmable logic control network, but preferably distinct from said first programmable logic control network, said programmable logic array output signal controlling the image signal / output image signals, comprising a plug or connection adapted to be connected to a unit camera control for transferring the image signal (O); wherein the output programmable logic array (F) includes a function for recovering in the integrated circuit memory (B) the slice (s) read, so that depending on a signal from a camera control unit , the output programmable logic array (F) transmits either one or more signals of the read slice (s), or one or more uncompressed or substantially uncompressed digital image signals (in RAW or raw uncompressed format) from the first programmable logic array via the transformation function (C). 2. A set or camera according to claim 1, characterized in that said set comprises at least: a high data rate RAM integrated circuit memory (flow greater than 80 Gigabit / second, in particular from 85 Gigabit / second to 200 Gigabit / second or more) (B); A first programmable logic network for high-speed data memory integrated circuit RAM control (flows greater than 80 Gigabit / second, in particular 85 Gigabit / second at 200 Gigabit / second or more), said first programmable logic network control system comprising at least the following functions: reception function (A) for receiving the digital image files (in RAW format or raw uncompressed or substantially uncompressed), possibly amplified, or digital negative images, possibly amplified, and for conditioning said digital files in a form useful for recording them in high data rate integrated circuit RAM memory (over 80 Gigabit / second stream, in particular from 85 Gigabit / second to 200 Gigabit / second or more). ); and at least substantially live signal transforming function (C) for conditioning the digital image files (in RAW format or raw uncompressed or substantially uncompressed) and transforming them into digital image signal / signals (in RAW format or raw uncompressed or substantially uncompressed) transformed or readable at least substantially live, said programmable logical transformation network transferring the digital image signal (s) (in RAW format or raw uncompressed or substantially uncompressed) transformed or readable at least partially live to a programmable logic output network (F) and to a high data rate RAM integrated circuit (over 80 Gigabit / second waveband, in particular 85 Gigabit / second to 200 Gigabit / second or more) (B) for at least temporary recording in said memory (B); A second programmable logic chip for a high data rate RAM integrated circuit memory control (flows greater than 80 Gigabit / second, in particular 85 Gigabit / second to 200 Gigabit / second or more), said second programmable logic network control system comprising at least the following functions transcription function (D) receiving transformed / readable image signals temporarily stored in high data rate RAM integrated circuit memory (over 80 Gigabit / second data stream, in particular 85 Gigabit / second to 200 Gigabit / second or more) (B), said programmable transcriptional logic network comprising a function for dividing or cutting, at least as a function of time, the transformed or readable image signals into at least temporal slices comprising a successive series of transformed or readable image signals, said programmable logic transcription network (D) comprising in addition, an output adapted to be connected to a nonvolatile memory (34), and - a reading function (E) of at least temporal slices of digital image signals (in RAW format or raw uncompressed or substantially uncompressed) transformed, said programmable logic read network comprising a read and transfer function of the slice read or slices read to a high data rate RAM integrated circuit memory (over 80 Gigabit / second wave, in particular 85 Gigabit / second wave at 200 Gigabit / second or more) (B) to at least store the slice read temporarily, and at least one plug or connection adapted to connect it to the nonvolatile memory (34), and ♦ a programmable output logical network ( F) controlling the image signal (s) / output image signal, comprising a plug or connection adapted to be connected to a camera control unit for transferring the image signal (s) s (O). wherein the output programmable logic array (F) includes a function for retrieving high data rate RAM in the integrated circuit RAM (streams greater than 80 Gigabit / second, in particular 85 Gigabit / second at 200 Gigabit / second, or more) (B) the slice (s) read, so that depending on a signal from a camera control unit, the output programmable logic array (F) transmits one or more signals from the read slices, one or more digital image signals (in RAW format or raw uncompressed or substantially uncompressed) transformed from the first programmable logic network via the transformation function (C). 3. A set or camera according to claim 1 or 2, characterized in that said set comprises at least: a high data rate RAM integrated circuit memory (flow greater than 80 Gigabit / second, in particular 85 Gigabit / second 200 Gigabit / second or more) (B); A first programmable receive logical network (A) for receiving the raw digital image files, possibly amplified, or digital negatives of digital images (in RAW format or raw uncompressed or substantially uncompressed), possibly amplified, and for packaging said digital files (in RAW or uncompressed or substantially uncompressed raw form) into a form useful for storing them in at least dual data rate integrated circuit memory; A second programmable logic network for transforming the at least substantially live signal (C) to condition the digital image files and transform them into digital image signal / signals (in RAW format or raw uncompressed or substantially uncompressed) transformed or at least substantially live readable, said programmable logical transformation network transferring the digital image signal (s) (in RAW format or raw uncompressed or substantially uncompressed) transformed or readable at least partially directly to a programmable logic output network (F) and to the high data rate integrated circuit RAM (over 80 Gigabit / second, especially 85 Gigabit / second to 200 Gigabit / second or more) (B) for at least temporary recording in said memory (B); A third output programmable logic array (F) controlling the one or more image signals / output image signals, comprising a plug or connection adapted to be connected to a camera control unit for transferring the image signal (O); ; A fourth programmable transcriptional logic network (D) receiving unprocessed or substantially uncompressed processed or read digital images (in RAW or raw uncompressed or substantially uncompressed format) stored in the high data rate RAM integrated circuit memory; (Flow greater than 80 Gigabit / second, in particular from 85 Gigabit / second to 200 Gigabit / second or more) (B), said programmable logic transcription network comprising a function for dividing or cutting, at least as a function of time, the digital image signals (in RAW format or raw uncompressed or substantially uncompressed) transformed or readable in at least a time slot comprising a successive series of transformed or readable image signals, said programmable transcriptional logic network (D) further comprising an output adapted to be connected to a non-volatile memory (34), ♦ a fifth logical network p rogrammable reading (E) of at least temporal slices of digital image signals (in RAW format or raw uncompressed or substantially uncompressed) transformed, said read programmable logic array comprising a read and transfer function of the slice read or slices read to the high data rate integrated circuit RAM memory (flows greater than 80 Gigabit / second, in particular 85 Gigabit / second at 200 Gigabit / second or more) (B) to at least memorize the slice read from temporarily, and at least one plug or connection adapted to connect it to the nonvolatile memory (34), wherein the third programmable output logical network (F) includes a function for finding in the high-speed RAM integrated circuit memory (greater than 80 Gigabit / second, especially 85 Gigabit / second at 200 Gigabit / second or more) (B) the slice (s) read, so that signal output from a camera control unit, the output programmable logic array (F) transmits either one or more signals of the read slice (s), or one or more transformed image signals from the second programmable logic array. transforming circuit (C), wherein the high data rate RAM integrated circuit memory (flows greater than 80 Gigabit / second, in particular from 85 Gigabit / second to 200 Gigabit / second or more) is preferably integrated circuit with at least double data rate, in particular DDR (B). 4. The assembly or camera according to any one of the preceding claims, characterized in that it comprises at least one non-volatile memory (34), advantageously a series of nonvolatile memories mounted in parallel. An assembly or camera according to any one of the preceding claims, characterized in that it comprises a digital adaptive equalizer system (30), said digital adaptive equalizer system advantageously comprising a waveform sampler. 6. Set or camera according to the preceding claim, characterized in that the digital adaptive equalizer system (30) is adapted to provide a variable gain at least in the frequency range of 500MHz to 1 GHz, the gain being advantageously between -2. dB and 10 dB. (Would it be possible to better specify what the different curves of Figure 4 represent) 7. Set or camera according to any one of the preceding claims, characterized in that it comprises one or more line amplifiers (16) adapted (s) for transferring digital image files (in RAW format or raw uncompressed or substantially uncompressed) amplified or digital image files (in RAW or uncompressed or substantially uncompressed raw) amplified, to a programmable logic array adapted to condition the digital image files (in RAW or raw uncompressed format) or substantially uncompressed) into a form useful for recording in the high data rate RAM integrated circuit memory (streams greater than 80 Gigabit / second, in particular 85 Gigabit / second at 200 Gigabit / second, or more) ( B), the said line amplifier (s) comprising a function or circuit for suppressing and pre-emphasizing the signal. 8. Assembly or camera according to the preceding claim, characterized in that the / the line amplifiers (16) is / are adapted (s) to ensure a substantially constant gain, preferably between -2 and OdB independently of the frequency, to less for the frequency range 100MHz to 3 GHz. An assembly or camera according to any one of the preceding claims, characterized in that it comprises a digital adaptive equalizer system (30) receiving signals from one or more line amplifiers (16) via a connection with speeds transmission greater than 1 Gbits per second, said connection advantageously comprising one or more optical fibers. 10. Assembly or camera according to any one of the preceding claims, characterized in that it comprises at least one non-volatile memory, preferably a series of non-volatile memory. 11. The set or camera according to the preceding claim, characterized in that it further comprises a connection adapted to connect it to one or a series of non-volatile external memories. The camera according to any one of the preceding claims, further comprising one or more CMOS sensors, one or more optical / electrical interfaces, and a connection for a camera signal control device. 13. Camera according to claim 12, characterized in that the double memory B is connected by a connection cable to the image sensor 10 whose distance is less than 10 cm, preferably less than 5 cm, preferably less than 5 cm. 3 cm. 14. Video signal transmission center comprising a device for controlling camera signals from a plurality of cameras according to the preceding claim. 15. Use of a camera according to claim 12 or 13, or a center according to claim 14 for the retransmission or broadcasting of images in real time, and slow motion images, in particular comprising images broadcast in super and / or slow motion.