AU9063491A - Logic placement using positionally asymmetrical partitioning algorithm - Google Patents

Logic placement using positionally asymmetrical partitioning algorithm

Info

Publication number
AU9063491A
AU9063491A AU90634/91A AU9063491A AU9063491A AU 9063491 A AU9063491 A AU 9063491A AU 90634/91 A AU90634/91 A AU 90634/91A AU 9063491 A AU9063491 A AU 9063491A AU 9063491 A AU9063491 A AU 9063491A
Authority
AU
Australia
Prior art keywords
positionally
partitioning algorithm
logic placement
asymmetrical partitioning
asymmetrical
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
AU90634/91A
Inventor
Mon Ren Chene
Stephen M Trimberger
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Xilinx Inc
Original Assignee
Xilinx Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US07/784,844 external-priority patent/US5224056A/en
Application filed by Xilinx Inc filed Critical Xilinx Inc
Publication of AU9063491A publication Critical patent/AU9063491A/en
Abandoned legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G06F30/392—Floor-planning or layout, e.g. partitioning or placement

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Architecture (AREA)
  • Evolutionary Computation (AREA)
  • Geometry (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
AU90634/91A 1990-11-15 1991-11-14 Logic placement using positionally asymmetrical partitioning algorithm Abandoned AU9063491A (en)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US61490690A 1990-11-15 1990-11-15
US614906 1990-11-15
US07/784,844 US5224056A (en) 1991-10-30 1991-10-30 Logic placement using positionally asymmetrical partitioning algorithm
US784844 1991-10-30

Publications (1)

Publication Number Publication Date
AU9063491A true AU9063491A (en) 1992-06-11

Family

ID=27087357

Family Applications (1)

Application Number Title Priority Date Filing Date
AU90634/91A Abandoned AU9063491A (en) 1990-11-15 1991-11-14 Logic placement using positionally asymmetrical partitioning algorithm

Country Status (2)

Country Link
AU (1) AU9063491A (en)
WO (1) WO1992009042A1 (en)

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3617714A (en) * 1969-04-15 1971-11-02 Bell Telephone Labor Inc Method of minimizing the interconnection cost of linked objects
UST940008I4 (en) * 1974-05-17 1975-11-04 Automated logic mapping system
EP0271596B1 (en) * 1986-12-17 1995-05-17 International Business Machines Corporation VLSI-chip design and manufacturing process
US4908772A (en) * 1987-03-30 1990-03-13 Bell Telephone Laboratories Integrated circuits with component placement by rectilinear partitioning
US4967367A (en) * 1988-11-21 1990-10-30 Vlsi Technology, Inc. Synthetic netlist system and method

Also Published As

Publication number Publication date
WO1992009042A1 (en) 1992-05-29

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