AU8858998A - Digital phase locked loop - Google Patents

Digital phase locked loop

Info

Publication number
AU8858998A
AU8858998A AU88589/98A AU8858998A AU8858998A AU 8858998 A AU8858998 A AU 8858998A AU 88589/98 A AU88589/98 A AU 88589/98A AU 8858998 A AU8858998 A AU 8858998A AU 8858998 A AU8858998 A AU 8858998A
Authority
AU
Australia
Prior art keywords
locked loop
phase locked
digital phase
digital
loop
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
AU88589/98A
Inventor
Antti Poutanen
Pekka Suvitaival
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nokia Oyj
Original Assignee
Nokia Telecommunications Oy
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from DE1997129476 external-priority patent/DE19729476C2/en
Priority claimed from DE1997129477 external-priority patent/DE19729477A1/en
Application filed by Nokia Telecommunications Oy filed Critical Nokia Telecommunications Oy
Publication of AU8858998A publication Critical patent/AU8858998A/en
Abandoned legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/099—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
    • H03L7/0991—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop the oscillator being a digital oscillator, e.g. composed of a fixed oscillator followed by a variable frequency divider
    • H03L7/0992—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop the oscillator being a digital oscillator, e.g. composed of a fixed oscillator followed by a variable frequency divider comprising a counter or a frequency divider
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K23/00—Pulse counters comprising counting chains; Frequency dividers comprising counting chains
    • H03K23/64—Pulse counters comprising counting chains; Frequency dividers comprising counting chains with a base or radix other than a power of two
    • H03K23/68—Pulse counters comprising counting chains; Frequency dividers comprising counting chains with a base or radix other than a power of two with a base which is a non-integer
AU88589/98A 1997-07-10 1998-07-08 Digital phase locked loop Abandoned AU8858998A (en)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
DE19729476 1997-07-10
DE1997129476 DE19729476C2 (en) 1997-07-10 1997-07-10 Numerically controlled oscillator
DE1997129477 DE19729477A1 (en) 1997-07-10 1997-07-10 Digital phase locked loop
DE19729477 1997-07-10
PCT/EP1998/004235 WO1999003207A1 (en) 1997-07-10 1998-07-08 Digital phase locked loop

Publications (1)

Publication Number Publication Date
AU8858998A true AU8858998A (en) 1999-02-08

Family

ID=26038171

Family Applications (1)

Application Number Title Priority Date Filing Date
AU88589/98A Abandoned AU8858998A (en) 1997-07-10 1998-07-08 Digital phase locked loop

Country Status (3)

Country Link
EP (1) EP1012980B1 (en)
AU (1) AU8858998A (en)
WO (1) WO1999003207A1 (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4996424B2 (en) * 2007-11-08 2012-08-08 ルネサスエレクトロニクス株式会社 Signal processing device
GB0807152D0 (en) * 2008-04-18 2008-05-21 Toric Ltd Clock generator circuits

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE1921133C3 (en) * 1968-05-08 1978-11-02 Kombinat Veb Rft Fernmeldewerk Leipzig, Ddr 7027 Leipzig Pulse scaler for rationally broken division factors
US5052031A (en) * 1990-08-14 1991-09-24 At&T Bell Laboratories Phase locked loop including non-integer multiple frequency reference signal
US5335253A (en) * 1992-10-01 1994-08-02 Gould, Inc. Non-integral frequency division using regulated digital divider circuits
JP3066690B2 (en) * 1993-09-20 2000-07-17 富士通株式会社 Phase-locked oscillation circuit

Also Published As

Publication number Publication date
EP1012980B1 (en) 2002-03-06
WO1999003207A1 (en) 1999-01-21
EP1012980A1 (en) 2000-06-28

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Legal Events

Date Code Title Description
MK6 Application lapsed section 142(2)(f)/reg. 8.3(3) - pct applic. not entering national phase