AU8172098A - Multi-function controller and method for a computer graphics display system - Google Patents

Multi-function controller and method for a computer graphics display system

Info

Publication number
AU8172098A
AU8172098A AU81720/98A AU8172098A AU8172098A AU 8172098 A AU8172098 A AU 8172098A AU 81720/98 A AU81720/98 A AU 81720/98A AU 8172098 A AU8172098 A AU 8172098A AU 8172098 A AU8172098 A AU 8172098A
Authority
AU
Australia
Prior art keywords
display system
computer graphics
graphics display
function controller
controller
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
AU81720/98A
Inventor
Dan C. Kang
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
S3 Inc
Original Assignee
S3 Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by S3 Inc filed Critical S3 Inc
Publication of AU8172098A publication Critical patent/AU8172098A/en
Abandoned legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/36—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
    • G09G5/363—Graphics controllers
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2360/00—Aspects of the architecture of display systems
    • G09G2360/12—Frame memory handling
    • G09G2360/121—Frame memory handling using a cache memory
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2360/00—Aspects of the architecture of display systems
    • G09G2360/12—Frame memory handling
    • G09G2360/125—Frame memory handling using unified memory architecture [UMA]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/001—Arbitration of resources in a display system, e.g. control of access to frame buffer by video controller and/or main processor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/003—Details of a display terminal, the details relating to the control arrangement of the display terminal and to the interfaces thereto
    • G09G5/006—Details of the interface to the display terminal
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/36—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
    • G09G5/39—Control of the bit-mapped memory
    • G09G5/393—Arrangements for updating the contents of the bit-mapped memory
AU81720/98A 1997-06-27 1998-06-25 Multi-function controller and method for a computer graphics display system Abandoned AU8172098A (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US08/884,361 US6052133A (en) 1997-06-27 1997-06-27 Multi-function controller and method for a computer graphics display system
US08884361 1997-06-27
PCT/US1998/013356 WO1999000741A1 (en) 1997-06-27 1998-06-25 Multi-function controller and method for a computer graphics display system

Publications (1)

Publication Number Publication Date
AU8172098A true AU8172098A (en) 1999-01-19

Family

ID=25384452

Family Applications (1)

Application Number Title Priority Date Filing Date
AU81720/98A Abandoned AU8172098A (en) 1997-06-27 1998-06-25 Multi-function controller and method for a computer graphics display system

Country Status (3)

Country Link
US (2) US6052133A (en)
AU (1) AU8172098A (en)
WO (1) WO1999000741A1 (en)

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US6483516B1 (en) * 1998-10-09 2002-11-19 National Semiconductor Corporation Hierarchical texture cache
US6801207B1 (en) * 1998-10-09 2004-10-05 Advanced Micro Devices, Inc. Multimedia processor employing a shared CPU-graphics cache
US6560674B1 (en) * 1998-10-14 2003-05-06 Hitachi, Ltd. Data cache system
US6323866B1 (en) * 1998-11-25 2001-11-27 Silicon Integrated Systems Corp. Integrated circuit device having a core controller, a bus bridge, a graphical controller and a unified memory control unit built therein for use in a computer system
US6292201B1 (en) * 1998-11-25 2001-09-18 Silicon Integrated Systems Corporation Integrated circuit device having a core controller, a bus bridge, a graphical controller and a unified memory control unit built therein for use in a computer system
US6598110B1 (en) * 1998-11-25 2003-07-22 Texas Instruments Inc Method and apparatus for data conversion in a computer bus
US6362826B1 (en) 1999-01-15 2002-03-26 Intel Corporation Method and apparatus for implementing dynamic display memory
US6411301B1 (en) 1999-10-28 2002-06-25 Nintendo Co., Ltd. Graphics system interface
US6618048B1 (en) 1999-10-28 2003-09-09 Nintendo Co., Ltd. 3D graphics rendering system for performing Z value clamping in near-Z range to maximize scene resolution of visually important Z components
US6717577B1 (en) 1999-10-28 2004-04-06 Nintendo Co., Ltd. Vertex cache for 3D computer graphics
US6452600B1 (en) 1999-10-28 2002-09-17 Nintendo Co., Ltd. Graphics system interface
EP1157370B1 (en) 1999-11-24 2014-09-03 DSP Group Switzerland AG Data processing unit with access to the memory of another data processing unit during standby
US6636939B1 (en) * 2000-06-29 2003-10-21 Intel Corporation Method and apparatus for processor bypass path to system memory
US6754761B1 (en) * 2000-08-07 2004-06-22 International Business Machines Corporation Communications system including symmetric bus bridge and method used therewith
US6811489B1 (en) 2000-08-23 2004-11-02 Nintendo Co., Ltd. Controller interface for a graphics system
US6636214B1 (en) 2000-08-23 2003-10-21 Nintendo Co., Ltd. Method and apparatus for dynamically reconfiguring the order of hidden surface processing based on rendering mode
US7538772B1 (en) 2000-08-23 2009-05-26 Nintendo Co., Ltd. Graphics processing system with enhanced memory controller
US6700586B1 (en) 2000-08-23 2004-03-02 Nintendo Co., Ltd. Low cost graphics with stitching processing hardware support for skeletal animation
US6707458B1 (en) 2000-08-23 2004-03-16 Nintendo Co., Ltd. Method and apparatus for texture tiling in a graphics system
US7196710B1 (en) 2000-08-23 2007-03-27 Nintendo Co., Ltd. Method and apparatus for buffering graphics data in a graphics system
US6859208B1 (en) * 2000-09-29 2005-02-22 Intel Corporation Shared translation address caching
US6697074B2 (en) * 2000-11-28 2004-02-24 Nintendo Co., Ltd. Graphics system interface
US6738068B2 (en) * 2000-12-29 2004-05-18 Intel Corporation Entering and exiting power managed states without disrupting accelerated graphics port transactions
US6753873B2 (en) * 2001-01-31 2004-06-22 General Electric Company Shared memory control between detector framing node and processor
US6904481B1 (en) * 2001-04-12 2005-06-07 Lsi Logic Corporation Bus sequence operation with automatic linking from current I/O information to subsequent I/O information
JP2003085127A (en) * 2001-09-11 2003-03-20 Seiko Epson Corp Semiconductor device having dual bus, dual bus system, dual bus system having memory in common and electronic equipment using this system
US6891543B2 (en) * 2002-05-08 2005-05-10 Intel Corporation Method and system for optimally sharing memory between a host processor and graphics processor
US7149909B2 (en) * 2002-05-09 2006-12-12 Intel Corporation Power management for an integrated graphics device
US6973528B2 (en) * 2002-05-22 2005-12-06 International Business Machines Corporation Data caching on bridge following disconnect
US6937243B2 (en) * 2002-07-23 2005-08-30 Silicon Intergrated Systems Corporation Transmission circuit and manufacture method for the same
TW573256B (en) * 2002-09-25 2004-01-21 Via Tech Inc Core logic chip with multiple data channel
US8749561B1 (en) * 2003-03-14 2014-06-10 Nvidia Corporation Method and system for coordinated data execution using a primary graphics processor and a secondary graphics processor
US7484247B2 (en) * 2004-08-07 2009-01-27 Allen F Rozman System and method for protecting a computer system from malicious software
US20060064561A1 (en) * 2004-09-20 2006-03-23 Brad Simeral Method and apparatus for operating a memory controller
US20070067517A1 (en) * 2005-09-22 2007-03-22 Tzu-Jen Kuo Integrated physics engine and related graphics processing system
US8234482B2 (en) * 2005-10-13 2012-07-31 Google Inc. Universal embedded controller for freeing CPU from operations of peripheral subsystem units with table of functions including an instruction specifying battery controller select protocol
US8072547B2 (en) 2006-03-31 2011-12-06 Conexant Systems, Inc. Comb filter that utilizes host memory
US8775704B2 (en) * 2006-04-05 2014-07-08 Nvidia Corporation Method and system for communication between a secondary processor and an auxiliary display subsystem of a notebook
US8271827B2 (en) * 2007-12-10 2012-09-18 Qimonda Memory system with extended memory density capability
US8736617B2 (en) * 2008-08-04 2014-05-27 Nvidia Corporation Hybrid graphic display
US9075559B2 (en) * 2009-02-27 2015-07-07 Nvidia Corporation Multiple graphics processing unit system and method
US9135675B2 (en) * 2009-06-15 2015-09-15 Nvidia Corporation Multiple graphics processing unit display synchronization system and method
US8766989B2 (en) * 2009-07-29 2014-07-01 Nvidia Corporation Method and system for dynamically adding and removing display modes coordinated across multiple graphics processing units
US9111325B2 (en) * 2009-12-31 2015-08-18 Nvidia Corporation Shared buffer techniques for heterogeneous hybrid graphics
US8780122B2 (en) * 2009-09-16 2014-07-15 Nvidia Corporation Techniques for transferring graphics data from system memory to a discrete GPU
US9818379B2 (en) 2013-08-08 2017-11-14 Nvidia Corporation Pixel data transmission over multiple pixel interfaces
US9818337B2 (en) * 2014-07-24 2017-11-14 Sct Technology, Ltd. LED display control circuit with PWM circuit for driving a plurality of LED channels

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US5379384A (en) * 1992-06-05 1995-01-03 Intel Corporation Configuration data loopback in a bus bridge circuit
US5553220A (en) * 1993-09-07 1996-09-03 Cirrus Logic, Inc. Managing audio data using a graphics display controller
US5450542A (en) * 1993-11-30 1995-09-12 Vlsi Technology, Inc. Bus interface with graphics and system paths for an integrated memory system
US5793996A (en) * 1995-05-03 1998-08-11 Apple Computer, Inc. Bridge for interconnecting a computer system bus, an expansion bus and a video frame buffer
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US5712970A (en) * 1995-09-28 1998-01-27 Emc Corporation Method and apparatus for reliably storing data to be written to a peripheral device subsystem using plural controllers
US5850207A (en) * 1995-11-22 1998-12-15 Cirrus Logic, Inc. Method and apparatus for minimizing effects of slope overload condition when using differential pulse code modulation scheme
US5796413A (en) * 1995-12-06 1998-08-18 Compaq Computer Corporation Graphics controller utilizing video memory to provide macro command capability and enhanched command buffering
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US5678009A (en) * 1996-02-12 1997-10-14 Intel Corporation Method and apparatus providing fast access to a shared resource on a computer bus
US5748203A (en) * 1996-03-04 1998-05-05 United Microelectronics Corporation Computer system architecture that incorporates display memory into system memory

Also Published As

Publication number Publication date
US6480198B2 (en) 2002-11-12
US20010012015A1 (en) 2001-08-09
US6052133A (en) 2000-04-18
WO1999000741A1 (en) 1999-01-07

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Legal Events

Date Code Title Description
MK6 Application lapsed section 142(2)(f)/reg. 8.3(3) - pct applic. not entering national phase