AU716743B2 - PSK demodulator - Google Patents

Description

-1-

AUSTRALIA

PATENTS ACT 1990 COMPLETE SPECIFICATION FOR A STANDARD PATENT *4 *c

ORIGINAL

Name of Applicant: Itzhak Gurantz, Yoav G Itzhak Gurantz, Yoav G{

RA,

rg SEC S g Ina a 1 113 u oldenberg and Sree A Raghav -7 O- Actual Inventor: Address of Service: SHELSTON WATERS MARGARET STREET SYDNEY NSW 2000 Invention Title: "PSK DEMODULATOR" Details of Original Application No. 59615/94 dated 29 December 1993 The following statement is a full description of this invention, including the best method of performing it known to me/us:la- PSK DEMODULATOR Field of Invention The present invention relates generally to receivers and demodulators employing digital processing responsive to symbol containing analog signals.

Background Art Fig 1 is a block diagram of a prior art phase shift key receiver employing digital processing. The receiver is responsive to a noise ladened suppressed carrier quadrature phase shift key (QPSK) modulated electromagnetic wave incident on antenna 10. The wave incident on antenna 10 is transduced into an electrical signal that is amplified by RF and IF stages 12. The wave has a precisely controlled carrier frequency determined at an electromagnetic wave QPSK transmitter and includes symbols having a predetermined rate, frequency, 20 mHz.

:The output signal of stages 12 is applied in *o ooo I* 2 parallel to mixers 14 and 16, also respectively responsive to mutually orthogonal oscillations derived by 450 phase shifters 18 and 20. Phase shifters 18 and 20 are in turn responsive to voltage controlled variable frequency local oscillator 22, having an output frequency approximately equal to the suppressed carrier frequency derived from stages 12. The resulting outputs of mixers 18 and 20 are respectively applied to matched (to the transmitter waveform) low- 10 pass filters 24 and 26 which derive variable analog baseband signals representing symbols to be processed into intelligence representing output signals. The baseband output signals of filters 24 and 26 are typically referred to as I and Q channel signals.

The I and Q channel signals derived by filters 24 and 26 are respectively applied via variable gain *:"amplifiers 23 and 25 to analog-to-digital converters 28 and 30, operated to sample the baseband I and Q signal amplitudes at a variable frequency, typically approximately twice the symbol frequency. The gains of amplifiers 23 and 25 are controlled so that the maximum amplitude of the analog signals supplied to converters 28 and 30 equals the optimal range which the converters can handle. In normal operation, converters 28 and 30 sample the I and Q channel signals supplied to them twice per symbol, approximately in the center and between adjacent symbols. Converters 28 and derive multibit digital output signals representing the magnitude and polarity of each sample applied to the converters. Converters 28 and 30, included on separate integrated circuit chips, are relatively expensive because they must sample the baseband I and Q channel analog signals at a frequency of approximately mHz.

-3- The I and Q representing digital signals derived by converters 28 and 30 are applied in parallel to carrier tracker 32, symboi tracker 34 and amplitude tracker 36, all of which. are digital processing circuits included on a single custom integrated circuit chip. Carrier tracker 32 derives a digital signal having a value representing the polarity and magnitude of the frequency and phase differences between the output of oscillator 22 and the suppressed carrier output of stages 12. Symbol tracker 34 derives :i a digital signal having a value representing the polarity and magnitude of an error in the sampling times of converters 28 and 30 relative to idealized oositions for these sampling times. Amplitude tracker 15 36 responds to the I and Q outouts of converters 28 and and a reference value for the optimal amplitude at which the converters should operate to derive a control signal for variable gain amplifiers 23 and 25. The I and Q output signals of converters 28 and 30 are also 20 applied to output processing circuit 37. Typically, :the digital signals have eight to ten bits, particularly to provide necessary resolution for control of amplifiers 23 and The digital signals derived by trackers 32, 34 and 36 are respectively applied to digital to analog converters 38, 40 and 42, having analog output signals respectively applied to low-pass filters 44, 46 and 48.

The output signal of filter 44 controls the frequency and phase of oscillator 22 so they are ideally equal to the frequency and phase of the suppressed carrier frequency derived from stages 12. The output of filter 46 is supplied to voltage controlled, variable frequency oscillator 50, having an output controlling the phase of clock pulses derived by clock source 51.

-4- The clock pules derived by source 51 are applied in parallel to clock inputs of analog-todigital converters 28 and 30, to control when the converters take samples of the analog inputs supplied to them. The clock pulses supplied to the clock input of converters 28 and 30 have a frequency approximately equal to twice the frequency of the symbols applied to the converters. The output of low-pass filter 48 is supplied in parallel to gain control inputs of variable gain amplifiers 28 and While the apparatus of Fig. I performs satisfactorily, it is excessively expensive for consumer appli-cations, involving manufacture of perhaps millions of units, and wherein cost savings of even a few cents per unit can be critical. Additionally, the prior art requires a comparatively large amount of semiconductor structures and excessive :I reliance upon digital-to-analog converters and low pass filters.

An object of the invention is to overcome, or substantially ameliorate at least one of the disadvantages of the prior art.

The Invention 00.

In accordance with the invention there is provided a demodulator responsive to S:'i symbols of an analog signal including residual components due to frequency and phase errors between a carrier on which the signal is modulated and a local frequency source, comprising means responsive to the analog signal for deriving first I and Q channel digital signals having values determined by sampled amplitudes, including the residual components, of the analog signal, and means responsive to the first I and Q channel digital signals for deriving second I and Q channel digital signals corrected for the frequency and phase errors and a third digital signal having a value representing the frequency and phase errors, the second I and Q channel digital signals being derived by combining the first I and Q channel digital signals and the third digital signal in accordance with a CORDIC function.

The straightforward approach for deriving the second I and Q channel digital signals, which has generally been employed in prior art demodulators, is to use a table look-up read only memory (ROM) for deriving signals representing the sine and cosine of an angle indicative of the frequency and phase errors. The values of the signals read from the ROM are combined with the values of the first digital signals in accordance with a pair of equations to derive the second I and Q digital signals. The prior art approach, however, requires an excessively large amount of semiconductor Se S 4 4 .44 44 44i 6 structures. The equations are solved with about a savings in the number of gates by utilizing the CORDIC functions rather than the table look-up approach.

Preferably the CORDIC function approach and sampling the analog signal amplitude at approximately the symbol rate are combined in a single device to reduce total cost.

The demodulator is preferably included in a receiver having a local frequency source having an output with a nominal frequency susceptible to variation from a set value thereof and means for combining an input signal including symbols modulated on a carrier frequency and the output of the local source. The I and Q channel digital signals have values determined by the modulation and by the frequencies and phases of the carrier and the local source. The values of the second I and Q channel digital signals are compensated by the value of the third digital signal. A variable digital phase shifter 20 has first and second inputs respectively responsive to at least one of the digital signals and clock pulses having approximately an integral multiple (including one) of the symbol rate for controlling sampling times by the analog-to-digital converting means of the signal at approximately the rate so that as the value at the first input of the phase shifter changes the sampling times change. This digital approach to controlling sampling time and compensating for frequency and phase errors, in combination with once per symbol sampling, obviates the need for digital-to-analog converters and extra low pass filters, while permitting inexpensive analog-to-digital converters. Additional cost savings are provided by using the CORDIC function and a relatively inexpensive one-bit sigma-delta modulator -7for deriving a gain control signal for amplifiers that control the amplitude of the analog signal applied to the analog-to-digital converter means.

in a preferred embodiment, the first input of the digital phase shifter is responsive to a comparison of indications of a function of the values of at least one of the digital signals for differing samples and taken by the converter means. The first input is derived as a function of(sign P(k-1) (-sign P(k), where P(k) is the value of an indication of a sample taken by the converter means for symbol k, and P(k- 1) is the value of the indication of the sample taken by the converter means for symbol Control for the first input is preferably in response to one or both of the second digital signals.

Unless the context clearly requires otherwise, throughout the description and the claims, the words 'comprise', 'comprising', and the like are to be construed in an inclusive as opposed to an exclusive or exhaustive sense; that is to say, in the sense of "including, but not limited to".

The above and still further objects, features and advantages of the present invention will become apparent upon consideration of the following detailed description .o of several specific embodiments thereof, especially when taken in conjunction with the accompanying drawings.

20 Brief Description of Drawings •coco, Fig. 1, as previously indicated, is a block diagram of a prior art phase shift key receiver and demodulator employing digital processing circuitry; Fig. 2 is a block diagram of a preferred embodiment of a receiver and demodulator employing digital processing circuitry in accordance with the present 25 invention; Fig. 3 is a block diagram of a derotator employed in Fig. 2; 441 bp3 1 1 8 Fig. 3A is a block diagram of one stage of the derotator of Fig. 3; Fig. 4 is a block diagram of a symbol tracker employed in Fig. 2; Fig. 5 is a block diagram of an error metric calculator of Fig. 4; Fig. 6 is a block diagram of a carrier tracker employed in Fig. 2; Fig. 7 is a block diagram of an amplitude tracker employed in Fig. 2; and Fig. 8 is a block diagram of an alternate symbol tracker employed in Fig. 2.

Description of the Preferred Embodiment Reference is now made to Fig. 2 of the drawing, wherein the front end of a receiver and demodulator in accordance with a preferred embodiment of the present invention is illustrated as being essentially the same as the front end of the prior art receiver illustrated in Fig. 1 and thereby includes antenna 10, RF and IF 20 stages 12, mixers 14 and 16, +45 and -450 phase shifters 18 and 20, matched low pass filters 24 and 26, and variable gain amplifiers 23 and 25. variable S• frequency, voltage controlled oscillator 22 is replaced by local oscillator 21 having an output frequency nominally equal to the fixed frequency output of stages 12; oscillator 21 has no control input terminal.

Because the receiver and demodulator of Fig. 2 is preferably of a type employed for consumer applications, the frequency of oscillator 21 is not particularly stable, being susceptible to considerable variation during use, as well as being subject to variation from unit to unit due to manufacturing tolerances.

9 The baseband, analog I and Q channel output signals of matched filters 24 and 26 are applied to analog to digital converters 54 and 56, respectively.

Converters 54 and 56 sample the output signals of filters only once during each symbol of I and Q quadrature phase shift key analog signals derived by matched filters 24 and 26. To minimize cost, converters 54 and 56 are incapable of sampling the signals applied by them twice per symbol as is required 1. 10 for converters 28 and 30 of the prior art. Hence, the cost of converters 54 and 56 and the digital circuitry they drive is considerably less than the cost of :converters 28 and 30 and the digital circuits they drive. The I and Q baseband signals of Fig. 2 need be sampled by converters 54 and 56 only once per symbol because of the nature of symbol tracking processing employed in Fig. 2, as discussed infra.

In one preferred embodiment for sampling at mHz, each of converters 54 and 56 is SONY type CXD 20 1172AM; the comparable SONY D1179Q or TRW 1175N2C40 converter, capable of sampling at 40 mHz, costs approximately 400% more than the SONY CXD1172AM.

While the present invention is particularly adapted to handle 15-35 megasymbols per second, many of the principles are applicable to other symbol rate ranges.

Converters 54 and 56 derive digital signals having values representing the polarity and magnitude of the analog input signals sampled by them. In the preferred embodiment, each of converters 54 and 56 derives a sixbit signal for each sample. For lower resolution, each of converters 54 and 56 can produce a four-bit signal in response to each sample.

The I. and Qin channel digital output signals of converters 54 and 56 have amplitudes that are 10 determined by the QPSK modulation on the suppressed carrier supplied to mixers 14 and 15, (b) error components due to differences in the frequency and phase of the output of local oscillator 21 relative to the frequency and phase of the suppressed carrier supplied to mixers 14 and 16 by stages 12, and (c) error components due to differences in the symbol rate and the sampling rate of converters 54 and 56. The I.

in and Qin signals are supplied to custom large scale 10 integrated digital processing circuit 57 included on a single integrated circuit chip. Circuit 57 includes derotator circuit 58, which responds to I. and Q, as in in, well as a digital signal, c, representing the error components of the frequency and phase differences.

Digital derotator 58 responds to the input signals thereof to derive digital output signals I and Q in accordance with: I I. cosc Qi sind (1) Q Q. cos4 in sine (2) i-n in The I and Q digital output signals of derotator 58 are corrected for the frequency and phase offset between the output frequency (w 0 of local oscillator 21 and the suppressed carrier output frequency (wg) of amplifier 12. The values of I and Q are computed in accordance with a CORDIC function, described infra, causing a substantial reduction in cost over the prior art look-up table or Taylor series approaches because there is about a 50% reduction in the number of gates in the CORDIC implementation relative to these implementations.

The I and Q output signals of derotator 58 are applied in parallel to output device 37, carrier tracker 60, symbol tracker 52 and automatic gain 11 controller 64; the latter three are included on the single integrated circuit chip containing processing circuit 57. Carrier tracker 60 derives a digital output signal having polarity and magnitude bits representing 0, the difference between the frequencies and phases of local oscillator 21 and the suppressed carrier of stages 12; the digital signal is applied as the phase input signal to digital derotator 58 without conversion to an analog signal, which helps to reduce cost.

The digital output signal of symbol tracker 62, having a polarity and magnitude representing the time shift necessary for correct sampling of each symbol applied to analog-to-digital converters 54 and 56, is a control input of digital asynchronous phase shifter 66, included in digital processing circuit 57 on the single integrated circuit chip. Phase shifter 66 is preferably of a type described in the co-pending, commonly assigned application entitled "Asynchronous 20 Digital Phase Shifter," filed December 23, 1992, by Goldenberg et al. (Lowe, Price, LeBlanc Becker Docket 1559-001). Phase shifter 66 is also responsive to clock source 68, having a frequency slightly greater than the frequency of symbols of the baseband I and Q channel signals supplied to analog-to-digital converters 54 and 56; alternatively, in certain situations where certain operations are performed at a frequency that is approximately an integral multiple, greater than one, of the symbol frequency, clock 68 has a frequency that is approximately the symbol frequency times the multiple and phase shifter 66 includes a frequency divider having a division factor equal to the multiple for deriving the sampling pulses applied to the converters. Phase shifter 66 responds to the 12 output of symbol tracker 62, to control when pulses from clock source 68 are applied to clock or sample control inputs of analog-to-digital converters 54 and 56 once per symbol.

Automatic gain controller 64 responds to the I and Q outputs of derotator 58 to derive a signal for controlling the gains of amplifiers 23 and Controller 64 includes a relatively inexpensive one bit sigma-delta modulator, preferably of a type described by Agrawal et al. in an article entitled "Design S: Methodology for CM, IEEE Transactions on Communications, Vol. No. 3, March, 1983, pages 360-369, to obviate the requirement for an eight-to-ten bit digital signal that must be applied to conventional 15 digital-to-analog converter 42 of Fig. 1. The resulting variable frequency constant amplitude and duration output pulses of the modulator in controller 64 are applied to low-pass filter 70, having an analog output which is supplied to gain control inputs of 20 amplifiers 23 and Reference is now made to Fig. 3 of the drawing, a conceptual block diagram of derotator 58 for computing the values of I and Q in accordance with Equations (1) in response to Iin, Qi and 4. The n in straightforward approach to calculate the values of I and Q is to use table lookups or sine and cosine multipliers for the values of sin and cos 4 in Equations 1 and 2. However, these straightforward approaches use an excessive amount of integrated circuit elements. By using the so-called CORDIC function approach, as disclosed by Voider, the number of integrated circuit elements is reduced by a factor of approximately 50%, to provide a considerable cost savings.

13 The CORDIC computer of Fig. 3 includes M+1 cascaded stages 80.0, 80.1, 80 2 80.k...80.(M) (where M is an odd integer), such that stage 80.0 is responsive to the Iin and Qin outputs of analog-todigital converters 54 and 56, and succeeding stages are responsive to output signals I(kl) and Q(k-1) of stage Latches (where p and M are odd integers and there is an even number oof stages 80 in the circuit of Fig. 3), 10 connected between the outputs of the odd-numbered stages and the adjacent next higher-numbered even stage, are activated at the same frequency as the sampling frequency for converters 54 and 56. In addition, stages 80.0...80.k...80.M are respectively responsive to values of M as derived by V calculator 82, which responds to the 4 output signal of carrier tracker 60 (which is in two's complement notation) and the sampling pulses supplied by phase .shifter 62 to converters 54 and 56. 5 calculator 82 20 responds to the value of 4 to derive, for each of stages 80.0, 80.1, 80.2...80.k...80.M a one bit value, which is either a 0 or 1.

In steady state, the values of are calculated once for each symbol time of the analog signal supplied to converters 54 and 56. For each set of lin and Qin stage 80.M derives a set of I and Q values which are the outputs of derotator 58. The value of f is the most significant bit of 4, as derived from carrier tracker 60; the value of 1i associated with stage 80.1 is the second most significant bit of 4; Associated with each of (2 5M are values of 42 6M. The value of b2 equals the value of 4, with the two most significant bits truncated and the third most significant bit reversed in digital value. Each 14 value for stages 80.2-80.M is associated with a predetermined angle, such that the value of a2 for stage 80.2 is 26.5*, the value of a3 for stage 80.3 is 14.04, etc., such that .j arc tan j is selectively each of integers In one preferred embodiment, M-7, so there are eight stages 80.0-80.7.

The inputs of stages 80.2-80.M are combined after selective bit shifting and polarity reversal as a function of 5 so that, Ik k-1 1 -2k) Qk-1 2 and (3) Qk-i 2 Ik-1 2 (4) Stage 80.0 responds to I. and Q. to derive I0 and Q in accordance with 15 I (1-2f) Qin and QO Iin (6) Swhile stage 80.1 derives I 1 and Q in accordance with I I (1-2fi) QO and (7) Q1 QO IO. (8) 20 Since (1- 2 5j) and can have values of only +1

J

and the multiplications by (1-2j) and (2jj-1) basically involve selective reversal or non-reversal of the most significant, polarity indicating bits of the S. Qki and Ik inputs of a particular stage; these operations are easily performed with half adders.

Multiplication by 2 -(k-1 is also easily performed by shifting the bits to the right stages in a shift register.

Zeta calculator 82 responds to the value of 4, as derived from carrier tracker 60, to derive the one bit values of k For the specific configuration illustrated in Fig. 3, the most significant and second most significant bits of b, as derived from carrier tracker 60, are respectively 15 supplied to the inputs of stages 80.0 and 80.1 as signals 0 and The third most significant bit (with a polarity reversal by inverter 83) in the value of o and the remaining bits in the value of b, as derived from carrier tracker 60, are supplied to block 84.2, which derives f inputs £2 and f3 for stages 80.2 and 80.3, as well as a multi-bit signal 44, having a value determined by the b2 input of block 84.2 and the values-of a 2 and a3 stored in block 84.2.

10 The (4 output of f block 84.2 is supplied to latch 86.4, which is activated by the output of phase shifter 66 simultaneously with latches 81.1-81.(M-2). Latch 86.4 supplies block 84.6 with a latched replica of the 4 output of f block 84.2. block 84.4 responds s" 15 to the output of latch 86.4 and the values of a 4 and a stored therein to derive one-bit signals 4 and respectively supplied to inputs of stages 80.4 and 80.5. In addition, f block 84.4 derives a multi-bit signal determined by the output of latch 86.4 and 20 the values of a 4 and a 5 stored in the f block. The (6 multi-bit output of c block 84.6 is supplied to latch 86.6, which responds to pulses from phase shifter 66 to 0 0 supply a latched replica of the 46 output of f block 84.4 to f block 84.6. block 84.6 responds to the output of latch 86.6 and values of o6 and a 7 stored therein to derive one-bit 56 and f7 signals which are supplied to the c inputs of stages 80.6 and 80.7.

All of c blocks 84.2, 84.4 and 84.6 are identical in configuration except for the values of a stored therein. Therefore, a description of f block 84.2 suffices for the description of f blocks 84.4 and 84.6.

As illustrated in Fig. 3, f block 84.2 responds to the value of 2 to derive the (41 '2 and £3 signals. block 84.2 includes pre-wired multi-bit digital 16 registers 88.2 and 88.3 that respectively store digital values representing a 2 (26.50) and a3 (14.040). The most significant polarity indicating bits of the signals stored in registers 88.2 and 88.3 are reversed in polarity to derive digital values respectively representing -a 2 and -a3; the values of -a2 and -a3 are stored in pre-wired registers 88.2' and 88.3', respectively. The digital levels stored in registers 88.2 and 88.2' are supplied to signal inputs of 10 multiplexer 90.2, while the signals stored in registers 88.3 and 88.3' are supplied to the signal inputs of multiplexer 90.3. Multiplexer 90.2 includes a control :input terminal responsive to the'most significant bit in so that as the binary value of the most significant bit of (2 changes, the values of a 2 and -a 2 as supplied to the inputs of the multiplexer by registers 88.2 and 88.2' are selectively supplied to the multi-bit output of multiplexer 90.2. The multibit output of multiplexer 90.2 and the multi-bit value 20 of (2 supplied to calculator 84.2 are combined in digital adder 92.2, which derives a 43 multi-bit output .equal to the sum of b2 and the output of multiplexer 90.2. The most significant bit in the (b output of adder 92.2 is coupled to the control input of multiplexer 88.3, to control coupling of one of the a 3 and -a 3 inputs of the multiplexer to the multiplexer output. The multi-bit outputs.of multiplexer 90.3 and adder 92.2 are added together in digital adder 92.3, which derives a 44 multi-bit output that is supplied to the input of block 84.4.

The most significant bits in 02 and as supplied to the control inputs of multiplexers 90.2 and 90.3, are respectively reversed in binary level by inverters 94.2 and 94.3. Inverters 94.2 and 94.3 thus 17 derive one bit outputs which are the two's complement of the most significant bits of b2 and b3 to provide signals having values equal to (2 and C3. The outputs of inverters 94.2 and 94.3 must be maintained constant for one symbol time, a result achieved by supplying the outputs of inverters 94.2 and 94.3 to latches 96.2 and 96.3, activated by the same sampling pulses which are applied by phase shifter 66 to converters 54 and 56.

Thereby, latches 96.2 and 96.3 derive constant binary 10 values indicative of '2 and 3 for the interval of each sample taken by converters 54 and 56. The outputs of latches 96.2 and 96.3 are respectively supplied to the inputs of stages 80.2 and 80.3. Blocks 84.4 and 84.6 are similarly constructed to supply C4 7 inputs to 15 the inputs of stages 80.4 80.7, respectively.

To solve Equations and stage 80.0 includes multipliers 110 and 112, respectively responsive to the Iin and Qin signals derived from converters 54 and 56. Multipliers 110 and 112 are also respectively responsive to the values of and 2 having tl values respectively derived by circuits 114 and 116, both of which are responsive to the value of 0. In actuality, multiplier 110 and circuit 114 perform modulo 2 addition, with a binary half adder, on the one bit values of g0 and the most significant, polarity indicating bit of I. (Numerous other multiplications and operations involving (1-2(k) and (2 k- 1 are performed by stages 80.0-80.M in a similar manner.) The outputs of multipliers 110 and 112 are respectively supplied to 10 and Q 0 outputs of stage 80.0.

To solve Equations and stage 80.1 includes multipliers 118 and 120, respectively responsive to the I 0 and Q00 outputs of stage 80.0 that F I 18 are applied to inputs of stage 80.1. Multipliers 118 and 120 are also responsive to t1 values computed in accordance with (2i-i1) and (1-2fI) by circuits 122 and 124, both of which are responsive to the value of The resulting product outputs of multipliers 118 and 120 are respectively supplied to one input of adders 126 and 128. The other inputs of adders 126 and 128 are respectively responsive to the Q0 and 1 0 signals supplied to stage 80.1. Adders 126 and 128 10 respectively derive output signals representing Q1 and I The remaining stages 80.2...80.k...80.M are very similar to each other, and generally take the form indicated by the circuit diagram of Fig. 3A for stage 15 80.k, which is used to solve Equations and Stage 80.k responds to Ik-1 and Qk- output signals of stage The Ik- 1 and Qk- input signals of stage 80.k are respectively supplied to one input of adders 130 and 132. The other input of adder 130 is derived by shifting the Qk-I input of stage 80.k to the right by bits in shift register 134, having an Soutput that is supplied to one input of multiplier 136.

The remaining input of multiplier 136 is (1-2 as derived by circuit 138 in response to the k input signal supplied to it. The output of multiplier 136 is supplied to the other input of adder 130.

The remaining input of adder 132 is derived by supplying the Ik-1 input of stage 80.k to shift register 140, which shifts the Ik-i signal to the right by bits. The output of shift register 140 is multiplied in multiplier 142 by (2 k- 1 a signal that is derived by circuit 144 in response to the value of k. The output of multiplier 142 is supplied to the remaining output of adder 132. Adders 130 and 132 19 respectively derive output signals indicative of Ik and Qk" While the apparatus of Fig. 3 is illustrated as including separate stages 80.0-80.M, it is to be understood that in the preferred embodiment it is not necessary to use stages. Instead, a plurality of such stages are employed in the preferred embodiment and output signals from the "last" stage are recirculated back to a previous stage, to minimize 10 hardware requirements.

Figure 4 is a block diagram of symbol tracker 62, which responds to one or both of the I and Q output signals of derotator 58 to derive a control signal for digital phase shifter 66, also responsive to clock 68.

15 Phase shifter 66 controls when sampling pulses are supplied to analog-to-digital converters 54 and 56. In the preferred embodiment, the I and Q output signals of derotator 58 are supplied to error metric computer 150 which basically compares the amplitudes of adjacent samples taken by analog-to-digital converters 54 and 56 of the analog I and Q baseband signals. From the adjacent sampled values, a determination is made of the approximate deviation of the adjacent symbols from a zero crossing line. Ideally, each sampling pulse supplied to converters 54 and 56 occurs in the center of each symbol supplied to the converters. Symbol timing error is calculated in accordance with: (sign (-sign (sign (-sign (9) where I(k) is the value of an indication of I for symbol k I(k-1) is the value of the indication.of I for symbol (k-1) Q(k) is the value of the indication of Q for 20 symbol k, and Q(k-l) is the value of the indication of Q for symbol The symbol timing error signal for a pair of adjacent bits, as derived from error metric calculator 150, is supplied to digital loop filter 152, basically a low pass filter having a cutoff frequency that is a fraction of a percent of the frequency of clock 68.

The output of loop filter 152 is supplied to integrator 10 154 which accumulates the filtered symbol timing error values to derive a signal representing the actual value of a phase shift to be imposed on pulses from clock 68, so sampling pulses are supplied once per symbol to analog-to-digital converters 54 and 56 at approximately the center of each symbol. The digital output signal of integrator 154 is supplied to digital phase shifter 156, preferably of a type disclosed in the copending, commonly assigned application of Goldenberg et al., Lowe, Price, LeBlanc Becker, Docket 1559-001. Pulses 20 from clock 68 supplied to phase shifter 156 have a frequency slightly above the frequency of the symbols supplied to converters 54 and 56. Basically, phase shifter 156 responds to the digital control signal supplied thereto by integrator 154 -to delay selected pulses from clock 68, to provide sampling pulses to analog-to-digital converters 54 and 56 with the required timing.

A preferred configuration for symbol timing error metric calculator 150 is illustrated in Figure 5 as including I and Q symbol timing error calculating channels 160 and 162. The symbol timing error calculations made by channels 160 and 162 are combined in adder 164 to derive a composite symbol timing error output signal. Since I and Q channels 160 and 162 are

C-

21 identical, a description of only the I calculating channel is provided. Corresponding elements of the Q channel are indicated on Figure 5 with the same reference numerals as the reference numerals for the I channel, except that each reference numeral in the Q channel is followed by the designation I calculating channel 160 responds to the I output of derotator calculator 58 for sample k taken by analog-to-digital converter 54; this input to channel 1 0 160 is designated as The I(k) input to channel 160 is delayed by the time between adjacent symbols of the baseband signal supplied to converter by delay unit 166. Delay unit 166 thereby derives an output signal having a value that is a function of the sample taken by analog-to-digital converter of symbol The I(k-1) output of delay unit 166 is supplied to one input of multiplier 168, having a second input equal to the sign of the value of the polarity S* indicating most significant bit of as derived from sign detector 170. The output of multiplier 168 is supplied to one input of adder 172 in accordance with sign I(k-1).

The other input to adder 172 is a digital signal equal to -sign Irk). To these ends, the most significant bit of the I(k-1) output of delay unit 166 is inverted in binary value by -sign element 174; the inverted output of the -sign element 174 is applied to one input of multiplier 176 having a second input equal to The resulting product output of multiplier 176 is applied to the second input of adder 172 which thereby derives an output signal in accordance with: sign I(k)I(k-l) (-sign Q channel 162 responds to digital signal Q(k) and derives a similar output in accordance with: 22 sign Q(k)Q(k-l) (-sign (11).

The resulting outputs of I and Q channels 160 and 162 are combined in adder 164 which derives an output signal representing the symbol timing error for a pair of adjacent symbols in accordance with Equation supra.

It is not necessary in all instances to employ the I and Q channels. Only one of the channels can be used in certain situations to derive the symbol error 10 correction signal. While it is preferable for the outputs of derotator 58 to be applied to symbol tracker S•62, the outputs of converters 54 and 56 can be applied directly to the symbol tracker with decreased resolution in the signal derived from output device 37.

15 Reference is now made to Figure 6 of the drawing, a block diagram of carrier tracker 60 responsive to the I and Q outputs of derotator 58 employed for deriving a signal indicative of the frequency and phase errors between the frequency and phase of local oscillator 21 and the frequency and phase of the suppressed carrier of the RF signal supplied to mixers 14 and 16. The Scircuit of Figure 6 includes error metric calculator *180 which basically compares the amplitudes of the I and Q outputs of the derotator 58 to derive a signal in accordance with: (-sign (sign I)Q (12).

Phase error metric calculator 180 includes multipliers 182 and 184, having first inputs respectively responsive to the I and Q outputs of derotator 58. A second input of multiplier 182 is responsive to -sign Q (as derived from sign detector 186), while a second input of multiplier 184 is equal to sign I, as derived from sign detector 188. The outputs of multipliers 182 and 184 are combined in 23 digital adder 190, which derives an output signal in accordance with Equation supra. The output of adder 190 thus represents the total phase error between the output of local oscillator 21 and the carrier frequency supplied to mixers 14 and 16.

The output signal of phase error metric calculator 180 is supplied to low pass loop filter 192, having a cutoff frequency that is between a fraction of a percent and a few percent of the frequency of clock 68.

The output of loop filter 192 is accumulated in integrator 194, having an output signal representing the phase correction b to be applied to derotator 58.

Reference is now made to Fig. 7 of the drawing, a block diagram of automatic gain controller 68 for 15 variable gain amplifiers 23 and 25, causing the amplitudes of the baseband AC signal supplied to digital-to-analog converters 54 and 58 to be controlled. Basically, the circuit of Fig. 7 determines the magnitude of the I or Q signal having the largest value, compares it with a reference value and supplies a smoothed resulting error signal to a one bit E-a modulator, of the aforementioned type disclosed by Agrawal. The E-A modulator derives a series of fixed duration, variable frequency pulses that are averages by a low-pass filter to provide an analog output signal that is supplied as a gain control signal to amplifiers 23 and 25. The use of a one bit 2-a modulator for digital-to-analog converter purposes is highly advantageous because of the relatively low cost thereof to achieve approximately the same resolution as is attained by 8-10 bit digital-to-analog converter 42.

To these ends, the I and Q signals derived by derotator 58 or the Iin and Qin output of converters 54 and 56 are supplied to absolute value circuits 196 and 24 198, respectively; in the illustrated embodiment the derotator outputs are supplied to the absolute value circuits. Absolute value circuits 196 and 198 remove the polarity indicating most significant bits from the I and Q signals, which are then supplied to comparator 200. Comparator 200 selects the I or Q signal having the largest magnitude and subtracts it from a reference value associated with maximum magnitude of the analog inputs of analog to digital converters 54 and 10 56. The resulting digital error signal is supplied to low-pass loop filter 202 having a cutoff frequency that is a few percent of the frequency of clock 68. The output of loop filter 202 is supplied to one bit E-A modulator 204, included on the same integrated circuit chip as circuits 58, 60 and 62. E-a modulator 204 .derives a series of variable frequency constant amplitude pulses which are averaged by low-pass filter into a variable amplitude analog signal that is supplied as gain control signals for variable gain amplifiers 23 and An alternate embodiment for controlling when timing pulses are supplied to analog-to-digital converters 54 and 56 is illustrated in Fig. 8. Fig. 8 is similar to Fig. 4, in that both include symbol error metric calculator 150, Fig. 5, which drives loop filter 152. However, the circuit of Fig. 8 does not include clock source 68 and digitally controlled phase shifter 66. Instead, the output of filter 152 is supplied to one bit E-a modulator 206, included on the same integrated circuit chip as circuits 58, 60 and 62. Modulator 206 derives a series of variable frequency constant amplitude pulses that are supplied to low-pass filter 208, having an analog output applied to a frequency control input of voltage controlled 25 oscillator 210. Voltage controlled oscillator 210 derives an output having a frequency equal approximately to the frequency of the symbols applied to analog-to-digital converters 54 and 56. The output of oscillator 210 is applied to the clock input of converters 54 and 56 causing the converters to sample the symbols of the baseband analog signals applied to them once per symbol, preferably in the center of each symbol.

10 While there have been described and illustrated plural specific embodiments of the invention, it will be clear that variations in the details of the embodiments specifically illustrated and described may be made without departing from the true spirit and scope of the invention as defined in the appended claims.

0 ft o eeoee•i

Claims (7)

1. 4. digital signals corrected for the frequency and phase errors and a third digital signal having a value representing the frequency and phase errors, the second I and Q channel 0 to digital signals being derived by combining the first I and Q channel digital signals and the third digital signal in accordance with a CORDIC function. The demodulator of claim 1 wherein the symbols have a rate and the means for t deriving the first digital signals samples the analog signal amplitude at approximately the symbol rate, and means responsive to at least one of the digital signals for controlling 0. I: 15 when the analog signal is sampled. 0 3. The demodulator of claim 1 wherein the symbols have a rate and the means for deriving the first digital signals samples the analog signal amplitude at approximately the symbol rate, and means, responsive to at least one of the second digital signals for controlling when the analog signal is sampled only once during a symbol. 2o 4. The demodulator of claim 1 wherein the symbols have a rate, the means for deriving the first I and Q channel digital signals comprising analog-to-digital converter means for sampling I and Q channel analog baseband signals at approximately the rate so that each symbol is sampled only once by the converter means, sampling times of the -27- I and Q channel analog baseband signals at the rate being controlled in response to a function of at least one of the I and Q channel digital signals. The demodulator of claim 4 wherein the analog-to-digital converter means includes an integrated circuit analog-to-digital converter, the integrated circuit analog-to- digital converter being incapable of sampling the symbols at a rate appreciably higher than the symbol rate, the symbol rate and the integrated circuit analog-to-digital converter being such that the cost of a comparable analog-to-digital converter integrated circuit capable of sampling the symbols at twice the rate is at least approximately higher than the cost of said integrated circuit analog-to-digital converter.
2. 6. The demodulator of claim 1 wherein the symbols have a rate, the means for deriving the first I and Q channel digital signals comprising analog-to-digital converter means for sampling I and Q channel analog baseband signals at approximately the rate so that each symbol is sampled only once by the converter means, sampling times of the I and Q channel analog baseband signals at the rate being controlled in response to the 15 second I and Q channel digital signals.
3. 7. The demodulator of claim 1 wherein the means for deriving the second I and Q channel digital signals derotates the first I and Q channel digital signals in accordance with the CORDIC function and includes a feedback loop for adjusting the value of the third digital signal by digital signal processing of the second I and Q channel digital signals.
4. 8. The demodulator of any one of claims 1-7 wherein the demodulator is included in a receiver having a local frequency source having an output with a nominal i/ r frequency susceptible to variation from a set value thereof and means for combining -28- an input signal including symbols modulated on a carrier frequency and the output of the local frequency source, the I and Q channel digital signals having values determined by the modulation and by the frequencies and phases of the carrier and the local frequency source, the values of the second I and Q channel digital signals being compensated by the value of the third digital signal, and further including: a variable digital phase shifter having first and second inputs respectively responsive to at least one of the digital signals and clock pulses having approximately an integral multiple of the symbol rate for controlling sampling times by the analog-to-digital converting means of the signal at approximately the rate so that as the value at the first input of the phase shifter changes the sampling times change.
5. 9. The demodulator of claim 8 further including a one-bit sigma-delta modulator for deriving a gain control signal, and an amplifier responsive to the gain control signal for controlling the amplitude of the analog signal applied to the analog-to-digital converter means. o 15 10. The demodulator of claim 8 or 9 wherein digital circuitry responsive to outputs of the analog-to-digital converter means causes the first input of the digital phase shifter S to be responsive to a comparison of indications of a function of the values of at least one S.:i of the digital signals for differing samples and taken by the converter means, the first input being derived as a fimunction of(sign P(k) P(k-1) (-sign P(k), 20 where P(k) is the value of an indication of a sample taken by the converter means for symbol k, and P(k-l) is the value of the indication of the sample taken by the converter means forsymbol -29-
6. 11. The demodulator of claim 10 wherein control for the first input is in response to only one of the second digital signals.
7. 12. The demodulator of claim 10 wherein control for the first input is in response to both of the second digital signals. DATED this 8th Day of April, 1999. COMSTREAM CORPORATION Attorney: JOHN B. REDFERN Fellow Institute of Patent Attorneys of Australia of SHELSTON WATERS e• 0 0 0 0 0 0000 0 0 *0. 0 0