AU714593C - Improved method of round robin bus arbitration - Google Patents

Description

IMPROVED METHOD OF ROUND ROBIN BUS ARB ITRATION Background of the Invention

The present invention relates to the field of digital data processing systems, and more particularly, to the field networks wherein units of the network are connected to a high speed bus requiring arbitration for access and data transfer.

As is well know in the art, as computer networks have grown in size and complexity, the need for high speed data transfer has increased. Among the types of data transfer devices which provide high speed transport between shared resources, such as bridges or switches, is the use of a high speed shared channel or bus. With such an arrangement, network efficiency and utilization is strongly affected by the procedure for controlling access to the high speed bus or channel.

As is also known, in general a transmission of data between two units over a high speed bus or channel requires two steps, since more than one unit has the capability of originating a transmission. The first step is for the transmitting unit to obtain control of the bus for some more or less defined interval. Once the selection step is completed, a second (or transfer) step is used to complete that transfer that is controlled by the selected transmitting unit.

Obtaining control of the bus requires contending with other units desiring bus access, to arbitrate and determine which one will be selected. As is known in the art, there are two principal generic approaches to arbitration. These are central arbitration and distributed arbitration. In the central arbitration, a single, central priority circuit or device receives all the requests for bus access and determines which requesting unit at any given time should be accorded the greatest priority and allowed to use the bus. Once the unit is selected, it is allowed to control the bus and effect the transfer. By contrast, in distributed arbitration, each unit connected to a bus is assigned a specific priority and each unit individually determines whether it has sufficient priority to obtain control of the bus when it desires to do so. If a unit of higher priority simultaneously seeks bus access, a device of lower priority must wait until some later time when it is the highest priority requester.

As is also known, in choosing a method of arbitration, fairness is assured when each unit connected to the bus has substantially equal average priority for obtaining bus access. In one such approach to guaranteeing fairness is a primitive round robin method. With such a method, for each unit, two delay interval possibilities exist; the delay selection for each unit is switched from time to time, on a round-robin basis, such that all units ts& given equal average priority.

In today's networks, data of more man one protocol may also coexist and be transferred from unit to unit in the network via the high speed bus. Examples of different protocols are Ethernet, FDDI, and Asynchronous Transfer Mode (ATM). Therefore, a method of arbitration is required that will not only guarantee fairness, but one that can handle data of both similar and different protocol.

Summary of the Invention

In accordance with one embodiment of the present invention, a method of round robin bus arbitration includes the steps of providing a plurality of modules, providing a bus

2 SUBSTITUTE SHEET (RULE 25) having a plurality of data lines, the bus connecting the plurality of modules, the bus having an arbitration unit, setting the bus to a wait state, signaling a first bus request to the bus by a first module needing to transmit a first plurality of data packets on to d e bus, the first module having a first module priority level and a first unique arbitration number, signaling a second bus request to the bus by a second module needing to transmit a second plurality of data packets on to the bus, the second module having a second module priority level and a second unique arbitration number, establishing a bus priority according to a comparison of the first module priority level and the second module priority level, asserting the first unique arbitration number on the bus by the first module, asserting the second unique arbitration number on the bus by the second module, determining whether the first module and the second module have been waiting for the bus, comparing the first unique arbitration number and die second unique arbitration number, scheduling transmission of data packets in response to the steps of determining and comparing, and repeating the steps of setting, signaling, establishing, asserting, determining, comparing, and scheduling.

Brief Description of the Drawings

The novel features believed characteristic of the invention are set forth in the appended claims. The invention itself, however, as well as other features and advantages there of, will be best understood by reference to the detailed description of specific embodiments which follows, when read in conjunction with the accompanied drawings, wherein:

FIG. 1 is a block diagram illustrating an exemplary local area network (LAN);

FIG. 2 is a block diagram illustrating an exemplary switch;

FIG. 3 is a high level flowchart illustrating the arbitration process in accordance with the principles of the invention;

FIG. 4 is a state diagram detailing the arbitration process in accordance with the principles of the invention; and

FIG. 5 is a timing diagram showing the between the data bus and the arbitration bus.

Detailed Description of the Preferred Embodimentf s

Referring to FIG. 1, an exemplary local area network (LAN) 10 is shown to include four nodes or modules labeled as 12, 14, 16, and 18, respectively. The exemplary LAN 10 is also shown as including two switches labeled as 20 and 22, respectively. Switch 20 includes three ports labeled as 24, 26, and 28, respectively, while switch 22 is shown having three ports labeled as 30, 32, and 34, respectively. Switch 20 is shown to be connected to a high speed bus 36 via poπ 28, while switch 22 is shown connected to the high speed bus 36 via port 34.

An exemplary transmission of data from node 12 (source) to node 18 (destination) proceeds in the following manner. A frame of data leaves node 12 and travels into switch 20 via the poπ 24. While in the switch 20, the frame is analyzed and checked for a source and destination address. If the source address and the destination address are valid, the data leaves the switch 20 and arbitrates for bus access. Once bus access is obtained, the frame of data is placed on the high speed bus 36 via poπ 28. The data on the high speed bus 36 arrives at switch 22 via poπ 34, and flows on to node 18 via poπ 32.

It will be appreciated that the exemplary LAN 10 may contain more than the number of nodes or modules and switches illustrated. In addition, in the exemplary transmission explained above, node 12 (or any of the other nodes) may be an Ethemet network adhering to the Ethemet protocol, while node 18 (or any of the other nodes) may be an Fiber Distributed Data Interface (FDDI) network adhering to the FDDI protocol. Furthermore, one or more of the nodes illustrated in FIG. 1 may be of the Asynchronous Transfer Mode (ATM) type, and thus adhere to the ATM protocol.

Referring now to FIG. 2, the switch 20 of FIG. 1 is shown to include a Data Moving Engine (DME) 50, a frame memory 52, and a lookup memory 54. Further, the DME 50 is shown to be connected to the ports 24, 26, and 28. In addition, each poπ is shown to have a corresponding buffer memory in the switch 20. Thus, poπ 24 is associated with buffer memory 56, poπ 26 is associated with buffer memory 58, and poπ 28 is associated with buffer memory 60. Furthermore, the switch 20 is shown to include a bus interface 62. The bus interface 60 provides an interface between the DME 50 and die bus 36 through buffer memory 60 and poπ 28. In a preferred embodiment, the DME 50 is a custom ASIC designed by Digital Equipment Corporation; it performs unica≤t transparent bridge forwarding (i.e., switching) at up to 1,000,000 pps, advanced bridge filtering, and core LAN functions at very high speeds. The DME 50 can suppoπ up to 48 bridged ports. The lookup memory 54 is used for data structures required by bridging and application code, while the flash memory 52 is used to store the configuration and operational code, and to run the code. When a frame of data arrives on a poπ, poπ 24 for example, the DME 50 checks the frame memory 52 and the lookup memory 54 to insure that the frame contains a valid source address and a valid destination address. Data leaving switch 20 flows from the DME 50 and on to die bus 36 via poπ 28.

Data arriving at switch 20 comes off the bus 36 and flows into the DME 50 via poπ 28. Again the DME 50 checks the received data for valid source and destination address in the frame memory 52 and the lookup memory 54, and then forwards the data to the appropriate node via the appropriate poπ, node 12 via poπ 24, for example.

The present invention resides in the bus interface of the switch, bus interface 62 in switch 20, for example. As stated above, the bus interface 62 is an interface between the DME 50 and the bus 36. In a preferred embodiment, the bus interface 62 is implemented in CMOS technology and typically runs at 50MHz. It contains an FDDI MAC Transmit Interface (TX) and an FDDI MAC receive interface (RX) with the DME 50. The TX interface runs at 50MHz and consists of the following signals: a byte wide TX data path, TX parity, TX control lines, TX ready, and TX aboπ.

As mentioned previously, the bus interface 62 contains a hub backplane arbiσation and bandwid± allocation logic device (Arb) 64. This Arb 64 includes the following (more fully descπbed below): distnbuted arbitration, pπoπry mechanism to suppoπ different classes of traffic, u que arbitration ID bits for each module, round robin arbitration within a given pnoπty level to produce fair access to the bus 36, arbirrauon timeout, and bandwiddi allocation between pπoπty levels. The Arb 64 typically runs at 10MHz. After the bus interface 62 receives a TX cell from the DME 50 and d e bus interface wins arbitration to die bus 36, a burst transmission process initiates with a transmission of a staπ cell delimiter onto the bus 36. The staπ bunt delimiter is defined as a 3 clock (50 MHZ) sequence of die following: all_ten_bits_zero, all_ten_bits_one, all_ten_bits_zero. For example, for 3 clock cycles the following pattern is sent out: 0-1-0 on all ten bus. Once a transmiπer staπs to send die 0-1-0 staπ delimiter it will continue to send die entire staπ delimiter. An aboπ will not occur during die staπ cell delimiter. Immediately following the staπ delimiter, 8 bits of data, and die parity and frame bits are transmitted. Except for the last 2 bytes, the frame bit will be high for the entire bunt. In order to reduce inter-packet gap, the frame bit is dropped 2 bytes pπor to d e end of the burst. A receive logic in the Arb 64 looks at the frame bit to generate a bus idle signal for the transmit logic. With the frame bit dropping early, bus idle is generated earlier and die inter-packet gap is minimized. In addition to d e frame bit, 1 bit provides parity (default is odd); this parity bit covers the 8 bits and die frame bit. If the transmit logic encounten an error, such as parity error, protocol error, or the DME 50 aboπed die burst, then an aboπ delimiter (all ten bits forced to l's) will be transmuted on to the bus 36. The bus interface 62 receives a byte of data from die bus 36 every 20ns (50MHz). The bus interface 62 receive logic in die Arb 64 samples all 10 bits from the bus 36 at an effective sampling rate of 300 MHZ. The receive logic searches for the staπ burst delimiter, 0-1-0. This pattern is searched for on each of 10 bits. For each bit, the receive logic searches for a staπ burst delimiter and for the middle of d e data, for each of 10 bits, i.e., die receiver attempts to find d e best sampling point for each bit. Once a staπ bunt delimiter has been detected for all 10 bits, the receive logic asseπs a valid data signal to a bus interface/DME RX interface (not shown) and die bu t is sent to the DME 50. If a staπ burst delimiter has been detected on any of the 10 bits and widiin the next 50MHz clock cycle, die remaining bits have not seen a staπ burst delimiter, a staπ burst error will be asseπed in an interrupt register. The bus interface 62 receives from the bus 36 8 bits of data, a frame bit, and a parity bit covering data and die frame bit. If an aboπ delimiter is received, the receive logic sees this as a parity error and the parity error bit at the RX end is asseπed high and die DME 50 will drop die burst.

As can be seen in FIG. 2, the bus 36 includes a serial two wire bus labeled as 66A and 66B, respectively. The serial two wire bus 66 A and 66B allows arbitration to occur independendy of a parallel data bus 68.

Referring to FIG. 3, a high level flowchaπ of an arbitration process according to the invention is shown to be a sequential process wherein the following definitions will aid in the understanding of d e process: ARB_STROBE Backplane WIRED-OR signal asseπed by paπicipating modules during d e arbitration sequence. The asseπion of ARBjBTROBE synchronizes the arbitration state machines in all modules. A module drives die backplane ARB-STROBE signal by asserting its internal TX_ARB_STROBE signal. A module monitors the state of die backplane ARB-STROBE signal by its internal RCV_ARB_STROBE signal.

.ARB DATA Backplane WIRED-OR signal used for die arbitration signaling process. ARB_DATA is activated by modules which are PARTICIPATING in a bus arbitration to signal dieir priority round robin bit and arbitration number. A module drives and monitors die backplane ARB.DATA signal by the internal TX_ARB_DATA and RCV_ARB_DATA signals.

RR_BΓΓ_PO,_PI Module internal signal used to insure fair access to the bus based on sequencing through arbiσation, IDs. Modules set their RR bit whenever the arbitration process completes with the winning module having a 4-bit arbitration ID number higher than theirs. When a module wins the arbitration process or if a module widi a lower number wins the arbitration process, then the module clears its RR bit. Thus if a module passes up its mm because it does not have a request to asseπ, it clears its RR bit and waits in line again.

Modules just entering the arbitration process should do so widi dieir RR bits cleared to insure they do not alter the sequence.

Modules have separate RR bits to each priority level. Thus different priority levels round robin independendy of each other.

PARTICIPATING A module is a bystander during an arbitration cycle if it does not have a bus request. If a paπicipating module loses an arbitration bit period or if its request is deasseπed the module becomes a bystander. Bystander modules do not asseπ ARB_STROBE. Bystanders must remain in sync with die arbitration process and monitor the arbitration in order to update their round robin bits coπecdy.

During an arbitration sequence a module may transition from PARTICIPATING to BYSTANDER but never vice versa. BUS_REQUEST Asseπed by a modules transmit data path to d e Arb logic to trigger the Arb logic to paπicipate in a bus arbitration. The PRIORITY line to the Arb logic must be valid whenever d e BUS_REQUEST line should stay asseπed until die Arb logic returns a BUS_GRANT if die BUS_REQUEST line is deasseπed by die σansmit data path prior to the assertion of BUS_GRANT the Arb logic will aboπ the arbitration by transitioning to the BYSTANDER state.

BUS_GRANT Asseπed by die Arb logic to the transmit data path upon winning die Arb process and entering the MASTER_ELECT state. Tne remains asseπed until BUS_REQUEST is deasseπed by the transmit data patii.

The following states can exist on the serial arbitration bus:

ARBJDLE Both ARB_STROBE and ARB_DATA deasseπed.

ARBITRATE ARB_STROBE asseπed, ARB_DATA may be asseπed or deasseπed. Arbitration runs to completion at which point the winner (MASTER_ELECT) releases ARB_DATA and continues to asseπ ARB_STROBE until becoming bus master. For a given application, diere will be an upper bound on how long die arbitration bus may remain in die ARBITRATE state before transitioning to the ARBJDLE state. This will depend upon die max length of the packets allowed by an application. The arbitration watchdog timer will time the arbitration process to detect a "hung" arbitration sequence.

Illegal ARB_STROBE deasseπed, ARB_DATA asseπed.

Referring now to FIG. 3, the sequence of events occurring during the arbitration process of die invention is as follows: at step 100 the bus 36 is in a WT_IDLE state or a

WT_REQ state until at least one module connected to the bus 36 signals a request. Tne

WT_IDLE state is entered under the following conditions: o reset o by die master elect module when it receives an acknowledgment to d e bus grant it passed to its data patii logic (bus requests deasseπs) o when a bystander module exits the ARB_ID_BπO state o when a paπicipating module losses arbitration and exits die ARB_ID_BIT0 state o when the arbitration winner is exiting the ARB_ID_B1T0 state and detects that die BUS_REQUEST from its data patii is no longer asseπed (the data path chose to aboπ the transaction).

At step 102, all modules wishing to request die bus 36 signal their priority level.

The highest signaled priority level is established in this step.

At step 104, a determination is made whed er modules wishing to use the bus 36 have been waiting their turn (RR bit set), or have taken their rum and have a new reques:

(RR bit cleared). Modules waiting in line have a higher priority.

At step 106, modules having a unique arbitration number (4 bits) compete for access to d e bus 36, with die higher arbitration number winning.

During each of die arbitration steps in FIG. 3, participating modules asseπ

TX_AR3_STR03E and signal the value of their arbitration number on the

TX_ARB_DATA line. After settling time, die value of die TX_ARB_DATA line is sampled. If the value matches what die ...adule signaled, the module continues to participate in d e next state. If the bus value does not match what the module signaled, die module loses the competition and ceases to participate (releases the

TX_ARB_STROBE, _DATA lines). The WIRED-OR bus 36 guarantees that the module widi die highest number will win the competition.

Referring to FIG. 4, a state diagram for die serial arbitration logic found in the Arb

64 is shown in detail. As mentioned previously, die WT_IDLE state 200 is entered under the following conditions: o reset o by the master elect module when it receives an acknowledgment to d e bus grant it passed to its data patii logic (bus requests deasseπs) o when a bystander module exits he ARB_ID_BITO state o when a participating module losses arbitration and exits die ARB_ID_BΓΪO state o when the arbitration winner is exiting die ARB_ID_BITO state and detects that die BUS_REQUEST from its data patii is no longer asseπed (d e data patii chose to aboπ d e transaction).

Once a module enters die WT_IDLE state 200, it will no longer remain there until the global arbitration bus has reached the ARB JDLE state 202. Once the arbitration bus has reached die WTJDLE state 200, any module needing to request die bus 36 can staπ the arbitration process by asserting ARB_STROBE. Modules which do not have an immediate request pending move to die WT_REQ state 204.

Modules enter die WT_REQ state 204 from the WTJDLE state 200 if they do not have a request pending when they detect die arbitration bus is idle. They will remain in this state until either they receive a bus request from the transmit data patii or some ther mc lϊ(s staπ an arbitration cycle.

The arbitration PRIORITY state 206 is used to signal high (ARB J) ATA = 1) or low (ARB JDATA = 0) priority. Those modules whose priority matches the value signed on the bus 36 continue to participate.

The serial arbitration ROUND JIOBIN state 208 is used to signal if any request is from a module waiting a turn (RR bit is set in modules Arb). If a module is paπicipating then it drives die ARB JDATA line widi its RR bit (each module has two RR bits, one for each priority). Those modules whose RR bit matches the value signaled on die bus 36 continue to paπicipate. During die serial arbitration ROUND J .OBIN states 210, the paπicipating modules signal dieir arbitration numbers. The module with die highest number will win. Following die ARB JDJJITO state 202 d e winning module will transition to the MASTER JΞLECT state 212 while all other modules transition to the WTJDLE state 200. If the winning module's BUS JIEQUEST line has deasseπed, this is an indication that the transmit data patii wishes to aboπ the packet - in this case the winning module transitions directly to the WTJDLE state 200 and does not asseπ a BUS J3RANT to the transmit data path.

It should be noted that the number of ARB JD J3ITx states may be altered to minimize die arbitration time based on d e number of modules using the bus 36. AH modules must be programmed for die same number of ARB JD JSITx states.

The winning module signals the MASTER JiLECT state 212 by releasing the ARB JD ATA line and keeping die ARE_STROBE line asseπed. All otiier modules will have released these lines. The MASTER JiLECT module signals a BUS J3RANT to its transmit data path and remains in this state until the data bust becomes idle, and its transmit data path logic starts transmission. The transmit data patii signals die Arb 64 by deasseπing the bus request at this time, allowing transition to the WTJDLE state 200. If the MASTER_ELECT module decides not to transmit the packet for which it requested die bus 36, it is required to release ARB vTROBE and transition to the WTJDLE state 200. Referring to FIG. 5, the timing relationship between the data bus 68 and die arbitration bus 66A/66B is illustrated. It should be noted that die arbitration states are net drawn to scale with respect to the data baud interval nor is die inter-packet gap shown to scale.

Having described a prefeπed embodiment of die invention, it will now become apparent, to one skilled in the an that other embodiments incorporating its concepts may be used. It is felt therefore, tiiat this embodiment should not be limited to d e disclosed embodiment, but ratiier should be limited only by the spirit and scope of d e appended claims.

Claims (5)

What is Claimed is:

1. A method of round robin bus arbitration comprising the steps of: providing a plurality of modules; providing a bus having a plurality of data lines, the bus connecting the plurality of modules, the bus having an arbitration unit; setting the bus to a wait state; signaling a fint bus request to the bus by a fint module needing to transmit a first plurality of data packets on to the bus, die fint module having a fi t module priority level and a first unique arbitration number, signaling a second bus request to the bus ^v. a second module needing to transmit a second plurality of data packets on to die bus, the second module having a second module priority level and a second unique arbitration number, establishing a bus priority according to a comparison of the first module priority level and the second module priority level; asserting the first unique arbitration number on the bus by the fint module; asserting the second unique arbitration number on the bus by the second module; determining whedier the first module and die second module have been waiting for the bus; comparing the fint unique arbitration number and die second unique arbitration number, scheduling transmission of data packets in response to the steps of determining and comparing; and repeating d e steps of setting, signaling, establishing, asseπing, determining, comparing, and scheduling.

2. The mediod of round robin bus arbitration according to Claim 1 wherein d e bus includes two data lines.

3. The method of round robin bus arbitration according to Claim 1 wherein die step of setting the bus to the wait state occurs in response to one of the following conditions: a reset signal on the bus; a deasserting signal by the one of the modules; a "exit from arbitration" signal by one of the modules; a "lose of arbitration" signal by one of the modules; and a "win of arbitration" signal by one of die modules.

4. The method of round robin bus arbitration according to Claim 1 wherein d e step of determining whether the fint module and die second module have been waiting for the bus includes the steps of: assigning a higher priority to the modules which has been waiting the longest; and scheduling the module widi the highest priority.

5. The method of round robin bus arbitration according to Claim 2 wherein the two data lines of die bus include: an ARB_STROBE line, die ARB J TROBE line carrying a WIRED-OR signal asseπed by the plurality of modules during an arbitration sequence; and an ARB_DATA line, die ARB_DATA line carrying a signal used for an arbitratiojn signaling process.