AU7130700A - Reconfigurable pinout ball grid array - Google Patents

Reconfigurable pinout ball grid array

Info

Publication number
AU7130700A
AU7130700A AU71307/00A AU7130700A AU7130700A AU 7130700 A AU7130700 A AU 7130700A AU 71307/00 A AU71307/00 A AU 71307/00A AU 7130700 A AU7130700 A AU 7130700A AU 7130700 A AU7130700 A AU 7130700A
Authority
AU
Australia
Prior art keywords
pinout
reconfigurable
grid array
ball grid
ball
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
AU71307/00A
Inventor
Henry Chung
Jeffrey Alan Miks
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Motorola Solutions Inc
Original Assignee
Motorola Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Motorola Inc filed Critical Motorola Inc
Publication of AU7130700A publication Critical patent/AU7130700A/en
Abandoned legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5382—Adaptable interconnections, e.g. for engineering changes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
AU71307/00A 1999-10-14 2000-09-12 Reconfigurable pinout ball grid array Abandoned AU7130700A (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US41805199A 1999-10-14 1999-10-14
US09418051 1999-10-14
PCT/US2000/025000 WO2001027996A1 (en) 1999-10-14 2000-09-12 Reconfigurable pinout ball grid array

Publications (1)

Publication Number Publication Date
AU7130700A true AU7130700A (en) 2001-04-23

Family

ID=23656481

Family Applications (1)

Application Number Title Priority Date Filing Date
AU71307/00A Abandoned AU7130700A (en) 1999-10-14 2000-09-12 Reconfigurable pinout ball grid array

Country Status (2)

Country Link
AU (1) AU7130700A (en)
WO (1) WO2001027996A1 (en)

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5184284A (en) * 1991-09-03 1993-02-02 International Business Machines Corporation Method and apparatus for implementing engineering changes for integrated circuit module
US5923539A (en) * 1992-01-16 1999-07-13 Hitachi, Ltd. Multilayer circuit substrate with circuit repairing function, and electronic circuit device
WO1993017455A2 (en) * 1992-02-20 1993-09-02 Vlsi Technology, Inc. Integrated-circuit package configuration for packaging an integrated-circuit die and method of packaging an integrated-circuit die
US5354955A (en) * 1992-12-02 1994-10-11 International Business Machines Corporation Direct jump engineering change system
US5753970A (en) * 1993-06-18 1998-05-19 Lsi Logic Corporation System having semiconductor die mounted in die-receiving area having different shape than die

Also Published As

Publication number Publication date
WO2001027996A1 (en) 2001-04-19

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Legal Events

Date Code Title Description
MK6 Application lapsed section 142(2)(f)/reg. 8.3(3) - pct applic. not entering national phase