AU705490B2 - Apparatus and process for producing time dependent waveforms of a power systems currents - Google Patents

Description

The present invention relates to a process and apparatus for producing time dependent waveforms of positive symmetrical sequence components (I1) and negative symmetrical sequence components (I2) of a power system's currents. The invention has particular use in protective relaying.

Protective relaying generally involves the performance of one or more of the following functions in connection with a protected power or energy system: monitoring system to ascertain whether it is in a normal or abnormal state; metering, which involves measuring certain electrical 10 quantities; protection, which typically involves tripping a circuit breaker in response to the detection of a short-circuit condition; and alarming, which provides a warning of some impending problem. In connection with these and other ancillary functions, such as fault detection, detection of S0** power flow direction, over-current detection, etc., the protective relaying 15 system must compare phasor quantities (voltages and currents). Generally, the faster such a comparison can be made, the better.

Prior to the present invention, protective relays compared phasor quantities using frequency domain techniques such as the Fourier transform. A primary goal of the present invention is to provide methods and apparatus for comparing phasor quantities in real time.

According to one aspect of the invention there is provided a process for producing time dependent waveforms of positive symmetrical sequence components (I1) and negative symmetrical sequence components (I2) of a power system's currents, comprising the steps of: sampling said power system's currents; and employing digital logic circuitry to generate digital symmetrical components (I1, 12) values in real time; wherein said digital logic circuitry comprises an arrangement of delay elements, amplifier elements and summing elements operatively interconnected to produce said digital symmetrical components in real time; and wherein said digital logic circuitry produces symmetrical components proportional to I1 k and I2k, wherein 11 is a positive sequence current, 12 is a negative sequence current, and the subscript k is an index referring to digital samples of the respective components.

Preferably the digital logic circuitry produces Clarke components:- Ia 311+ 32= 2a Ib Ic If= 31-32 -3(Ib Ic) j 10 wherein said power system comprises a first phase (phase-a), a second phase (phase-b), and a third phase (phase-b), and Ia is a phase-a current, Ib is a phase-b current, and Ic is a phase-c current.

In a preferred form of the invention the digital logic circuitry receives samples of Ia, Ib and Ic; generates Iak, IClk-1., Ik and Ifk,1; and then 15 combines ak, Iak-1, Ik and IP 3 k, so as to produce values of 11k, 11k-1, 1k-2, I2k, 1 2 k- 1 and I 2 k-2.

The power system may comprise a first phase (phase-a), a second phase (phase-b), and a third phase (phase-b), and said digital logic circuitry receives samples of Ia, Ib and Ic; generates sample values Iak, Iak.1, Ibk Ibk1 Ick and Ick1; and then combines lak, Iak-1, Ibk Ibk 1 Ick and Ick-1 SO as to produce values of 1 k and I 2 k; wherein Ia is a phase-a current, Ib is a phase-b current, and Ic is a phase-c current.

According to another aspect of the invention there is provided an apparatus for producing time dependent waveforms of positive symmetrical sequence components and negative symmetrical sequence components of a power system's voltages or currents, comprising: means for sampling said power system's currents; and digital logic circuitry for generating positive symmetrical sequence components (I1) and negative symmetrical sequence components (12) of a power system's currents, comprising an arrangement of delay elements, amplifier elements and summing elements operatively interconnected to produce said digital symmetrical components in real time; wherein said digital logic circuitry produces symmetrical components proportional to Ilk and I2k, wherein 11 is a positive sequence current, 12 is a negative sequence current, and the subscript k is an index referring to 10 digital samples of the respective components.

In order that the invention may be more readily understood and put into practical effect, reference will now be made to the accompanying drawings in which:- Fig. 1 schematically depicts the power system inputs for 15 protective relaying applications and/or numerical comparator applications.

~Fig. 2A schematically depicts a cylinder unit with inputs S1 and S2.

5 Figure 2B depicts the expected torque vs. phase angle (between S1 and S2) characteristics of a cylinder unit.

Figure 3A is a block diagram of a numerical comparator in accordance with the present invention. This embodiment of the invention computes Mk, in real time, wherein Mk l is analogous to the torque of a cylinder unit.

Figure 3B depicts the phasor characteristics of the numerical comparator depicted in Figure 3A. Figure 3B depicts the phasor characteristics of the cylinder unit depicted in Figure 2A, which are analogous to the phasor characteristics of the numerical comparator and its output

M.

Figure 4A depicts a circuit that simulates 15 equations that define the inputs to a numerical comparatorbased phase-to-phase distance unit in accordance with the present invention.

Figure 4B is a block diagram of one embodiment of a phase-to-phase distance unit using the delay operator "d" 20 Figure 4C depicts a circuit that simulates equations that define the inputs to a numerical comparator based phase-to-ground distance unit in accordance with the present invention.

CFigure 4D is a block diagram of one embodiment of a phase-to-ground unit in accordance with the present invention.

CFigure 5A depicts the required characteristic of a directional unit on the R-X plane. The directional units described in this specification exhibit this characteristic.

Figure 5B illustrates the idealized cylinder unit and the relationship between M (torque) and e (angle).

Figures 5C to 5F depict the processing performed by the numerical comparator directional units in accordance with the present invention.

Figure 6A depicts an analog symmetrical filter components.

6 Figures 6B and 6C schematically depict illustrative embodiments of symmetrical components filters in accordance with the present invention. Figure 6B depicts a Clarke component-based symmetrical components filter. Figure 6C depicts a direct phase shift symmetrical components filter.

Figure 7 schematically depicts one embodiment of an over-current unit (which can use voltage inputs as well as current inputs) and its implementation along with a trip comparator in accordance with the present invention. (Note that many units derived with the numerical comparator will use the trip comparator, which is a decision making processor.) Figure 8A depicts the mechanical system analog for the trip comparator.

15 Figure 8B schematically depicts one embodiment of a numerical trip comparator in accordance with the present invention.

"Figure 9 schematically depicts the functionality of the trip comparator.

20 Figure 10 is an exemplary graph of the output of the trip comparator.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS A. BRIEF OVERVIEW Protective relaying is a science concerned with 25 protecting electrical equipment drawing voltages and %wo*currents from a power system. The protective relaying system requires certain inputs from a transmission line which includes three phase conductors A, B, C. Figure 1 illustrates the traditional way of obtaining the required inputs. As shown, voltage inputs VA, VB, VC are obtained by voltage transformers 12 and current inputs IA, IB, IC are obtained by current transformers 14. The quantities available for the protective relaying apparatus 16 are the phase voltages VA, VB, VC; the zero sequence voltage 3V0 VA+VB+VC; the phase currents IA, IB, IC; and the zero sequence current 310 IA+IB+IC.

7 B. REAL-TIME PHASE COMPARATOR MODELED AFTER CYLINDER

UNIT

A comparator is a device used in protective relays to compare two phasor quantities in phase and/or magnitude.

The cylinder unit 18, schematically depicted in Figure 2A, is a well-known type of comparator used in electromechanical relays. Two outstanding characteristics of the cylinder unit are its insensitivity to DC offset and speed of operation.

When two voltages S1 and S2 are applied to the cylinder unit 18, flux densities B1 and B2 are produced.

These flux densities are vectors distributed on the surface of the rotating cylinder. If B1 and B2 are time-dependent, currents are induced in the cylinder, and these currents are 15 proportional to the rate of change of B1 and B2, represented as dBl/dt and dB2/dt, and the angle theta which is the phase difference between S1 and S2. These cylinder currents are directed toward the positive Z axis perpendicular to the plane of Figure Using the vector force equation 20 (below), the force vector field around the surface of the cylinder can be found: F x B)1 The torque on the Z axis is the quantity of interest. This torque can be calculated by summing the torque components.

=E x F The torque expressed in terms of flux densities BI, B2 is: a r 3 1 2 T B l t dB2(t) B2(t) dB 1 z 1 2r dt dt or M= K B( t) dB2(t) B2(t) dBl(t) z dt dt where, a electric conductivity (mhos/m) 7T 3.1415 r cylinder radius 1 cylinder length 8 T cylinder thickness.

If two time varying voltages Sl(t) and S2(t) are applied to the cylinder unit 18, a time varying flux density B(t) will be produced. The flux density B(t) will have components Bl(t) and B2(t) related to Sl(t) and S2(t) as: S1 d N A dB1 dt dt S2(t) d N1 A dB2 dt dt C-At B2(t+At)= S2(t)dt+B2(t) SB2 tA t) f S

A

10 where N1 and N2 are the number of turns of the S1 and S2 input windings.

It should be mentioned that these equations do not contain any loss mechanism. The following relationships do contain losses and can be used to relate the S (inputs) and B terms.

S(t) =LB dB1+RB BI t....dt S2 t) LB dB2 RB B2 dt where LB and RB are constants that can be determined to make the model more efficient.

If Sl(t) and S2(t) are sine waves, such as Sl(t) Sin (wt) S2(t) Sin (wt 6), the torque in P.U. (per unit) terms will be: M 0 when M -1 when 6=900 M 0 when 6=1800 M 1 when 6=2700 as depicted in Figure 2B.

9 To apply the above equations to protective relays based on microprocessors and/or microcontrollers, they can be discretized using the trapezoidal rule: Bl A t S A t RB 2 LB S At RB +2 LB k kand

B

2 k 2At 1 S2 S 2 4- (At RB 2 LB B2 1 [At RB +2 LB k k 1 At Blk FK2 [Slk Slk_- FK1 Blk-1

B

2 k FK2 [S2k S 2 k-1 FK1 B 2 k1] where: FK AtRB-2LB 10 At FK2= A A tRB+2LB and the torque can be expressed as: Mk B 2 k Blk- Blk B 2 k-1 where: 15 k+1 actual sample k previous sample At sampling period.

Figure 3A is a block diagram of a numerical comparator circuit or system 20 for computing Mk. In the 20 system of Figure 3A, denotes a delay unit; denotes a summing unit; denotes a multiplier; and "FK1", "FK2" are amplifiers. The output Mk of the system 20 represents the real time torque Mk of a comparator having the phasor characteristics depicted in Figure 3B, which illustrates the operating characteristics of the numerical comparator Having S1 as the reference, a phase difference of 0 to negative 1800 indicates operation of the unit. A phase difference of 0 to positive 1800 indicates no-operation or restraint of the unit.

This procedure can be employed in distance relays, pilot wire relays, directional relays, over-current relays, over/under voltage relays, etc., where a real-time 10 comparison of two phasor quantities is desired. In specific applications of this invention, mechanical influences to the model, such as a restraining spring force, friction force, and/or bias force, can be included as necessary.

C. DISTANCE UNIT FOR FAULT DETECTION A procedure for obtaining distance units employing a numerical comparator is described next.

Protective relaying concerns the detection of faults in power apparatus. In transmission line relaying, distance relays are used to detect several types of faults in the transmission line. These devices detect faults in transmission lines up to certain reaches or distances. In general, these devices measure the impedance, which is proportional to the distance from the relay location to the sea* 15 fault (hence the name "distance unit"). The digital/numerical distance units derived by this procedure detect faults faster than prior art fault detectors, but otherwise behave like known electromechanical distance units. The numerical methods disclosed herein are less 20 vulnerable to transients and noise than any other time domain method. This is due to the analogy to the cylinder unit, which has shown to operate well under transients.

1. PHASE-TO-PHASE

UNIT

To detect phase-to-phase faults, the inputs to the 25 numerical comparator are: S1 =VA-VB- (IA-IB) S2=VC-VB-(IC-IB) The circuit depicted in Figure 4A simulates these equations. Therefore, Sl(t) and S2(t) may be derived from the phase-to-phase voltages and currents as follows: sl(t)=va(t) -vb(t) -ib(t) )(Rc+Lc- d s2( )=vc t)-vb(t)-(ic(W)-ib(L))Rc+Lc d dt If we make the equations discrete and apply them to the cylinder unit model derived above, we obtain: 11 Slk=Vak-Vbk- RC+ la RCr Ib Lc

C

S

2 kVCk-Vbk k k-1 bk- bk- 1 which are the inputs to the numerical comparator (also called the "torque generator") derived above. S1 k and S 2 k are then used to obtain Blk,, B2k and Mk as described above.

The above equations are discrete realizations of a phase-to-phase distance unit that will detect all types of faults involving two phases and some phase-to-phase-toground faults.

Figure 4B is a block diagram of one implementation of the above equations for a phase-to-phase distance unit.

Notice that the delta currents lab and Icb are sampled, delayed and combined with the sampled and delayed delta S voltages Vab and Vcb. The combination for each are the S 15 inputs to a numerical comparator 20a, which is like the numerical comparator 20 described above. The output of the numerical comparator is coupled to a clipping unit denoted which forms part of a trip comparator 30 (described below). The equations for Bl and B2 are implemented and the 20 cross multiplication of B1k times B2k+1 and Blk1i times B2k is employed to obtain the Mk term. The amplifiers are labelled "A00", "BOO", "FK1", and "FK2" in accordance with their gains, as set forth in the following list: A00 Rc Lc/At BOO Lc/At CC At 2 /l EE 1/(1 At 2 KC/1 At KD/1) FF 2 At KD/1 FK1 (2 LB At RB)/At FK2 At/(At RB 2 LB).

(Note that CC, EE and FF are related to the trip comparator).

2. PHASE-TO-GROUND UNIT 12 The inputs to a well known means for detecting phase-to-ground faults are: S1 VA-(IA-KOIO)Zc S2=VC-VB where I0= IA+IB+IC 3 Zc=Rc+jXc=Rc+j2n.fLc KO=Kr+jKi= ZOc-Zc Zc The circuit schematically depicted in Figure 4C 10 simulates the above equations. If these equations are made discrete and are applied to the numerical comparator equations, we obtain: S1 k Vak R lak+ .ak KrRc- KiXc KrAC K KC i0 k KrXc KiRc l 2 irfA t

S

2 k= Vck- Vbk 15 which are the inputs to the numerical comparator derived above.

Figure 4D is a block diagram of one embodiment of a phase-to-ground unit in accordance with the present invention. The currents and voltages shown are sampled and combined in the adders as shown, and then input to the numerical comparator 20b. The B1 and B2 terms are then cross multiplied and Mk is obtained and fed to the trip comparator 30 (described below). The amplifiers are labelled "A01", "B01", "C01", "E01", and "FF" in accordance with their gains, as set forth in the following list: A01 Rc Lc/At B01 Lc/At C01 (Kr Rc Kl Xc)/3 (Kr Xc K1 RC)/3w At E01 (Kr Xc Kl RC)/3w At CC 1/(1 At 2 KC/1 At KD/1) 13 EE At2/ FF 2 At KD/l.

In sum, a general procedure for obtaining impedance units (distance units) has been described. The units obtained are high speed since they require only three sampling periods k, k+l) to obtain a trip criterion, regardless of the sampling frequency. Finally, many other distance units can be obtained by the procedure disclosed herein. The above-described distance units, the phase-tophase distance unit and the ground distance unit (also referred as the quadrature polarized ground distance unit), are just two examples of the different principles used in protective relaying to obtain distance units. The procedure described above can produce any type of distance unit now 15 used in industry requiring the comparison of two phasor quantities D. DIRECTIONAL UNIT Directional units are devices required in *':protective relaying to indicate the direction of power flow.

Ground directional units derived from the numerical comparator disclosed above are fast, making them ideal for protective relaying applications and in combination with distance units derived from the numerical comparator.

Figure 5A illustrates the characteristics of such directional units on the R-X plane. In this example, the forward direction indicates that power is flowing into the transmission line. The reverse direction indicates that power is flowing from the transmission line.

Directional units come in two categories, phase directional units and ground directional units. Phase directional units operate under all conditions. Ground directional units operate only when there is an unbalance in the power system. The following directional units have been developed: 14 1. NEGATIVE SEQUENCE POLARIZED DIRECTIONAL

UNIT

Using the output of a numerical symmetrical components filter, the following equations are used to implement a negative sequence polarized directional unit: Blk FK2 V2 k 2 V 2 k- V 2 k 2 FK1 Bik1)

B

2 k FK2 2 2 1 2 k-1 1 2 k-2 FK1 B 2 k-) Mk B 2 k Blk- Blk B 2 k-1 In the above equations, V2 and 12 are outputs of the numerical symmetrical components filter, an example which is described below.

2. ZERO SEQUENCE POLARIZED DIRECTIONAL

UNIT

The following equations can be used to implement a zero sequence polarized ground directional unit: Blk FK2 3VOk 2 3VOk- 3 VOk2 FK1 Blk1) B2k FK2 AA 3 1 0 k AB 310k-1 BB 3 1 0 k2 FK1 B2k-1 Mk B2k Bl, Blk B2k-1 *where: AA= 1 4 4x fAt BB= V 1 4 4 7r fAt 20 AB AA BB In the above equations, 3V0 VA+VB+VC and 310

IA+IB+IC.

3. CURRENT POLARIZED GROUND DIRECTIONAL

UNIT

If Ipol(t) is an input from a grounding point in the power system, a ground directional unit can be implemented with the following equations: 310 3IOk_ 2 Blk FK2 k 0 k-2 FK1 Blk At k B2k FK 2 (IpolK 2 IpolK-1 IpOIK 2 FK1 B2K-1) Mk BI-B 2 k B 2 k-Blk 15 4. PHASE DIRECTIONAL

UNIT

A phase directional unit can be implemented with the following equations: Blk FK2(-VCBK 2VCBK-1

VCBK

2 FKlBK-1) B2 2 FK2 (AA IAK ABIAK- BBIAK-2 FK1 B 2

K

1 Mk BlkB 2 k B 2 k-Blk where:

AA=

S4 47fAt BB= 1 I 4 47xfA t

*AB=AA+BB

and VCB is the delta voltage (VC VB).

1 0 Other directional units can be implemented with the numerical comparator disclosed above. The above equations determine the "torque" of the unit, which can be combined with a numerical trip comparator.

Figures 5C to 5F depict the processing performed 15 for the directional units.

Figure 5C illustrates the data flow for the negative sequence polarized ground directional unit, which comprises a numerical comparator 20c and a trip comparator The V2 and 12 inputs to the numerical comparator are derived from a symmetrical components filter. The implementation of the equations of the negative sequence polarized ground directional units combines the samples of V2 and 12 to produce the Bl and B2 terms that are cross multiplied to obtain the Mk term, which is fed to the trip comparator 30. The amplifiers labelled

"FF",

"FK1", and "FK2" have the following gains: CC 1/(1 At 2 KC/1 At KD/1) EE At 2 /1 16 FF 2 At KD/1 FK1 (2 LB At RB)/At FK2 At/(At RB 2 LB).

Figure 5D illustrates the data flow of the zero sequence polarized ground directional unit. The 3VO and 310 terms are derived from the actual power system samples VA+VB+VC and 310 IA+IB+IC). The implementation of the equations of the zero sequence polarized ground directional unit combines the samples of 3V0 and 310 to produce the B1 and B2 terms that are input to the numerical comparator and cross multiplied to obtain the Mk term fed to the trip comparator 30. The amplifiers labelled "AA55",

"BB

55 and "AB55" have the following gains: AA55 sqrt(3)/4 1/(411 f At) 15 BB55 sqrt(3)/4 1/(41 f At) g*e AB55 AA55 Figure 5E illustrates the data flow of the current polarized ground directional unit comprising a numerical comparator 20e and a trip comparator 30. The 310 term input to the numerical comparator is derived from the actual power system samples (310 IA+IB+IC) and the Ipol samples are the actual samples of a current obtained from a suitable grounding point of the power system. The implementation of the equations of the current polarized ground directional unit combines the samples of 310 and Ipol to produce the B1 and B2 terms that are cross multiplied to obtain the Mk term fed to the trip comparator.

Figure 5F illustrates the data flow of the phase directional unit (phase A) comprising a numerical comparator 20f and a trip comparator 30. The VCB term input to the numerical comparator is VC VB, where VC and VB are the actual samples from the C and B phases. IA is the phase A current. This implementation of the equations of the phase directional unit combines the samples of VCB and IA to produce B1 and B2 terms that are cross multiplied to obtain the Mk term fed to the trip comparator. The amplifiers labelled "AA52", "BB52" and "AB52" have the following gains: 17 AA52 1/4 sqrt(3)/(4n f At) BB52 1/4 sqrt(3)/(4n f At) AB52 AA52 BB52.

The above-described procedures are exemplary procedures for directional units. Those skilled in this art will recognize that other directional units can be obtained with the invention disclosed herein.

E. SYMMETRICAL COMPONENTS

FILTER

Symmetrical component quantities are required for fast and reliable relaying of different parts of the power system. The procedures described below provide the symmetrical components in a time-dependent manner. These procedures are required employed in fast directional units and/or distance units. Three procedures will now be 15 described.

1. SIMULATION OF EXISTING ANALOG FILTER Figure 6A depicts an analog filter. The positive and negative sequence components in discrete form are given by the following equations: V1- Vak Vbk 2 Vck) At 1 (2Vck t R1 C 3 R1 Cl 2 Vbk) VClk- 1 where:

VC

k (2 Vck-1 2Vbk) VCk k- R1 C1 3 and 1 V1k (ak Vbk) VC2k where: VC2k 1 )(2Vc 2 Vb) VC2) 1+ At R2 C2 3 k-1 R2 C2 Constants C1, R1, C2 and R2 can be fine-tuned to obtain the corresponding optimized equations. There will be a set of 18 R1, C1, R2 and C2 constants that produce the smallest error and the correct phase shift.

2. DIRECT PHASE SHIFT The symmetrical component equations are: 11 (1A a IB a 2

IC)

3 12 (1A a 2 I1B a TC) 3 These equations can be implemented by using the phase shifting identities, a 1 4rrf dt e.0.

Therefore, in discrete form: o 3 1 1 k =a b -I V3(b -lk1 k 1 4- f t. Tck 4 7 tf3t(Ick Tk1 3. 2k IaK 2--b ITb) 1 -ick V (Ick ICk- 1 j 3. CLARKE COMPONENTS

DERIVATION

By definition, the Clarke components are: ITa 3 311 3 12 2 la lTb Ic -P 311 -312 =V3 1 c It follows that: 311 1 (Ia jIp) 2 19 312 (a jIp) 2 Using the operator: 1 d 27f dt it follows that: 1 (a 1 dIP 311 (Ia dIp) 2 2xf dt 312 1 (la dI 2 27if dt Making the equations discrete: 3 1 1 k (I ak Pk -Pk 2 27f At 1 1 k IPk-1 312 (IJ, 2 27f At This implementation is the simplest. However, a further step to "align" the time with respect to the derivatives can

S°

o be performed to reduce errors and increase the accuracy of the method: 3 Iak I c k 1 I Ikl- 4 4 f At 32 k i k (k k-1) 3 I2k k k- 15 4 4Tcf At Figures 6B and 6C schematically depict illustrative embodiments of symmetrical components filters in accordance with procedures 3 (Clarke components) and 2 (Direct phase shift), respectively.

Figure 6B illustrates the combination of IA, IB and IC samples to obtain the Ia and 13 components and later manipulate them, according to the above equations, to obtain the Ii and 12 (positive and negative) components of the currents. The same process could be performed for voltages to obtain the positive and negative sequence components of the voltages. The amplifiers labelled and have the following gains: 20 A 1/4 B 1/(4n f At).

Figure 6C illustrates the combination of IA, IB and IC samples, using the direct phase shift equivalent (the A and B constants), to obtain the II and 12 components of the currents. The same procedure could be followed to obtain the positive and negative sequence components of voltages.

In this embodiment, amplifiers and have the following gains: A -1/2 B sqrt(3)/(4n f At).

OVER-CURRENT

UNIT

The over-current unit disclosed below employs a numerical algorithm that is fast and unaffected by DC 15 offsets. It can be used as a level detector for voltage or current.

To implement a single input over-current unit, one "of the numerical comparator inputs should be phase-shifted.

Using this criterion, the following equations can be employed to provide an over-current unit free of the effects of DC offset. This unit is extremely fast.

Blk FK2 (IAk IAk-1 FK1 Blk-1)

B

2 k FK2 (IAk 2 IAk-1 IAk-2 FK B2k-1) Bk-B 2 k B 2 k Blk This output "torque" (Mk) can be fed into the numerical trip comparator and the opposing torque constant, MC, can be adjusted for the trip level. In the above equations,

IA

could be a current, voltage, or any other power system quantity (such as a symmetrical component) Figure 7 schematically depicts one embodiment of an over-current unit 20g and its implementation in accordance with the present invention. The inputs to the numerical comparator, in this embodiment, are derived as shown from the single quantity IA. The samples are combined to obtain the B1 and B2 quantities, as expressed in the above equations. The output, Mk, can be used to feed the numerical 21 trip comparator 30 described below. Amplifiers "FKl" and "FK2" have the following gains: FK1 (2 LB At RB)/At FK2 At/(At RB 2 LB) RB LB 0.001.

G. TRIP COMPARATOR The procedure described next can be used in the implementation of a numerical trip comparator relay unit.

The numerical trip comparator is a complement of all the embodiments described above. The trip comparator makes the trip decision. In other words, it decides when to indicate the operation of the unit to which it is connected.

A numerical model of the travel of an electro- 15 mechanical cylinder unit contact should resemble the electro-mechanical operation of the cylinder unit. The numerical comparator depicted in Figure 3A was employed to develop the numerical trip comparator disclosed herein.

In Figure 8A: 6 the angle of travel, T the trip angle, M the electro-mechanical torque, MS the opposing spring (force) torque, MC the constant opposing torque, 25 I the moment of inertia of the cylinder.

The electro-mechanical equation for the model is: I d 2 (M MC) KD d KS.

dt 2 dt If the equation is discretized, 6k can be expressed as: k- Ok-lFF 0 k-2 CC(M MC) EE k- k-2 where: EE 1+ t KD At 2

KC

I+ I I At KD FF t D 2

I

22 CC =At In the numerical trip comparator, the following conditions are applied: 1. If (Mk MC) 0, then the next 0 8 is zero.

2. If 6 k 8 T' then the next 8 k is set to 0 and a trip is issued.

Figure 8B schematically depicts one embodiment of a numerical trip comparator 30 in accordance with the present invention. The trip comparator receives as input the torque Mk (generated in any of the above-described units) and, as shown in the Figure 8B, it is limited to -MM M k +MM and then the opposing bias torque MC is subtracted from Mk. The rest of the circuitry implements the above equations. The output 0 is later compared to 8 for a trip, as mentioned in condition 2. The gains of amplifiers and "FF" are disclosed above.

Referring now to Figures 9 and 10, which illustrate the operation of the trip comparator, this unit issues a logic (false) if the unit has not operated and issues a 20 logic (true) if the unit has operated. The variable "0" is the input to the block and is compared to upper and lower limits. It should be mentioned that Figure 10 illustrates typical limits; however, other limits can be used.

If the instantaneous value of 0 is greater than 0.6 (in this example a logic (true) is issued to the protective relaying logic in the microprocessor-based apparatus. If it is less than 0.6, a logic (false) is issued to the protective relaying logic in the microprocessor-based apparatus. The limits of the variable are from 0 to 1 in this example.

Those skilled in the art will appreciate that the present invention can be embodied in apparatus and processes not exactly like those described hereinabove. The numerical trip comparator is used in protective relaying to implement numerically the function(s) of a phase comparator. The cylinder unit in electromechanical relays is the building 23 block of many different units used in protective relaying, including distance units, directional units, over/undercurrent units, over/undervoltage units, pilot wire and other specialized applications. The numerical comparator is another phase comparator unit that can be used to develop relaying units like the ones discussed above.

The development of the numerical comparator algorithms described above resulted from the analysis of the behavior or the cylinder unit, but the equations have been modified. They are not an exact model of the cylinder unit.

Indeed, the flexibility of the equations, factors, multiplier, ranges, etc., which are the equations to be implemented in microprocessor based apparatus, allow the :designer to accommodate the behavior of the unit with more flexibility than an actual cylinder unit.

*oo S S THE CLAIMS DEFINING THE INVENTION ARE AS FOLLOWS:- 1. A process for producing time dependent waveforms of positive symmetrical sequence components (11) and negative symmetrical sequence components (12) of a power system's currents, comprising the steps of: sampling said power system's currents; and employing digital logic circuitry to generate digital symmetrical components (11, 12) values in real time; wherein said digital logic circuitry comprises an arrangement of delay elements, amplifier elements and summing elements operatively interconnected to produce said digital symmetrical components in real time; and wherein said digital logic circuitry produces symmetrical components proportional to Ilk and 1 2 k, wherein 11 is a positive sequence current, I2 is a negative sequence current, the subscript k is an index referring to digital samples of the respective components, and wherein said digital logic circuitry produces Clarke components: Ia 311+312= 2a-Ib-Ic 311- 312 (bIc) wherein said power system comprises a first phase (phase-a), a second phase (phase-b), and a third phase (phase-c), and la is a phase-a current, Ib is a phase-b current, and Ic is a phase-c current.

2. A process as claimed in claim 1, wherein said digital logic circuitry receives samples of la, Ib and Ic; generates ITk, Ick-1, Ik and I 13 k1; and then combines ICk, Iak-k, Ik and Ip 1 3 k so as to produce values of Ilk, k-1, I1 k-2, I 2 k, 1 2 k-1, and I 2 k-2.

23/3/99

Claims (3)

1. 3. A process as claimed in claim 2, wherein said power system comprises a first phase (phase-a), a second phase (phase-b), and a third phase (phase-c), and said digital logic circuitry receives samples of Ia, Ib and Ic; generates sample values lak, lak-1, Ibk Ibk- IC k and Ick1; and then combines lak, lakl, Ibk Ibk- ICk and ICk- so as to produce values of I1 k and I 2 k; wherein la is a phase-a current, Ib is a phase-b current, and Ic is a phase-c current.
2. 4. An apparatus for producing time dependent waveforms of positive symmetrical sequence components and negative symmetrical sequence components of a power system's voltages or currents, comprising: means for sampling said power system's currents; and digital logic circuitry for generating positive symmetrical sequence components (I1) and negative symmetrical sequence components (12) of a power system's currents, comprising an arrangement of delay elements, amplifier elements and summing elements operatively interconnected to produce said digital symmetrical components in real time; wherein said digital logic circuitry produces symmetrical components proportional to Il k and I2k, wherein I1 is a positive sequence current, 12 is a negative sequence current, the subscript k is an index referring to digital samples of the respective components; and wherein said power system comprises a first phase (phase-a), a second phase (phase-b), and a third phase (phase-c), and said digital logic circuitry produces Clarke components: Ia= 311+ 312= 2a Ib Ic
3. 311- 312 If/3= l- (Ib Ic) J 23/3/99 wherein la is a phase-a current, lb is a phase-b current, and Ic is a phase-c current. An apparatus as claimed in claim 4, wherein said digital logic circuitry comprises a first input terminal for receiving samples of la, a second input terminal for receiving samples of Ib, a third input terminal for receiving samples of Ic; means for generating I k, lak-1, Ik and Ipk-1; and means for combining lak, I(ak-, I'k and Ipk-1 so as to produce values of Ilk, I1 k-1, 1 k-2, I 2 k, I 2 k-1, and I 2 k-2. 6. An apparatus as claimed in claim 4, wherein said power system comprises a first phase (phase-a), a second phase (phase-b), and a third phase (phase-c), and said digital logic circuitry comprises a first input terminal for receiving samples of Ia, a second input terminal for receiving samples of Ib, a third input terminal for receiving samples of Ic; means for generating sample values lak, lak1l, Ibk, Ibk-, Ick and ICk-; and means for combining lak, Iak-1, Ibk, Ibk-, ICk and ICk-1 so as to produce values of Ilk and I 2 k wherein la is a phase-a current, Ib is a phase-b current, and Ic is a I I phase-c current. Dated this 23rd day of March 1999 I i I ABB POWER T D COMPANY INC Patent Attorneys for the Applicant PETER MAXWELL ASSOCIATES 23/3/99 ABSTRACT A process for producing time dependent waveforms of positive symmetrical sequence components (I11) and negative symmetrical sequence components (12) of a power system's currents includes sampling the power system's currents and employing digital logic circuitry to generate digital symmetrical components (11, 12) values in real time. The digital logic circuitry includes an arrangement of delay elements, amplifier elements and summing elements operatively interconnected to produce the digital symmetrical components in real time proportional to 11k and I 2 k, the subscript k being an index referring to digital samples of the respective o* components. e 00 0000 *0 o 4 *oe