AU7033687A - Apparatus and method for providing a settling time cycle for a system bus in a data processing system - Google Patents

Apparatus and method for providing a settling time cycle for a system bus in a data processing system

Info

Publication number
AU7033687A
AU7033687A AU70336/87A AU7033687A AU7033687A AU 7033687 A AU7033687 A AU 7033687A AU 70336/87 A AU70336/87 A AU 70336/87A AU 7033687 A AU7033687 A AU 7033687A AU 7033687 A AU7033687 A AU 7033687A
Authority
AU
Australia
Prior art keywords
providing
data processing
time cycle
settling time
processing system
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
AU70336/87A
Inventor
John F. Henry Jr.
James B. Keller
Robert E. Stewart
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Digital Equipment Corp
Original Assignee
Digital Equipment Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Digital Equipment Corp filed Critical Digital Equipment Corp
Publication of AU7033687A publication Critical patent/AU7033687A/en
Abandoned legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4063—Device-to-bus coupling
    • G06F13/4068—Electrical coupling
    • G06F13/4072—Drivers or receivers
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
    • G06F13/362—Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control
    • G06F13/364—Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control using independent requests or grants, e.g. using separated request and grant lines

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Bus Control (AREA)
  • Small-Scale Networks (AREA)
AU70336/87A 1986-01-29 1987-01-29 Apparatus and method for providing a settling time cycle for a system bus in a data processing system Abandoned AU7033687A (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US82377486A 1986-01-29 1986-01-29
US823774 1986-01-29

Publications (1)

Publication Number Publication Date
AU7033687A true AU7033687A (en) 1987-08-25

Family

ID=25239674

Family Applications (1)

Application Number Title Priority Date Filing Date
AU70336/87A Abandoned AU7033687A (en) 1986-01-29 1987-01-29 Apparatus and method for providing a settling time cycle for a system bus in a data processing system

Country Status (7)

Country Link
EP (1) EP0290472A1 (en)
JP (1) JPH01501426A (en)
AU (1) AU7033687A (en)
CA (1) CA1278100C (en)
ES (1) ES2002950A6 (en)
IL (1) IL81423A (en)
WO (1) WO1987004827A1 (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2657740A1 (en) * 1990-01-26 1991-08-02 Sgs Thomson Microelectronics METHOD AND CIRCUIT FOR CONTROLLING AN INTEGRATED CIRCUIT OUTPUT BUS.
US6188249B1 (en) * 1998-06-30 2001-02-13 Sun Microsystems, Inc. Asymmetric arbiter with fast signal path
US7203779B2 (en) * 2002-01-30 2007-04-10 Stmicroelectronics, Inc. Fast turn-off slow turn-on arbitrator for reducing tri-state driver power dissipation on a shared bus

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4186379A (en) * 1977-04-28 1980-01-29 Hewlett-Packard Company High-speed data transfer apparatus
US4249093A (en) * 1978-09-06 1981-02-03 Lockheed Electronics Co., Inc. Multiple request arbitration circuit

Also Published As

Publication number Publication date
WO1987004827A1 (en) 1987-08-13
JPH01501426A (en) 1989-05-18
IL81423A0 (en) 1987-08-31
CA1278100C (en) 1990-12-18
EP0290472A1 (en) 1988-11-17
IL81423A (en) 1991-06-10
ES2002950A6 (en) 1988-10-01

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