AU678452B2 - Arrangement for preventing flickering of visual indicator means - Google Patents

Description

P/00/011 28/5/91 Regulation 3.2

AUSTRALIA

Patents Act 1990 Dc o

D

ORIGINAL

COMPLETE SPECIFICATION STANDARD PATENT Invention Title: "ARRANGEMENT FOR PREVENTING FLICKERING OF VISUAL INDICATOR MEANS" The following statement is a full description of this invention, including the best method of performing it known to us:- .oo o o *o i This invention relates to telephone subsets, particularly telephone subsets capable of accessing exchange based facilities such as, for example, call waiting and call diversion facilities.

Such telephone subsets further include visual indicator means, typically light emitting diodes (LEDs) for visually indicating various conditions and modes of operation such as, for example, incoming ring, call forward, etc.

The LEDs obviously require power for their energisation. However, the power available in the subset is normally provided over the exchange line and is therefore limited, so subsets batteries are required.

Some such telephones incorporate a standard serial link such as RS232 for coupling a personal computer to the subset. The serial link is powered by a ao DC power supply derived from the mains power.

The serial link incorporates a shift register which is utilised to energise the subset's LEDs.

SeA disadvantage of this arrangement is that the use of the shift register to directly control the state of the LEDs causes the LEDs to flicker as data applied to the shift register moves across the shift register momentarily turning on and turning off the LEDs.

"2t: It is an object of the present invention to provide an anti-flicker arrangement for a LED control circuit comprising a shift register.

According to the invention there is provided an arrangement for preventing flickering of visual indicator means respectively coupled to a plurality of outputs of a shift register when a predetermined signal condition is applied to 2 a data input of said shift register at a predetermined time relative to the period of clock pulses applied to a shift clock input of said shift register to selectively illuminate at least one visual indicator means, wherein said arrangement includes a switchable oscillator means whose oscillator signal output is coupled to said shift register's latch clock input and whose switch control input is coupled to said shift clock input of said shift register such that the oscillator signal ceases when a pulse train is being applied to the said shift clock input, whereby the latch clock updates the shift register's latch only during periods when the shift register is not receiving data on said data input.

In order that the invention may be readily carried into effect, an embodiment thereof will now be described in relation to the accompanying drawings, in which: Figure 1 is a schematic representation of part of a telephone subset incorporating the invention.

Figure 2 is a circuit of a known oscillator used in the present invention.

Referring to the drawings, there is shown a microprocessor 1 associated with a telephone subset circuit (not shown). An output 2 of microprocessor 1 is coupled to an I/O port 3 of a memory board 4. Two signal lines D and CL are respectively coupled, via an opto-isolator means 5, to a Data input and a Clock input of a shift register 6 incorporated in a standard serial link board 7. Outputs S~Q1, 0.2 and Q3 of shift register 6 are respectively coupled to LEDs, D1, D2 and D3 located on the subset (not shown).

Serial link board 7 is connected to a mains derived power supply (not shown).

Serial link board 7 further includes an oscillator 8 having an oscillator control coupled to the shift register's clock, and an oscillator output coupled to the shift register's latch clock. Details of the known oscillator are shown in m ee~ Figure 2. It comprises a known NAND Schmitt trigger and an RC network.

20. In use, when updating of the LEDs is required, the microprocessor will cause 8 pulses to be applied to the CL line. In order to illuminate, for eg. diode D2, the microprocessor will cause a HIGH logic condition to be applied to the D line at a point in time that is immediately prior to the last two clock pulses. As a result the data is shifted from the data input to Q2 output thus providing a condition thereon to illuminate D2. This condition was, however, fleetingly applied to 01 causing D1 to flicker.

In order to prevent this flicker, the latch clock is caused w update the latch only during periods when the shift register is not receiving new data. This is accomplished by stopping the oscillation of the latch clock whenever a pulse train is being applied to the shift clock.

Claims (9)

1. An arrangement for preventing flickering of visual indicator means respectively coupled to a plurality of outputs of a shift register when an enabling signal condition is applied to a data input of said shift register to selectively illuminate at least one visual indicator means, wherein said arrangement includes a switchable oscillator means whose oscillator signal output is coupled to said shift register's latch clock input and whose switch control input is coupled to said shift register's shift clock input such that the oscillator signal ceases when a train of pulses is being applied to the said shift clock input, whereby the latch clock updates the shift register's latch only during periods when the shift register is not receiving data on said data input,

2. An arrangement as claimed in claim 1, wherein said visual indicator -°S means are at least two light emitting diodes.

3. An arrangement as claimed in claim 1 or 2, wherein said oscillator means comprises a NAND Schmitt trigger.

An arrangement as claimed in any one of the preceding claims, wherein 'said shift register is incorporated in a telephone subset having a processor means.

5. An arrangement as claimed in claim 4, wherein said shift register is :i 20 included in a serial link means.

6. An arrangement as claimed in claim 4 or 5, wherein said enabling condition and said clock pulses are provided at outputs of said processor means.

7. An arrangement as claimed in claim 6, wherein said enabling signal condition and said clock pulses are respectively coupled to said data input and said shift clock input of said shift register via opto-isolator means.

8. An arrangement as claimed in claim 7, wherein an I/O port means is operatively interposed between said outputs of said processor means and input means of said opto-isolator means.

9. An arrangement substantially as herein described with reference to Figure 1 of the accompanying drawings. DATED THIS FOURTH DAY OF OCTOBER 1996 ALCATEL AUSTRALIA LIMITED 4 a ABSTRACT An arrangement for preventing flickering of light emitting diodes energised by a shift register associated with a telephone subset. According to the invention the shift register's latch clock is caused to update the shift register's latch only during periods when the shift register is not receiving new data. This is accomplished by applying the output of a switchable oscillator to the latch clock input of the shift register's latch. The oscillator is controlled by using the clock signal applied to the shift register's shift clock input. Thus the oscillator is prevented from oscillating when a pulse train is being applied to the shift clock input. S FIGURE 1. 0.: 9 o0 S