AU6712496A - Point-to-multipoint arbitration - Google Patents

Point-to-multipoint arbitration

Info

Publication number
AU6712496A
AU6712496A AU67124/96A AU6712496A AU6712496A AU 6712496 A AU6712496 A AU 6712496A AU 67124/96 A AU67124/96 A AU 67124/96A AU 6712496 A AU6712496 A AU 6712496A AU 6712496 A AU6712496 A AU 6712496A
Authority
AU
Australia
Prior art keywords
point
arbitration
multipoint
multipoint arbitration
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
AU67124/96A
Other languages
English (en)
Inventor
Stephen A. Caldara
Matthias L. Colsman
Stephen A. Hauser
Thomas A. Manning
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Fujitsu Network Communications Inc
Original Assignee
Ascom Nexion Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ascom Nexion Inc filed Critical Ascom Nexion Inc
Publication of AU6712496A publication Critical patent/AU6712496A/en
Abandoned legal-status Critical Current

Links

Classifications

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    • H04L2012/5678—Traffic aspects, e.g. arbitration, load balancing, smoothing, buffer management
    • H04L2012/5681—Buffer or queue management
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/54—Store-and-forward switching systems 
    • H04L12/56—Packet switching systems
    • H04L12/5601—Transfer mode dependent, e.g. ATM
    • H04L2012/5678—Traffic aspects, e.g. arbitration, load balancing, smoothing, buffer management
    • H04L2012/5681—Buffer or queue management
    • H04L2012/5682—Threshold; Watermark
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/54—Store-and-forward switching systems 
    • H04L12/56—Packet switching systems
    • H04L12/5601—Transfer mode dependent, e.g. ATM
    • H04L2012/5678—Traffic aspects, e.g. arbitration, load balancing, smoothing, buffer management
    • H04L2012/5681—Buffer or queue management
    • H04L2012/5683—Buffer or queue management for avoiding head of line blocking
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/54—Store-and-forward switching systems 
    • H04L12/56—Packet switching systems
    • H04L12/5601—Transfer mode dependent, e.g. ATM
    • H04L2012/5685—Addressing issues
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/04—Speed or phase control by synchronisation signals
    • H04L7/041—Speed or phase control by synchronisation signals using special codes as synchronising signal
    • H04L7/046—Speed or phase control by synchronisation signals using special codes as synchronising signal using a dotting sequence

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Security & Cryptography (AREA)
  • Software Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)
AU67124/96A 1995-07-19 1996-07-18 Point-to-multipoint arbitration Abandoned AU6712496A (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US149895P 1995-07-19 1995-07-19
US001498 1995-07-19
PCT/US1996/011921 WO1997004562A1 (en) 1995-07-19 1996-07-18 Point-to-multipoint arbitration

Publications (1)

Publication Number Publication Date
AU6712496A true AU6712496A (en) 1997-02-18

Family

ID=38659672

Family Applications (1)

Application Number Title Priority Date Filing Date
AU67124/96A Abandoned AU6712496A (en) 1995-07-19 1996-07-18 Point-to-multipoint arbitration

Country Status (3)

Country Link
JP (1) JPH11510003A (ja)
AU (1) AU6712496A (ja)
WO (1) WO1997004562A1 (ja)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20080079027A (ko) * 2007-02-26 2008-08-29 삼성전자주식회사 네트워크 프로세서 패킷 처리 장치 및 그 방법

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CA2015248C (en) * 1989-06-30 1996-12-17 Gerald R. Ash Fully shared communications network
US5535197A (en) * 1991-09-26 1996-07-09 Ipc Information Systems, Inc. Shared buffer switching module
GB2273224B (en) * 1992-12-05 1997-01-22 Netcomm Ltd An ATM Cell switch suitable for multicast switching
US5530695A (en) * 1993-12-15 1996-06-25 Nec Usa, Inc. UPC-based traffic control framework for ATM networks
US5392280A (en) * 1994-04-07 1995-02-21 Mitsubishi Electric Research Laboratories, Inc. Data transmission system and scheduling protocol for connection-oriented packet or cell switching networks
US5528588A (en) * 1994-09-14 1996-06-18 Fore Systems, Inc. Multicast shared memory
US5521916A (en) * 1994-12-02 1996-05-28 At&T Corp. Implementation of selective pushout for space priorities in a shared memory asynchronous transfer mode switch

Also Published As

Publication number Publication date
JPH11510003A (ja) 1999-08-31
WO1997004562A1 (en) 1997-02-06

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