AU666184B2 - A presentation graphics system for a colour laser copier - Google Patents

Description

666184

AUSTRALIA

PATENTS ACT 1990 COMPLETE SPECIFICATION FOR A STANDARD PATENT

ORIGINAL

S F Ref: 238781 o e e sc r Name and Address of Applicant: Actual Inventor(s): Address for Service: Invention Title: ASSOCIATED PROVISIONAL [311 Application No(s) PL2143 Canon Information Systems Research Australia Pty Ltd 1 Thomas Holt Drive North Ryde New South Wales 2113

AUSTRALIA

Kia Silverbrook Spruson Ferguson, Patent Attorneys Level 33 St Martins Tower, 31 Market Street Sydney, New South Wales, 2000, Australia A Presentation Graphics System for a Colour Laser Copier

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APPLICATION DETAILS [33] Country

AU

[32] Application Date 29 April 1992 The following statement is a full description of this invention, including the best method of performing it known to me/us:- 5815/3 A Presentation Graphics System for a Colour Laser Copier The present invention relates to colour laser copying, and in particular, discloses a presentation graphics system which can be connected to an existing colour laser copier that is provided with a video interface.

Colour composition systems for creating full colour desk top publishing capable of creating and printing A3 size full colour images at 400 dots per inch (dpi) traditionally use a personal computer system with the aid of various input devices such as a mouse and a keyboard. The image is normally composed and stored in a frame buffer memory device on a pixel by pixel basis before the image is written out to the relevant display device, such as a colour printer on a line by line basis.

For an image the size of an A3 page, at 400 dpi, 4,632 x 6,480 pixels must be stored.

If 24-bits of colour are stored per pixel, this gives a total storage requirement of over Mbytes. Such a storage size requirement is often a significant expense in the design of a full colour composition system in addition to a resulting increase in the size of any system 1 incorporating the composition system, thereby hindering the acceptance of full colour systems in normal consumer markets.

It is an object of the present invention to provide a simplified image composition system for use with a printing device that substantially eliminate need for storage of an image on a pixel by pixel basis.

In accordance with one aspect of the present invention there is disclosed a graphics system for a colour copier, said system comprising an input object image data, host processor means connected to a user controllable input means for selecting and editing said object image data to create edited image data, real-time processor means for rendering said edited image data to output an image signal and communication means for interconnecting said system with said copier for printing an image represented by said image signal.

25 A number of embodiments of the present invention will now be described with reference to the accompanying drawings in which: Fig. 1 is a schematic block diagram of a first embodiment; Fig. 2 is a schematic block diagram of a preferred embodiment and Fig. 3 is an illustration of the preferred embodiment.

The present invention is specific application of technology disclosed in: Australian Patent Application No. 3 8244/93 (Attorney Ref: (RT07)(23 8909)) claiming priority from Australian Patent Application No. PL 2147 of 29 April 1992, entitled "A Real-Time Object Based Graphics System"; (RT03)(238781AU)(CFP107AU) (ii) Australian Patent Application No. 38240/93 (Attorney Ref: (RTO8)(238740)) claiming priority from Australian Patent Application No. PL 2148 of 29 April 1992 entitled "Method and Apparatus for Filling an Object Based Rasterised Image"; (iii) Australian Patent Application No. 38242/93 (Attorney Ref: (RTO13) (238899)) claiming priority from Australian Patent Application No. PL 2153 of 29 April 1992 entitled "Method and Apparatus for Providing Transparency in an Object Based Rasterised Image"; (iv) Australian Patent Application No. 38233/93 (Attorney Ref: (RTO5/16) (238799)) claiming priority from Australian Patent Application No. PL 2156 of 29 April 1992 entitled "Edge Calculation for Graphics Systems" and Australian Patent Application No. PL 2145 of 29 April 1992 entitled "Object Sorting for Graphics Systems"; Australian Patent Application No. 38250/93 (Attorney Ref: (RTO2)(238860)) claiming priority from Australian Patent Application No. PL 2142 of 29 April 1992 entitled "A Preprocess ,ng Pipeline for RTO Graphics System"; (vi) Australian Patent Application No. 38246/93 (Attorney Ref: (RTO10) (238766)) claiming priority from Australian Patent Application No. PL 2150 of 29 April 1992 entitled "Object Based Graphics Using Quadratic Polynomial Fragments"; and S (vii) Australian Patent Application No. 38239/93 (Attorney Re;: (RTO9)(238753)) claiming priority from Australian Patent Application No. PL 2149 of 29 April 1992 entitled "Bezier Spline to Quadratic Polynomial Fragment Conversion"; 20 all lodged herewith by the present applicant, the disclosure of each of which is hereby incorporated by cross-reference. Those specifications disclose arrangements by which real-time object based images can be created, generally using quadratic polynomial fragment (QPF) representations of objects.

Referring now to Fig. 1, there is shown first embodiment of the present invention in 25 the form of a presentation system 1 which includes a host processor 2 connected to a processor bus 3 via an address latch 14. Also connected to the processor bus 3 are a system ROM 4, a system RAM 5, a serial controller 6, a memory card interface socket 7, an RTO processor 12, and a dual port RAM 8.

The host processor 2 is a general purpose microprocessor which is arranged to control the generation of object based images. In the preferred embodiment, the host processor 2 is a 32 bit microprocessor such as the INTEL i960SA, which permits high speed operation at low cost and has a wide addressing range. The host processor 2 operates to create and maintain multiple object lists which are stored in the system RAM 5 and which include multiple objects which are ultimately processed the RTO processor 12 to form an image. The calculations for image generation are generally only performed at the (RTO3)(238781AU)(CFP107AU) °y; graphic object level. For each image that is to be created, the host processor 2 specifies the position, size, and colour of each object that is to appear in the final image. The host processor 2 also interacts with the serial controller 6 to a keyboard 20 which allows the user to inteiface with the presentation system 1 for command and control, including the selection of graphic objects to form an image for printing. The serial controller 6 interprets keyboard commands from the keyboard 20 and forwards the keyboard commands to the host processor 2 via the processor bus 3.

The host processor 2 has a 16-bit external data bus which is multiplexed with a 32 bit address bus, in addition there are 16 control signals provided by the host processor 2. The most significant 16 address bits (bits 31-16) are not multiplexed, However address bits 4 are demultiplexed by the address latch 14. The host processor 2 has secondary control of the processor bus 3 whilst the RTO processor 12 can obtain access to the bus via DMA whenever it requires such access, except whenever specifically locked out via software S controlling the host processor 2. The address latch 14 are of a tri-stated nature and are only 15 used when the host processor 2 has control of the bus. The address bits 3,2,1 are demultiplexed directly by the host processor 2 to avoid any latch delays during burst S" accesses. During bursts, the upper address bits and the latched address bits remain static while address bits 3-1 count up. Thus host processor bursts are limited to 16 bytes. These bursts can occur in several combinations of byte and half-word accesses. All address decoding is based on the upper 4 address lines (aligned to 256 Mbyte boundaries), so one host processor burst cannot span multiple devices.

The multiplexed data bus of the host processor 2 is used to directly control the RTO processor 12, system RAM 5, system ROM 4, serial controller 6 and the memory card interface socket 7.

25 Arbitration of the processor bus 3 takes place between the host processor 2 and RTO processor 12. The host processor 2 masters the bus until the RTO processor 12 is commanded (by the host processor 2) to begin operation. The RTO prccessor 12 then takes control of the processor bus 3 and will notify the host processor 2 when it is finished. The host processor 2 has no mechanism to stop RTO processor 12 from obtaining the processor bus 3 except by halting the RTO processor 12 from operation. The RTO processor 12 will attempt co completely prepare an object list for printing or display once started and may use the processor bus 3 continuously once it gets it (if the RTO pr -essor 12 is rendering at the same time it may bottleneck internally and release the processor bus 3 until it is able use it again). Multiple object lists can be used to make up an image, and hence the system (RTO3)(180424:LDP) -4software could use this approach to prevent the RTO processor 12 from holding too long a mastership of the processor bus 3.

The host processor 2 communicates with the various other devices of the presentation system 1 by means of memory mapped I/O. The upper 4-bits of the processor bus 3 are decoded by programmable array logfic units (PALs) (not shown) to provide all necessary enable and select signals, read and write strobes, buffer controls and the ready signal for the host processor 2. These logic units are active when the host processor 2 masters the bus and when RTO processor 12 masters the bus.

The system ROM 4 preferably contains 512 kilobytes ofROM which is generally provided by a single 256K x 16 device. The system ROM 4 contains the controlling program for the presentation system 1 as well as various examples of images, fonts, clip titles, and other data used in the presentation system 1. Both the host processor 2 and RTO processor 12 can access the memory in the system ROM 4 and single and burst accesses are supported. Preferably, the system ROM 4 is wired so that larger ROMs can be used when 15 they become readily available.

The system RAM 5 preferably contains 256K bytes of RAM which consists of two 128K x 8 devices. The system RAM 5 is used by the host processor 2 for the caching of graphics objects including QPF lists, the caching of performance critical code, and as a variable storage. Single and burst accesses are supported, as are byte writes. Preferably, the system RAM 5 is also wired so that larger RAMs can be used when they become readily available.

The memory card interface socket 7 provided for the insei tion of standardized memory cards. Typically, these sockets are adapted to take cards conforming to both the JEIDA and PCMIA standards. JEIDA (Japanese Electronics Industry Development 25 Association) and PCMCIA (PC Memory Card International Organization) have released substantially identical standards for the use of 68 pin interchangeable memory cards. Each memory card 15 may be typically be used as ROM devices incorporating object graphic data, but can also be either flash EPROM or static Ram with battery backup. Each memory card 15 is used to store libraries of graphics objects, object edit lists, clip titles, fonts, characters, animation sequences and/or special programs which can be used to replace or supplement all or part of the programs within system ROM 4. Where static RAM cards are used, then these can also be used for storage of a user's images for later use.

Preferably the memory card interface socket 7 is capable of accommodating cards with increased storage capabilities as they become available.

(RTO3)(180424:LDP) The memory card bus 9 to the memory cards is preferably buffered by a bidirectional buffer 10 from all other devices accessing the processor bus 3. This is to ensure that the memory cards 15 do not interfere with the logic levels of the processor bus 3 at any stage.

Since a memory card 15 can be inserted or removed by the user at any time, some bus problems may be unavoidable. Short pins in the memory card interface socket 7 can be used to provide interrupts a short time before the card is removed. If the RTO processor 12 is mastering the processor bus 3 when a card is removed, the recovery time for the host processor 2 software will be reduced by the maximum bus tenure of the RTO processor 12.

The memory card interface socket 7 is provided with short card detect pins which generate insertion and removal interrupts for the indication of the presence or otherwise of a memory card 15. The signals are sent to the serial controller 6 where they can be used for detection of removal, insertion of crooked memory cards. Detected memory card signal can then be relayed to the host processor 2 through a general interrupt. This allows notification S. of a software event to update the current state of the host processor 2 to take account of the 15 removal.

In order to determine the nature of the memory card 15 inserted, an optional attribute memory may be read from the memory card 15. This attribute memory is only 8 bits wide and is read on the low data bus and is accessed at the predetermined memory address of the memory card. This allows the presentation system 1 to be used in conjunction with memory cards of different attributes and speeds. Preferably system software is provided to interrogate the memory cards and decide based on their speed and optional attribute memory, how the RTO processor 12 and the host processor 2 will best be able to safely access the memory cards.

Where SRAM type memory card devices with battery backups are supported, the 25 memory card sockets 7 is provided with battery condition signals that are connect to the serial controller 6 and indicate whether the battery is good or bad.

The serial controller 6 is preferably implemented by a Exar 82C684 Quart device which includes four, full duplex, asynchronous serial channels, two timers and sixteen general purpose input and output ports. The connection of the serial controller 6 to processor bus 3 is only 8 bits wide so all accesses only exist on the lower (even) byte of the processor bus 3. A first serial communications link 21 of the serial controller 6 is used to communicate with an output device such as a Canon CLC 500 colour laser copier 24 to control the copying device and receive status information. A second serial communications link 22 is used as an RS232 interface which provides a means to interrogate and control the host processor 2 when performing servicing or updating system control software. A third (RTO3)(180424:LDP) 0* 0 serial communications link 23 is used to communicate with a keyboard 20 for the interactive entry of user requests, commands, selections and information. Additionally the serial controller 6 is also used for timer events, serial communication, special keyboard keys, and memory card insertion and removals which can be communicated to the host processor 2 through an interrupt.

The RTO processor 12 is setup and controlled by the host processor 2 for the realtime rendering of object based graphic image and a full description of a specific example of the RTO processor 12 can be found in Australian Patent Application 38244/93, claiming priority from Australian Patent Application No. PL2147 (Attorney Ref: (RT07)(23 8909)) of 29 April 1992 by the same applicant, the disclosure of which has been previously incorporated by cross-reference.

The RTO processor 12, apart from interfacing with the processor bus 3, also interfaces with its own dedicated QPF memory 16, which is implemented as 512k bytes of local QPF memory (four 128K x 8 rams). These rams are always enabled, and RTO 15 processor 12 drives the read and write strobes directly.

Once setup and started, the RTO processor 12 reads lists of objects from system ROM 4, system RAM 5, or the memory cards into its own local memory, prepares the objects, and then renders the objects, outputing an 8 bit data word an RTO processor level output bus 17, for each pixel of the output device, which describes the level and effects desired for the highest visible object active at the pixel. Preferably, the display lists include object outline data which permit the calculation of graphic images in real time. An example of such data is quadratic polynomial fragments which are normally cached in the system RAM 5, but may be read directly from the system ROM 4 or from memory card After reading the display list in the form of QPF's, the RTO processor 12 scales and translates the QPF objects in each of the X and Y directions. This allows the implementation of squash and stretch effects, as well as the compensation for different pixel aspect ratios found on different output devices.

Next, QPF's which have been translated or scaled entirely off the screen are removed from the object list by culling. QPF's which are too small to be visible, are also culled.

QPF's which cross the boundaries of the output device are also clipped. After initial processing, the QPF's are stored in the dedicated QPF memory 16. Once all the QPF's are stored in the dedicated QPF memory 16, they are sorted into line order and then pixel order in terms of the position of each of the first pixel in each QPF. Subsequently, the intersections of all QPF's with scan lines that they cross are calculated. This is performed in 35 real-time without the use of a frame store. QPF's are not flattened into straight lines before -~a ~ST ;iq~, i: "i?

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,c (RT03)(23878 IAU)(CFP 107AU) -7intersection calculation, and accordingly curvature is preserved in the curves even at high magnification. After intersection calculation, the visible ordering of objects is determined and hidden surfaces are removed. Regions of colour are then filled by extending the priority levels for each QPF until the next intersection. Transparency and effect calculations are then performed in hardware and at real-time data rates. In this manner, the RTO processor 12 outputs pixel data for display on raster displays or printing on a copier device in a synchronous n manner and comprises colour level data tran 'ferred via the level output bus 17.

When the RTO processor 12 is a slave to the host processor 2, the host processor 2 is able to read the control registers of the RTO processor 12 in addition to reading the dedicated QPF memory 16. Access to control registers of the RTO processor 12 is performed by memory mapped I/O techniques. The base address for accessing the dedicated QPF memory 16 is programmed into the RTO processor 12 registers at start-up .i and is also set according to the host processor m nmory map table. The RTO processor 12 15 does not support burst access or byte writes tu its registers or dedicated QPF memory 16.

When the RTO processor 12 is in control of the processor bus 3, the RTO processor 12 drives the demultiplexed address and data buses directly. As mentioned previously it requests use of the processor bus 3 by notification and subsequent grant from the host processor 2.

S* 20 The RTO processor 12 has an interrupt output signal which is connected to the host processor 2 and forms the highest priority interrupt (INTO) of that device. This interrupt can be used to indicate many events including completion of operations and internal error events.

The 8-bit contents of the RTO processor output level bus 17 is used to form the 25 address of a dual port RAM 8 which is used as a colour palette between the RTO processor S. 12 and a colour copier 24 such as a Canon CLC 500. Preferably, the dual port RAM 8 is divided into a number of separate palette areas, with a separate palette area being chosen after a predetermined number of lines have been printed by the copier 24. The copier 24 operates by means of a four pass process. TIe four colour passes include Cyan, Magenta, Yellow and Black (CMYK). Hence swapping of palette areas can be timed to occur at the completion of each colour pass of the copier 24. One port of the dual port RAM 8 outputs the colour selected by the RTO processor 12 to a copier interface buffer The copier interface buffer 25 outputs the current pixel colour in addition to pixel clocking information, copier enablement signals and line enable signals obtained from a timing bus 26 output from the RTO processor 12, by way ofRS422 output drivers, to the (RT03)(180424:LDP) -8copier 24 according to its specific timing requirements. Where the copier 24 is a CLC 500, the buffers 25 output to an IPU port of that copier. The other port of the dual port RAM 8 is co.inected to the processor bus 3. This port is readable and writable and permits burst accesses by the host processor 2 which can be used by the host processor 2 to alter the colour palette area by software control. Hence the colour palettes can by changed at any time by the host processor 2 including between the time that the copiel 24 is engaged in a colour pass or even when the copier 24 is engaged in a current colour pass.

The RTO processor output level bus 17 is also fed to a video processing unit 27 which contains a video synchronisation unit, preferably implemented by a 74ACT715 Video Synchronization Generator which is a programmable video synchronization generator, capable of producing a wide range of different sync waveforms and timings. The host processor 2, acting under software control, is designed to program the video synchronisation unit at start-up by the processor bus 3, so as to output the correct synchronisation timings and interlace factors as required by the particular video device, 15 such as video TTFT LCD display 28. The interlace factor is also forward to the RTO pi-ocessor 12.

The video processing unit 27 also contains a RamDac device which is preferably implemented by a Bipolar 'echnologies, BT478 RamDac device, which is software programmable to contain a palette of 256 colours. The RamDac can be software S" 20 programmed by the host processor 2 at start-up or during operation. In addition to the colour palette, the RamDac has a single overlay pattern available which can be preprogrammed by the host processor 2 so that when the RTO processor 12 is being used to print an image on the copier 24, the video TFT LCD display 28 can be colour blanked. The RamDac of the video processing unit 27 reads in the current value of the RTO processor o 25 output level bus 17 and uses this to determine which of 256 output colours to output to the video TFT LCD display 28. Output is in an RGB analog output format in addition to vertical and horizontal synchronization information and backlight brightness control information.

Referring now to Fig. 2 and Fig. 3, there is shown the preferred embodiment of the present invention. This embodiment is similar in structure to the first embodiment and corresponding components are numbered identically. Additional features include a second memory card unit 29 adapted to simultaneously receive a second memory card 30, a touch panel 31, a dial control 32, a RGB band store 37 and a SCSI controller 33. Additionally a colour processing unit 13 has replaced the dual port RAM 8 of Fig. 1.

(RTO3)(1 80424:LDP) The second memory card unit 29 is used to substantially increase the range of graphics materials such as libraries of graphics objects, object edit lists, clip titles, fonts, animated characters etc. that can be accessed by the host processor 2 thereby substantially increasing the overall utility of the presentation system 1.

The transparent touch panel 31 is provided over either one of the memory card units or over the video TFT LCD display 28, to increase the ease with which a user can select a desired object in the creation of an image or carry out a particular command. The touch panel 31 includes an interface unit (not shown) for deriving an X-Y position of a depression of thb- touch screen and sending this value to the host processor 2.

A dial control 32 is also provided and allows for the rapid selection of a desired object on the video TFT LCD display 28 amongst a multitude of different objects, thereby also increasing the efficiency of selection of objects formed in the creation of any image.

The colour processing unit 13 is provided in replace of the dual port RAM 8 of Fig. 1.

•The colour processing unit 13 consists of a colour generation and mixing (CGM) device for each single colour component of the output colour space of said colour processing unit 13.

S.'0 A full description of the operation of the CGM device and its configuration the colour o processing unit 13 is given in Australian Patent Application No. 3 8245/93 claiming priority from Australian Patent Application No. PL2152 (Attorney Ref: (RTO 12)(23 8738)) filed by the present applicant simultaneously herewith and entitled "A Colour Generation and 20 Mixing Device", the disclosure of which is incorporated herewith by cross-reference.

The colour processing unit 13 can produce RGB colour information 34 from colour q. information received from RTO processor 12. The RGB colour information 34 can be used for display on the video TFT LCD display 28. The colour processing unit 13 can also be used to determine the CYMK output for the copier 24 by the host processor 2 loading tie 25 correct colour control information at the start of each pass of the colour copier and then reloading RGB colour control information for the video TFT LCD display 28 at the end of the printing process.

Additionally, there is provided the optional capability for interfacing with other forms of output devices 35 such as a inkje: copier 36 (the Canon CLC 10 for example) which is capable of printing an image in a number of predetermined bands. This can accomplished by storing RGB colour information in a RGB band store 37 before forwarding it to a SCSI controller 33 which is used for forwarding the RGB colour information to the SCSI interface, of the ink jet copier 36.

The foregoing describes only two embodiments of the present invention particular to specific output devices. Use of other types of output devices and other modifications, (RT03)(23878 IAU)(CFP 107AU) v N obvious to those skilled in the art, can be made thereto without parting from the scope of the invention ft e a* a e a* 94 sees r f e o e (RTO3)(180424:LDP)

Claims (11)

1. 2. A graphics system as claimed in claim 1 wherein said real-time image processing means comprises a real time object processor means for rendering said edited image data, and said system further comprises a colour transformation means connected to said real time object piocessor means and adapted to receive said rendered edited image data and to determine said image signal from said rendered edited image data.
2. 3. A graphics system as claimed in claim 1 or 2 wherein said image data is based on quadratic polynomial fragments. 15 4. A graphics system as claimed in claim 1i, 2 or 3 wherein said real-time image "i processing means also produces a video image signal for driving a video presentation means and said graphics system further comprises said video presentation means adapted to receive said video image signal and display a corresponding video image. A graphics system as claimed in claim 2 wherein said colour transformation means 20 includes a colour mixing and generation device for each colour compo.. nt of said image signal.
3. 6. A graphics system as claimed in claim 5 wherein said colour transformation means is connected to said host processor and setup and control informatior:.,: ,d by said colour 2 transformation means is alterable by said host processor means.
4. 7. A graphics system as claimed in claim 5 or 6 wherein said colour transformation means includes a memory device having a plurality of colour storage areas.
5. 8. A graphics system as claimed in claim 7 wherein said memory device further com- prises a dual ported memory device with one port connected to said host processor and the contemts of the colour storage areas are alterable by said host processor.
6. 9. A graphics system as claimed in claim 4 wherein said video image signal comprises only a portion of the image which is to be printed by said copier. A graphics system as claimed in any one of the preceding claims wherein said input includes a plurality of memory storage housing means adapted to receive detachable mem- ory storage devices containing object image data. (RTO3)(238781 AU)(CFP107AU) -12-
7. 11. A graphics system as claimed in claii wherein said detachable memory storage devices are in the form of non-volatile memory cards.
8. 12. A graphics system as claimed in claim 10 or 11 wherein said memory storage devices include system code used in the operation of said graphics system.
9. 13. A graphics system as claimed in claim 10, 11 or 12 wherein said input further com- prises detection means for determination of the presence or absence of said detachable memory storage device.
10. 14. A graphics system as claimed in any one of the preceding claims further comprising a touch panel, sensitive to a users input and adapted to forward the location of said input to said host processor means. A graphics system as claimed in any one of the preceding claims further including dial control means connected to said host processor means and adapted to receive direc- tional inputs from the user of said graphics system.
11. 16. A graphics system for a colour copier substantially as described herein with refer- S 15 ence to Fig. 1, or Figs. 2 and 3 of the drawings. a a a S(RTO3)(238781 AU)(CFP07AU) ,(RTO3)(238781AU)(CFP 107AU) Abstract A PRESENTATION GRAPHICS SYSTEM FOR A COIDUR LASER COPIER In order to produce high quality colour presentation graphics such as posters, advertisements, notices, greeting cards etc., efficiently and at a low cost, there is provided a graphics system for a colour copier(24). The system includes a memory card input for object image data, a host processor connected to a user controllable keyboard (20) for selecting and editing the object image data to create edited image data, a real-time object processor (12) for rendering the edited image data to output an image signal (17) to the copier (24) for printing an image represented by the image signal. The system is characterised by the absence of an image frame store. Fig. 1 *e (RTO3)(180424:LDP)