AU660293B2 - Improved code pad - Google Patents

Description

IL

f3O2 3 0 P/00/0011 Regulation 3.2

AUSTRALIA

Patents Act 1990 COMPLETE SPECIFCATION FOR A STANDARD PATENT

ORIGINAL

S*

0 *00* 0 000 0 0 00 0 0 0* 0* 0 4 0* Name of Applicant: NIDAC SECURITY PTY. LTD.

00000.

0**S S S 0* S

*S

SS*. Se 0 @005e0 0 50 5 0 0 0* Address for service in Australia Invention Title: CARTER SMITH BEADLE, Qantas I-ouse, 2 Railway Parade, Camberwell, Victoria, 3124, Australia, Attorney Code SA.

IMPROVED CODE PAD The following statement is a full description of this invention, including the best method of performing it known to me/us: -1I- 0 00 0 25 9 20 o 0 25 2 TITLE: IMPROVED CODE PAD This invention relates to push-button controllers, such as keypads or boards for security systems such as intruder alarms, security door releases and the like.

Most security systems are now activated and deactivated by the entry of a secret code by means of a push-button controller or keypad. In most existing keypads, the signal output from each key is transmitted to the alarm controller by means of individual wires connected to the output from each key. Where the keypad is separated from the alarm controller, as is usually desirable for security reasons, the wiring for each key must extend from the keypad to the controller. This form of connection not only complicates installation but also leaves the wiring susceptible to electrical and radio interference.

Where more than one remote keypad is required (e.g.

at each entry door), the hard wiring of each push-button must be repeated for a considerable distance, thereby increasing installation cost. Hard wiring also limits the number of valid codes which may be used with a particular system since no number may be repeated, and each time a code is changed, rewiring of the keypad is necessary.

In addition to the above, since the prior art keypads are always in an active state, any response, such as a code validation signal, sent to one remote keypad will be repeated at all other keypads and this may be disconcerting or even frightening to persons tbnidac.spe 91 11 1

S.

S..

20 25 3 located near other keypads who may not be aware that another keypad is in use.

It is an object of the present invention to provide an improved push-button controller in which the above described problems of prior art systems are at least ameliorated.

The invention therefore provides a push-button controller or keypad, comprising a multiplicity of electrical key switches connected to an encoder means, said encoder means being arranged to generate a serial code of data from signals generated by said key switches, a single data line connected to said encoder, a decoder means adapted to be positioned remote from said encoder and connected thereto by said data line and at least a ground line, said decoder being programmable to generate an acknowledge signal or an error signal for transmission along said data line to said encoder.

By arranging the encoder and decoder in different locations, greater security of the decoding electronics Is achievable, and cutting or shorting wires at the keypad will not result in activation or deactivation of the alarm.

Since serial data transmission is used, a number of remote encoders may be connected in parallel to the decoder without the need for synchronization or costly shielded cable.

Both the encoder and the decoder preferably utilize a similar microprocessor configured to perform the required functions. The decoder microprocessor tbn.idac. spe 91 11 2G 15

CC

CC. 4 preferably has an associated programmable memory means, such as a EEPROM in which the desired valid codes may be programmed. Each remote push-button encoder includes means for audibly and/or visually indicating the status of the code which has been entered so that the user knows whether the code entered is correct. In one preferred form, an acknowledge signal gene.:ated by the decoder is indicated by a predetermined audible and/:or visual signal, while an error signal is indicated by a different audible and/or visual signal.

The decoder may be programmed withn a multiplicity of different valid codes so that each user of the system may have their own personal entry and exit code. The decoder may be easily reprogrammed to change the valid codes, for example, each time there is a personnel change in the area being protected.

The encoder is also preferably configured to enable a panic or duress code to be entered, and the entry of such a code may cause any desired activity, such as the activation of a remote alarm or the activation of a dialler to notify a security post or the police. In one form, the activation of one particular button on the key pad during the entry of any part of any valid code will cause the decoder to recognise a panic or duress situation.

When the encoder is not in use, the microprocessor is preferably programmed to revert to a stop mode of operation in which a very low level of current (e.g.

about 0.25 mA) is drawn to reduce the drain on the tbnidac.spe 91 11 1 Sa S. 2 5 battery power supply. When any button on the keypad is pressed, the microprocessor becomes active to enable a code to be entered and acknowledged. Where more than one remote key pad is connected to the system, only that keypad in use will be active and all other keypads remain in the stop mode. In this way, acknowledge and other signals received by the active keypad will not be repeated at the other keypads.

The system may be programmed to operate in a oneway or priority mode in which the actuation of a single button plus the enter button will cause the system to be activated as an temporarily authorised person, such as a cleaner or workman, leaves the premises. In the present embodiment, this is achieved by actuation of the button followed by actuation of the enter button. This one-way mode of operation does not allow the temporarily authorised person to turn the alarm system off and therefore maintains security.

If desired, each valid code may include a PIN which is used to identify the person gaining access to the premises. The decoder stores the PIN so that the identity of the person gaining entry can be subsequently determined.

A preferred embodiment of the invention will now be described with reference to the accompanying drawings in which: Figure 1 is circuit diagram of a preferred decoder circuit for the push-button controller; Figure 2 is a preferred encoder circuit diagram for tbnidac.spe 91 11 6 a 15 *a a the push-button controller; Figure 3 is a preferred home keypad circuit diagram which also includes a schematic circuit diagram showing the method of connection of two keypads and a home keypad to a decoder connected to an alarm system CM8, and Figures 4 to 7 are flow charts which illustrate one preferred embodiment of firmware for use with the decoder and encoder circuits shown above.

Referring firstly to Figures 1 and 2 of the drawings, the push-button controller or keypad embodying the invention comprises an encoder KCR (Fig. 2) to which an array K of key stitches is connected, and a separate decoder KC6 (Fig. 1) interconnected by a data line DTA and a ground line connection GND. The encoder KCR is configured to transmit a serial data stream along the data line DTA according to the key switches pressed. The decoder KC6 functions to receive the data stream and determine from separately stored valid codes whether the code which has been entered is valid or invalid. The decoder then transmits an acknowledge or error signal to the encoder along the data line DTA to cause the encoder to generate an audible and visual accept or error signal, as described further below. Both the encoder and the decoder comprise a Z86C08 Microprocessor, which is a member of the ZILOG Z8 family. This microprocessor was chosen for the present design for its low pin-out and small package size, its powerful instruction set, stop mode and watchdog functions, and its low power tbnidac.spe 91 11 0 *000 i 15 0 20 fee**: 7 consumption. The microprocessors are programmed to perform the required encoder and decoder functions, and the nature of programming of each microprocessor may be determined by testing the status of port P02, a high state indicating an encoder and a low state indicating a decoder. The program occupies two kilobytes of read only memory and scratchpad random access memory is used for temporary storage of data.

HARDWARE DESCRIPTION Decoder Referring to Figure 1, in typical security systems the main power source is backed up by the use of a 12 volt battery supply. This necessitates a means of applying power quickly to the microprocessor system so that it never operates with marginal power supply rails, even though the backup battery supply may have run down.

The KC6 achieves this by the use of a low power operational amplifier U1 (pins 5,6,7) which senses the battery volts via R4 and R5, and compares it with a zener reference diode VR1. The output of this operational amplifier is applied to the series pass transistor Ql.

VR2 is a three terminal series pass regulator which converts the switched 13.7 volts to 5 volts suitable for the Z86C08 U2 microprocessor. VR3 is another three terminal series pass regulator which is connected in a current source configuration to provide a source of 23 milliamps to the power/data line (DTA). At switch on however there may be up to 10 remote keypads connected tbnidac.spe 91 11 0 15

S..

*.0 20 .9 0 00000* 0 0 0000 8 to the DTA line and these all have their own power filter capacitors which need to be charged up quickly.

Also each remote keypad will operate for about milliseconds until the program takes them into the STOP mode where the power consumption is considerably less.

To achieve this "extra" power at switch on, Q2 has been added driven by operational amplifier Ul (pins 1,2,3).

It remains ON for a period determined by R2 and C3, approximately 0.2 second.

The six outputs of the Decoder are buffered through the driver chip U 4 to provide each output with a current sink capability of around 100 milliamps.

U3 is an EEPROM and is connected via four control lines to the microprocessor ports. The four lines are: Chip select serial clock data input (DI), and data output (DO).

Y1 is a 3.579MMhz ceramic resonator providing the clock source for the microprocessor.

Acknowledge codes are sent to the DTA line via U4 (pins 7,10).

Encoder Referring to Figure 2, the power line filter referred to above is supplied by D1 and Cl. Cl having sufficient charge to supply power to the Z86C08 Ul during data transmission time when the DTA line is being controlled according to the serial data bit stream from Ql. Acknowledge codes are received on the line through port P31 which is protected from excessive voltages by the use of zener diode VR2. The keypad K is connected in tbnidac.spe 91 11 9 0*e* gO 9 9 9* eq 09 C *9 9 a matrix mode as shown and Q2 serves to signal the processor Ul via P27 whenever any key is pressed. This enables the processor to be released from the STOP mode with the negative edge transition on P27. Audible and visual feedback of the key press is provided by the piezo element P1 connected to port P01 and LED E2. This LED also serves to act as a previous alarm warning when operated by the alarm control panel via the optional connection (PA1). El is a green status LED which is also optionally used by the alarm control panel via the "STA" line to signal the alarm on condition and exit delay period. A tamper switch is also provided which may optionally be used to signal to the alarm control panel unauthorized tampering of the unit.

FIRMWARE DESCRIPTION The flow charts Keyflow 1 to 3 (Figures 4 to 6) detail the logical flow for the Decoder and flow chart Keyflow 4 (Figure 7) details the Encoder logic. The program always begins at the start of flow chart 1 and branches where the Encode/Decode test is performed.

The flow charts are organized with a rectangular box designating some type of action to take and the diamond boxes representing some type of decision to be made. The charts are generalized to show the main decision and action processes within the code. Sometimes a label that is used in the actual source code appears on an inter-connecting line.

Referring to flow chart 4, the Encoder and Decoder utilize the port allocations in slightly different ways, 0 20 i S 0 0 tbnidac.spe 91 11 10 the first action therefore is to establish the correct port mode. Various registers are cleared and a pointer is set up to point to the start of an area in RAM to be designated a "BUFFER" for the key entry sequence. As discussed below, the Encoder falls into four categories: INTERNAL, HOME, EXTERNAL, and TRANSMITTER.

A brief distinction between these is as follows: INTERNAL Indicates a pad for internal use.

This pad has all of the function features.

HOME This is a modification to the

S.

99 0 15

S

0 9 6 9 9 9 20 9

S

S

:25

EXTERNAL

TRANSMITTER

internal pad to provide only 2 functions: HOME and EMERGENCY. It would normally be used in a domestic installation and located within a master bedroom. It does NOT have an ENTER key as do the other keypad types, and is expressly designed for single key operation.

This pad does not include the abbreviated key sequences for "One way code"(#,enter) or Emergency (*,enter).

This is effectively a keypad which does not use any interconnecting wires. It uses a small in-built transmitter to transmit the key codes to a receiver connected to the Decoder. It therefore cannot receive tbnidac.spe 91 11 15 1 11 any acknowledgment codes back from the Decoder and therefore needs to handle the acknowledge response section of the program a little differently.

The transmitter keypad can be identified by an absence of a "marking high" state of the receive input line on port P31. External or internal are set on the Encoder by the status of port P32. If the link on the board is cut, P32 goes high to indicate an EXTERNAL pad.

The Decoder identifies a pad as external, or internal, by the preamble characters transmitted prior to the key sequence.

Flow chart 4 therefore shows the various testing for the type of keypad. If it is a transmitter model a flag is set so that when it will know not to expect any acknowledge codes. The internal/external identifier, simply means loading a different preamble character to go ahead of the key sequence. The home pad type is determined by testing the validity of a connection between ports P20 and P32.

Since the Encoder is normally in a STOP mode to conserve power consumption, one needs to determine if the program is running because of a "power applied" condition or a key press. A key press takes the microprocessor out of the STOP mode by the negative going edge on port P27. On leaving the STOP mode, program execution is from the same memory location as a normal power on situation (OCH).

SWS 5

S

*J S

S

:25 tbnidac.spe 91 11 15

I

**CC

A

25 12 Detection of a key press takes us to the next main section of flow chart 4, i.e. load the transmitter buffer with key characters, count the keys and check for time-out. If the time-out is exceeded, i.e. no key pressed within 10 seconds the unit will go into the LOP mode once again. This is achieved by internal programming of the encoder microprocessor U1 in a known manner. If the maximum number of keys has been entered without detecting the "enter key" then the unit restarts, effectively wiping the transmit buffer and entering the key as though it were the first. The HOME keypad is a special case since we want it to respond as a single key operation. The "star" or characters are established from the particular key press and the "enter" key is added under program control. The "enter key" is loaded to the transmit buffer and the key counter incremented.

The next main section (last) in flow chart 4, transmits the string of characters in the buffer and waits for a response from the Decoder. If it is a transmitter model, NO response is expected and the unit goes straight into STOP mode; otherwise we expect to receive a single character A,B,C or D within 2 seconds to characterize the Decoder response to the code sent to it. The responses are summarized as follows: Mean, a successful code. (2 blips) Means an unsuccessful code. (Blarp) Means a successful ADD/DELETE functih.blips) tbnidac.spe 91 11

.R.

ccc. 15 C C 25 to 13 Means a quiet acknowledge. (silent) If the character is none of the above, or if the unit times out the 2 seconds, then a "blarp" is sounded to indicate "fail".

Referring to flow chart 1, the EEPROM is then tested to see if it is empty of data or already programmed with data. If the EEPROM is empty, it is preprogrammed automatically to the following default means values. All outputs set to zero and all outputs set to a BISTABLE mode of operation. The outputs are then restored to that defined by the default values. The Decoder then sits in a receive preamble character loop waiting for any information to be received off the line.

Since the first five characters sent from the Encoder are preamble characters defining whether the pad is an INTERNAL or EXTERNAL pad, it remains in the loop simply setting or re-setting the Internal/External flag bit in the status register. When the first character that is NOT a preamble character is received, the character counter is cleared to zero and the 10's of milliseconds timer is also cleared to zero. A receive character loop is entered where we test for certain critical characters and also for a code duration time-out of 400 milliseconds. If the time-out is exceeded the program branches back to the RESTART location. The first character tested is the ENTER key or defining the end of the string. If received, the ACKNOWLEDGE register is tested for characters and if there are any, indicating a fault at this point then the acknowledge is tbnidac.spe 91 11 Let 15 a to 2 LSSO 15 00 96too0 0 0S 0b 0 0 a 14 sent, and the program reverts back to the RESTART. If NO acknowledge characters are present at this point we test the STATUS register to see what MODE we are in, and branch according either to flow charts for "normal" mode, or flow chart 3 for the "Add/Delete" mode.

While assembling this string of characters from the Encoder into the receive buffer, the critical characters tested are as follows: The "star" or is valid either as a first character to indicate ADD when in the ADD/DELETE mode, or in any position as a DURESS identifier in an otherwise normal code. In the ADD/DELETE mode if it appears in an position other than first it is regarded as an error and the ACKNOWLEDGE register is loaded with The flow chart shows the testing of n (character counter) to determine if the is the first character received.

The character is a special case, and is sent only by the HOME pad to toggle an alarm system on or off in the "HOME" mode. This is used in the NIDAC CM8 alarm panel where various alarm sectors can be isolated for the home mode of operation. A "HOME" flag is set in the status register and the program loops back to get the next character without entering it in the receive buffer. The next character expected of course will be the 'ENTER" to mark the end of the string.

The "hash" or character is valid as the first character in the ADD/DELETE mode to identify a DELETE function. It is also valid in the normal mode on the tbnidac.spe 91 11 15 20 9*4*

S~

1 15 INTERNAL pad to identify a ONE WAY CODE. The flow chart shows that if either the ONE :AY CODE or the ADD/DELETE mode is already set then receipt of a will constitute an error condition and a (fail" is loaded into the acknowledge register. In a normal mode the may be used as part of the 3-7 character code as a PIN number delineator.

Referring to flow chart 2, the number of characters in the code is our first clue for appropriate action. As shown in the flow chart, the character counter is tested firstly for zero. The abbreviated codes from the internal pads e.g. HOME, ONE WAY, EMERGENCY have zero character count since the and and are not counted as code characters. The exception to this is the if it is included as part of a normal code for the purpose of acting as a PIN number delineator. Hence the chart shows that if the character count is zero and it is an internal pad, then we test the status flags for DURESS/EMERGENCY, ONE WAY CODE, or HOME. The appropriate outputs are set, and either or acknowledge characters are sent back to the Encoder. Note that with these abbreviated codes there is no need to verify the codes against any stored code in EEPROM. If the code character count is zero and it is not an internal pad, this is then an error and is sent to the Encoder and the ATTEMPTS counter is incremented. Should the failed attempts reach a value of 5, the Decoder will lock for a period of 60 seconds. This is included to frustrate the attempts of unauthorized code breakers, limiting the tbnidac.spe 91 11 16 *9 9 a* 15 44 9 J

B.

*'20 8414 a 0,

S

0 S attempts to 5 each one minute.

If the character counter is 3 or greater, it is then checked for an exact match against the stored codes in the EEPROM. A fail on this "CODE VALID" test, again sends a to the Encoder and increments the ATTEMPTS counter.

If the match is VALID, we need to check firstly if the output code is either a or a since these represent special cases. The denotes a MASTER code and the appropriate action is to toggle the ADD/DELETE NORMAL mode bit in the status register. The resulting mode is then tested and either 2 blips or 5 blips corresponding to acknowledge codes or is then sent back to the Encoder. If the output code is this means the code is a "HEX" code where the operator wishes to effect multiple outputs at the same time. The second digit following the in a HEX code defines the outputs to be operated. Note the outputs are not simply toggled, but are forced to the state determined by the code. Outputs 1,2,3 are the ones effected by the code.

The first digit following a is a PIN number or "Operator Identifier" and is sent to a serial line to an optional decoder chip called a "4017". Hence the action block "CLK 4017" meaning clock the 4017.

The new output states are saved in EEPROM and the acknowledge character sent the Encoder. If EMERGENCY/DURESS had been set we need to wait 1 second, reset it and return to the RESTART location.

If the output code is NOT or then it must tbnidac.spe 91 11 Oi 15 *soe a 20 17 be 1-6 (normal outputs) and these may operate in either bistable or monostable modes. The mode is retrieved from the EEPROM and the appropriate output set accordingly.

If the output is monostable, the Decoder cannot receive any further data until expiration of the monostable time constant. Also there is no value in saving the output status in EEPROM for monostable outputs.

Referring to flow chart 3, this shows schematically the ADD/DELETE mode of operation.

OPERATION

The Encoder KCR transmits 300 baud ASCII data over the serial line DTA to the Decoder KC where the data is converted to 4bit binary and compared to the contents of the EEPROM U3. Success of this compare will activate the output, and will generate an acknowledgment signal AKN by way of one of four AKN codes transmitted back over the line DTA. The current output status of outputs 1-6 are stored in the EEPROM so that after a power fail the outputs can be restored. The code transmitted includes five characters of pre-amble in order to "wake up" the vox on a radio receiver. The preamble characters define if the Encoder is an internal or external device. The way in which the Decoder handles the duress, acknowledge and home mode signals is determined by the internal/external mode identifier character. The string length is 5 (pre-amble chr) 7 (max code digits) 1 (end of string). When in the ADD mode the EEPROM stores an extra digit at the start which defines the output port number. Codes are always stored tbnidac.spe 91 11 09 19 0*.S 0 0 0 00 0 S* S ,5 0 50 0 0 0..

0

S

S

00 18 as eight character codes. Shorter codes fill the empty registers with "3F" Hex marking the end of the string.

NORMAL MODE The unit will power up in the normal mode. The output states will be restored to the states prior to the power down. If the memory was totally cleared, then certain default parameters referred to above are automatically programned into memory.

The ADD/DELETE MODE may be entered either by using the MASTER CODE, or by inserting the LINK on the Decoder board. Some ADD/DELETE functions will only operate with the LINK in place. These are: 1. Program a new monstable value 2. Erase a MAS

T

ER code 3. Erase ALL codes 4. Program a new MASTER code A successful acknowledge in the ADD/DELETE mode is indicated by 5 blips from the piezo P1.

MASTER CODE is used for REMOTE setting and resetting of the ADD/DELETE made and is identified as an OUTPUT CODE 9. It also has 3-7 digits. It is only effective if the ADD/DELETE link is left OFF on the PCB.

It enables the following functions to be performed without the need to access the LINK on the Decoder board: 1. Erase a particular code 2. Erase a group of codes for a particular output 3. Program a new code A ONE WAY CODE state may be achieved by pressing 15 25 tbnidac.spe 91 11 19 0**0 *0 0 &s* *0 s o is

S

20 ft9 "ENTER" to set output 1 ON. This output is normally used for the ARM function for an alarm system.

The INTERNAL keypad is the only pad which can effect this function.

The EMERGENCY state is achieved by pressing "ENTER" on an INTERNAL keypad, or simply on a HOME keypad will activate output 6 for 1 second. Note this will not work on an EXTERNAL pad. However output 6 may be operated as a normal output only in configuration with the appropriate CODE.

The HOME keypad KCH (Fig. 3) has only two keys which operate as single button entries. you do not need an ENTER KEY"). One is the emergency function described above, and the other is a HOME toggle function which activates or de-activates output 5. This output is normally used to set a security system into the HOME mode. The HOME keypad is for user convenience and would normally be located in the master bedroom. No other keypad has single button entries. Output 5 may also be operated from either an INTERNAL or EXTERNAL keypad by using the appropriate CODE.

When in the ADD/DELETE mode either by entering the MASTER code, or inserting the on decoder board link, the indicates an ADD parameter, and the indicates a DELETE parameter. The next digit must represent the output number 1,2,3,4,5,6,7 followed by the new number to write or simply enter in the case of erasure. Note 7 is NOT an output number since there are only 6 outputs.

It is used for a special "HEX" function which enables tbnidac.spe 91 11 20 outputs 1,2,3 to be activated in any combination with one code or de-activated in any combination with another code. This is described under "HEX" below.

The following describes the key entry for various functions: s 10 S S

S.

S 5 15 9 5 S. S CODE DELETION: enter Clears the MASTER code. LINK must be in place #,0,1,2,3,enter Clears ALL codes. LINK must be in place #,X,enter Clears ALL codes with the output designated by X. Legal values for X are 1,2,3,4,5,6,7.

#,NNNNNNN,enter Clears the particular code represented by 3-7 digits. If the code does not exist it will respond with a "failure acknowledge" (blarp) CODE PROGRAMMING: *,X,NNNNNNN,enter Programs a new code, provided it does not already exist. X represents the output code, valid values are 1,2,3,4,5,6,7. The code numbers represented by may be 3 to 7 digits in length and may include a in any location except the first. The number following the is used as a PIN identifier, and is output to a decoder so that operator identity can be transmitted to the control station.

*,9,NNNNNNN,enter Programs a new MASTER code.

Any output can be programmed for either BISTABLE or monostable operation with variable ON times. The default value is 0. The position after the 8 denotes the particular output.

PROGRAMMING PRIORITY OUTPUTS (MEMORY 7) tbnidac.spe 91 11 9* o.o 20 99 15 20 9 o 21 In some applications, it is desirable to set or reset more than one output with the same code. Memory 7 enables the user to set or clear outputs 1, 2 or 3 to any desired state. For example, one desired state may allow the system to be armed using a predetermined code while prohibiting disarming with the same code (one-way code). Memory 7 can store up to 7 variants of how OU1, OU2 and OU3 operate in conjunction. There are some rules to remember: 1. Many different codes can be added to memory 7, not just one.

2. The code must contain a followed by at least 2 digits.

3. A minimum of 4, and maximum of 7 digits can be used. (including 4. The cannot be the very first digit in the code.

The 1st digit after the represents a PIN number (for a future development). It can be any digit.

6. The 2nd digit after the represents the output status of OU1, OU2 and OU3. The chart below shows the digit that determines the status of the outputs:- 2nd diai.t OU1 1 on 2 off 3 on 4 off on tblAdac. spe OU2 off on on off off OU3 off off off on on 91 11 6 off 7 on 0 off Add priority codes *7 26#01 B mode.

22 on on on on off off (Program link ON) The 1 will set OUI on in the operate 5 6*e 0 0 *00* *5 15 *0 *r S 20

S

0

S

C

*7 14#23 B The 3 will set OU1 and OU2 on in the operate mode.

*7 54#20 B The 0 will set OU1, 2 and 3 off in the operate mode.

The codes shown are examples only.

In the Operate mode, each code entered overrides the previous code. When deleting a code from memory 7, precede the code with 7 e.g. 7 code E. If erasing all codes in memory 7 E.

MEMORY 8 (Momentary output settings) To program, enter the ADD/DELETE mode and enter: 8, n, n, n, n, n, n, enter Where n is: 0 Bistable mode 1 1 second 2 2 seconds seconds seconds seconds tbnidac.spe 91 11 23 seconds seconds seconds

CO

SR

C

SR..

Cr 20 0 seconds In any one code, digits may repeat. This is an advantage over prior art keypads in which no number repetition is allowed. The character may be used to identify the start of a PIN number. It is still counted as one of the digits and becomes part of the valid code, but may NOT be used as the first digit in the code but may be used elsewhere in the code.

The codes for each output must NOT be the same.

Note also that a single star inserted anywhere within a valid code is interpreted as a DURESS alarm. In this case the code is acted upon and acknowledged in the normal way so as not to arouse suspicion, and output 6 is therefore triggered so that the DURESS condition, can be acted upon. On an INTERNAL keypad the duress code "*,enter" may be used without entering a valid 3-7 digit code.

If a code is accepted as valid by the DECODER it is acknowledged in one of 4 ways using ASCII codes A,B,C,D.

Each code corresponds to the following: A normal code entry success. blip, blip B normal code entry fail blarp C Add mode success tbnidac.spe 91 11 j 1 0 24

*GOP

5*62

S

S

SS9 S

SSS*

6 blip,blip,blip,blip,blip D Quiet acknowledge silent The maximum number of characters in any code string to be stored in the EEPROM is 8, which includes the output port number. The first 4 bit number is ALWAYS the output port number. This means we can always start a code at the beginning of the 16 bit EEPROM register pairs, i.e. 2 registers are needed for any one code.

CODE VALIDITY Only the "numeric" and characters are stored for comparison in the received code. This should never exceed seven digits. Comparison with stored EEPROM codes is always done on 7 digits even if the code is only 3.

The receive buffer is cleared prior to assembling the received string.

PROGRAM CODE (MEMORY 9) Most memory type keypads allow user codes to be added or change by use of a "program code". Some systems store their program code in a DRAM or SRAM (Dynamic or Static RAM) which lose this code when the power is removed, and then default to a "factory preset" or "house code" which is generally publicized in the instruction literature. This method can compromise security as a person skilled in the art could purposely remove the power to force this house code condition and then program their "own" program code and thus user code for illegal use at a later time.

The present system allows only authorized persons to add, change, or overwrite a forgotten "program code" tbnidac.spe 91 11 too.

'60*.0 15 *Deaf: Do

S

*0.0*6 20 Cdp 6 0

CS,..

S

C.

G

C

25 by using a program link at the safe protected environment of the decoder. This code is stored indefinitely during a power break by use of an EEprom.

One of the major advantages of the push-button code operator described above is that the Decoding electronics may be secured in a location which is remote from the push-button array and only two wires are required to connect the Encoder to the Decoder thereby considerable simplifying installation. Up to ten pushbutton/Encoders may be connected in this way to the same Decoder since the use of serial data transmission enables the Encoders to be connected in parallel without synchronization or expensive shielded cabling. Since the Decoder may be programmed with up to twenty-nine different codes, each user can have a unique operating code. Each user may also be required to use a PIN so that access to the area being protected by a particular person may be subsequently determined. The panic or duress facility allows the user to advise a remote station the user is under duress without any indication appearing at the keypad. When each keypad is not in use, it reverts to the STOP mode in which a very low current is drawn thereby preserving the life of the power supply to the keypad.

tbnidac.spe 91 11

Claims (6)

1. 4.. .9 9 9@ .944 S.. 4 0 S. 4 2 S The Claims defining the invention are as follows 1. A push-button controller or keypad, comprising a multiplicity of electrical key switches connected to an encoder means, said encoder means being arranged to generate a serial code of data from signals generated by said key switches, a single data line connected to said encoder, a decoder means adapted to be positioned remote from said encoder and connected thereto by said data line and at least a ground line, said decoder being programmable to generate an acknowledge signal or an error signal for transmission along said data line to said encoder. 2. The controller or keypad of claim 1, wherein said encoder and said decoder both utilize a similar microprocessor configured to perform the required functions. 3. The controller or keypad of claim 2, wherein the decoder microprocessor has an associated programmable memory means in which the desired valid serial codes are programmed. 4. The controller or keypad of any preceding claim, wherein said encoder means includes means for audibly and/or visually indicating the status of a code which has been entered in response to the generation by said decoder of an acknowledge signal or an error signal. The controller or keypad of claim 3, wherein said programmable memory means is programmable with a multiplicity of different valid codes so that each user of the system may have their own personal entry and exit tbnidac.spe 91 11 27 S 0*S* 0 15 00 0@.Sgs S S.. 0 S. code.
2. 6. The controller or keypad of any preceding claim, wherein said encoder is configured to enable a panic or duress code to be entered, said encoder including means for responding to the entry of said panic or duress code, including the activation of a remote alarm or the activation of a dialler to notify a security post or the police.
3. 7. The controller or keypad of claim 6, wherein said encoder is configured such that the activation of one particular key switch during the entry of any part of any valid code causes the decoder to recognize a panic or duress code.
4. 8. The controller or keypad of any preceding claim, wherein said encoder is programmed to revert to a stop mode of operation in which a very low level of current is drawn to reduce the drain on the power supply to the encoder, said encoder being configured such that when any one of said key switches is activated, the encoder reverts to its normal mode of operation.
5. 9. The controller or keypad of any preceding claim which is programmable to operate in a one-way or priority mode in which the actuation of a single button plus the enter button will cause the system to be activated as an temporarily authorized person, such as a cleaner or workman, leaves the premises. The controller or keypad of any preceding claim, wherein each valid code includes a PIN which is used to identify the person gaining access to the premises, said tbnidac.spe 91 11 28 decoder being configured to store the PIN so that the identity of the person gaining entry is able to be subsequently determined.
6. 11. A push-button controller or keypad substantially as hereinbefore described with reference to the accompany drawings. DATED this 20 November 1991 SMITH SLTNBEADLE Fellows Institute of Patent Attorneys of Australia Patent Attorneys for the Applicant: NIDAC SECURITY PTY. LTD. 10 a a a. a. a a a a a. a a. a a S a. a. a a a S 3 a a .a S a. a a. tbnidac. spe 9 12 91 11 1 so of 00' 0w 0, 29 ABSTRACT A push-button controller or keypad K having a multiplicity of electrical key switches K connected to an encoder KCR and a separate decoder KC6 interconnected by a data line DTA and a ground line connection GND, the encoder KCR being configured to transmit a serial data stream along the data line DTA according to the key switched K pressed, the decoder KC6 functioning to receive the data stream and determine from separately stored valid codes whether the code which has been entered is valid or invalid, the decoder KC6 then transmitting and acknowledge or error signal to the encoder along the data line DTA to cause the encoder KCR to generate an audible and visual accept or error signal. a* 0 00 S* 0 S tbnidac.spe 91 11