AU6500996A - Link scheduling - Google Patents

Link scheduling

Info

Publication number
AU6500996A
AU6500996A AU65009/96A AU6500996A AU6500996A AU 6500996 A AU6500996 A AU 6500996A AU 65009/96 A AU65009/96 A AU 65009/96A AU 6500996 A AU6500996 A AU 6500996A AU 6500996 A AU6500996 A AU 6500996A
Authority
AU
Australia
Prior art keywords
link scheduling
scheduling
link
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
AU65009/96A
Other languages
English (en)
Inventor
Richard G Bubenik
Stephen A. Caldara
Michael E Gaddis
Stephen A. Hauser
Thomas A. Manning
James M. Merideth
Raymond L. Strouble
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Ascom Nexion Inc
Original Assignee
Ascom Nexion Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ascom Nexion Inc filed Critical Ascom Nexion Inc
Publication of AU6500996A publication Critical patent/AU6500996A/en
Abandoned legal-status Critical Current

Links

Classifications

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    • H04L47/10—Flow control; Congestion control
    • H04L47/18—End to end
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/163—Interprocessor communication
    • G06F15/173—Interprocessor communication using an interconnection network, e.g. matrix, shuffle, pyramid, star, snowflake
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    • H04L12/4608—LAN interconnection over ATM networks
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    • H04L12/56—Packet switching systems
    • H04L12/5601—Transfer mode dependent, e.g. ATM
    • H04L2012/5685—Addressing issues
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/04—Speed or phase control by synchronisation signals
    • H04L7/041—Speed or phase control by synchronisation signals using special codes as synchronising signal
    • H04L7/046—Speed or phase control by synchronisation signals using special codes as synchronising signal using a dotting sequence

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  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Security & Cryptography (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)
AU65009/96A 1995-07-19 1996-07-18 Link scheduling Abandoned AU6500996A (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US149895P 1995-07-19 1995-07-19
US001498 1995-07-19
PCT/US1996/011919 WO1997004561A1 (fr) 1995-07-19 1996-07-18 Ordonnancement des liaisons

Publications (1)

Publication Number Publication Date
AU6500996A true AU6500996A (en) 1997-02-18

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ID=38659664

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Application Number Title Priority Date Filing Date
AU65009/96A Abandoned AU6500996A (en) 1995-07-19 1996-07-18 Link scheduling

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EP (1) EP0845181A4 (fr)
JP (1) JP2000501897A (fr)
AU (1) AU6500996A (fr)
WO (1) WO1997004561A1 (fr)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1196300C (zh) 1997-11-04 2005-04-06 皇家菲利浦电子有限公司 使用不同传输特性的通信网络
US6324625B1 (en) 1999-03-16 2001-11-27 Fujitsu Network Communications, Inc. Rotating rationed buffer refresh
ES2229917B1 (es) * 2003-07-15 2006-07-01 Diseño De Sistemas En Silicio, S.A. Procedimiento de gestion dinamica de recursos de sitemas de telecomunicaciones en funcion de la calidad de servicio y del tipo de servicio.

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2736092B2 (ja) * 1989-01-10 1998-04-02 株式会社東芝 バッファ装置
US5535197A (en) * 1991-09-26 1996-07-09 Ipc Information Systems, Inc. Shared buffer switching module
US5583861A (en) * 1994-04-28 1996-12-10 Integrated Telecom Technology ATM switching element and method having independently accessible cell memories
US5491691A (en) * 1994-08-16 1996-02-13 Motorola, Inc. Method and apparatus for pacing asynchronous transfer mode (ATM) data cell transmission
US5541912A (en) * 1994-10-04 1996-07-30 At&T Corp. Dynamic queue length thresholds in a shared memory ATM switch
US5521916A (en) * 1994-12-02 1996-05-28 At&T Corp. Implementation of selective pushout for space priorities in a shared memory asynchronous transfer mode switch

Also Published As

Publication number Publication date
EP0845181A4 (fr) 2001-07-18
WO1997004561A1 (fr) 1997-02-06
EP0845181A1 (fr) 1998-06-03
JP2000501897A (ja) 2000-02-15

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