AU645122B2 - An ATM load distribution arrangement - Google Patents

Description

P/00/01l 28/5/91 Regulation 3.2

AUSTRALIA

Patents Act 1990 bu~S @4 C 4 we 4 4 a *4 eC 4 C

S

C Sq

C

04*4 04 0 444* 06 C.

U.S

S Ut) C *4 44 49 C 4

ORIGINAL

COMPLETE SPECIFICATION STANDARD PATENT Invention. Title: "AN ATM LOAD DISTRIBUTION ARRANGEMENT" The following statement is a fuill description of this invention, including the best method of performing it known to tis:- This invention relates to a method and a circuit arrangement for evenly distributing ATM cells to a group of lines.

Such a method and circuit arrangement are known from J.S. Turner, "Design of a Broadcast Packet Network", published in "Proceedings of INFOCOM April 1986, pages 667 to 675.

Under the heading of "Link Groups", this publication states that several lines are combined into groups within an ATM switching matrix. The lines in a group must have the same destination. The traffic is distributed uniformly among all the lines in a group. For this purpose, the ATM cells destired for a group are distributed to the lines in. the group cyclically.

In the case under discussion, the concept ATM (ATM Asynchronous Transfer Mode) is considered to be a data transmission system in which the data can be combined into segments of equal or unequal length, and then provided with a *890 header and transmitted as a sequence of packets or cells. The transfer of short data 15 streams in undivided form, eg. for internal system control purposes, also takes place l by means of such ATM cells.

With the ATM cells being distributed to each of the lines of a group in turn, unequal loading of the lines can result, since the cells are of differing lengths. How- 4 ever, there are also other reasons for combining lines into a group. In that case, it may be necessary to form both large and small groups, with the smaller groups being components of a larger group. For example, a 2-group, together with another 2-group, can form a 4-group. If now the ATM cells destined for one of the 2-groups are distributed cyclically to these lines, and the ATM cells destined for the 4-group are distributed cyclically to the four lines, then the two lines which are common to 25 both groups are loaded more heavily. The technique disclosed in this specification ameliorates bottlenecks occurring on individual lines.

This specification describes a method for distributing ATM cells to a group of lines, wherein for'each ATM cell that line is selected which was least loaded by the cells preceding the cell under consideration.

The specification also describes a circuit arrangement for distributing ATM cells to a group of lines, wherein a selection facility (AE, RL, Fl, F8) is provided which, for each ATM cell, selects that line 1, 08) which was least heavily loaded by the preceding cells.

The basic idea is not to decide the distribution on the basis of the incoming traffic, but on the basis of the outgoing traffic, by always selecting from the lines being considered the one which was least heavily loaded last time.

Additional features described in the specification can be applied separately or in combination. For the case in which buffers are allocated to the lines, a solution is preferred in which firstly the occupancy level of the buffers is established to determine the selection, and secondly, for equal occupancy levels, out of each pair of lines, the one is selected that was not chosen last time. Even if only the number of ATM cells contained is considered in the occupancy level of the buffers, and not the cell lengths, the cell length nevertheless forms part of the selection criterion because for longer cells the occupancy level changes more slowly than for shorter cells. This solution is also found to be advantageous when the lines have different capacities. This can be because of different transmission rates on the lines, or because the receiving terminal influences the transmission in some way (eg. by requests or "hand-shaking" proce- 15 dures).

In the following, the invention will be further described by means of design examples and with the aid of the accompanying drawings.

S. Figure 1 shows a block diagram of an ATM switching element with 8 inputs and 8 outputs and a circuit arrangement according to the invention for evenly distributing the ATM cells to these outputs.

Figure 2 shows the nucleus of this circuit arrangement in more detail.

Figure 3 shows the detailed construction of a comparator circuit used repeatedly.

The ATM switching element shown in Figure 1 has eight inputs II, 18, a 25 multiplexer Mx, a unit Hp for detecting cell headers, a buffer PS, a demultiplexer Dx, eight outputs 01, 08, a memory management unit SV, a block RL for path selection, an evaluation unit AE, eight FIFOs Fl, F8, and an additional multiplexer FMx.

This example is based on the assumption that the data stream, ie. the ATM cells to be distributed, is parallelised to L bits in the switching element and is also temporarily stored in blocks of L bits in the buffer PS. The synchronisation circuits, serial/parallel and parallel/serial converters required for this are not shown. Values of the order of L 50 are currently being considered. The number of inputs and outputs given here has only been selected as an example. Indeed, switching elements with 16, or even 32, inputs and outputs are being developed. In addition, there is an internal input and an internal output which enable control data generated in the switching element to be added to the input data stream in the multiplexer Mx for transferring to any selected output, or to take control data, arriving at any selected input, from the outgoing data stream at the demultiplexer Dx, for use internally. This does not form part of the present invention, nor is it a requirement for such a switching element. It is not shown in the drawing and not discussed any further here.

The inputs II, 18 are cyclically scanned by the multiplexer Mx, under the control of the memory management. unit SV, and the cells are stored in blocks of L bits in the buffer PS. The output from the buffer PS is also controlled by the memory management unit SV, in such a way that, after the cyclical distribution within the demultiplexer Dx to the outputs 01, 08, the correct output streams result.

In the present example, the switching action is achieved by the correct processing of the addresses at which the cells to be switched are stored in the buffer. This provides the best use of the available storage space. In principle, however, the cells 15 themselves could be stored in the FIFOs, and not their addresses as is the case in this example and will be described further.

The cell header detection unit Hp detects incoming cell headers, signals them to the memory management unit SV and passes their path selection information on to Sthe path selection block RL. The memory management unit SV searches for a free memory area in the buffer PS, places the cell into the buffer and simultaneously places its address, via the "FIFO Data in" line, on the inputs of all eight FIFOs. The path selection block RL, in accordance with the contents of the cell header, selects the outputs that can be considered, or are predetermined, for the output action. These outputs are passed to the evaluation unit AE in the form of a mask MASK. Fur- 25 thermore, the evaluation unit AE contains the logarithm (to base 2) of the selected group size RGS. From this data, and from the occupancy levels Cl, C8 from the FIFOs., one or more of the FIFOs Fl, F8 is selected and caused, via the selection lines SELl, SEL8, to accept the applied address.

Supplying the group size RGS and the mask MASK separately not only simplifies the processing in the evaluation unit AE; it also allows for the possibility of transferring a cell out at several outputs. If the number of outputs given by the mask MASK is greater than the predetermined group size RGS, an output takes place in each selected group of this size. If the group size RGS indicates 2-groups, but the mask MASK indicates all four outputs to be two 2-groups, then at one output of each of these two 2-groups an output transfer takes place, and thus the incoming cell is duplicated.

If the cells are longer than L bits, the memory management unit SV must arrange that the memory areas chosen for the addresses in the buffer PS can be made to correspond again during the output transfer. This can be ensured by an internal process in the memory management unit SV or, alternatively, by arranging to store the follow-on addresses also in the FIFOs.

The conversion of the cell header contents in the selection block RL is either achieved by algorithms or by look-up tables. The tables can either be predetermined and fixed, or they may be freely selectable by control signals, continuously or at start-up.

The outputting of the cells is controlled by the memory management unit SV in such a way that, at the output of the buffer PS, a time division multiplex signal appears which, due to the cyclical distribution within the demultiplexer Dx, produces 15 the correct cell sequence at the outputs. The discontinuous data streams at the outputs of the demultiplexer can be transformed into continuous data streams by use of buffers, especially in conjunction with parallel/serial converters. At least for the beginning of a cell, the memory management unit SV must, via the additional multiplexer FMx, request the address of a memory area from that FIFO which corresponds to the output on which the next output transfer is to take place. If a FIFO is empty, this must be recognised, and an empty cell must be transferred out.

With the aid of Figure 2, the selection of one of the FIFOs, and thus one output, S' will now be described in more detail Figure 2 shows the eight FIFOs Fl, F8, several comparator circuits CPA, 25 CPD, CPI, CPII and CP arranged in three stages, a multiplexer BMx and 8-way AND circuit AU. The four FIFOs F3, F6, as well as two further comparator circuits CPB and CPC associated with them, and the associated controls, are only indicated by a series of dots.

A first stage comparator circuit is allocated to every two FIFOs, a comparator circuit of the next higher stage is allocated to every two comparator circuits of the first and second stage. Each FIFO can be individualy selected; the comparator circuits of the first stage each represent a 2-group; the comparator circuits of the second stage each represent a 4-group; the comparator circuit of the third stage represents an 8-group, that is it permits the selection of one of the eight outputs. An extension to 16, 32 or even 64 outputs is obvious.

If an additional control channel is to be available, as mentioned earlier, this must be processed directly by the memory management unit SV, since grouping of the control channel with one of the other channels would be inappropriate.

If, in an exceptional situation, the number of outputs is not a power of 2, this can be accommodated by arranging that, as part of the allocation, individual FIFOs or comparator circuits of a lower stage can skip one or more comparator circuits, being allocated directly to a comparator circuit of a higher stage.

Each FIFO transfers an occupancy level Cl, C8 to its associated comparator circuit. In the present example, the occupancy level of the FIFOs is determined, and also transferred, as a 5-bit binary word. In the simplest case, this indicates the number of occupied memory cells in the FIFO. This then corresponds to the number of cells which are ready to be transferred out from the associated output. If the cells are of different lengths, this is not directly reflected in the occupancy level, neverthe- *J less, as the occupancy level decreases more rapidly for short cells than for long cells, 15 the cell length is taken into account to some extent.

A more precise consideration of the cell length can be achieved if this is always transmitted by the memory management unit to the FIFOs and is there taken into account by addition during input, and by subtraction during output.

Instead of transferring the complete occupancy level each time, it would be possible to transfer only two or three of the higher-order bits as a simplified count.

It is also possible to use a derived occupancy level with, say, two bits which can indicate full, empty, and one or two intermediate states, or even a single bit indicating full/not full or empty/not empty. None of these variations affect the principle.

Every comparator circuit selects the lower of the two occupancy levels applied f 25 to it, and transfers this to its associated higher stage comparator circuit. For example, the comparator circuit CPA selects the lower of Cl and C2, arriving from the FIFOs Fl and F2, and passes this on as occupancy level CA to the higher-order comparator circuit CPI. The comparator circuits CPB, CPC and CPD produce the corresponding occupancy levels CB, CC and CD. The comparator circuits CPI and CPII produce the occupancy levels CI and CII and pass them on to the comparator circuit CP.

Via the result lines BA, BD, BI, BII and B, the comparator circuits transfer the selected FIFO to the higher-order comparator circuits and also to the multiplexer BM. At the inputs of the multiplexer BMx, the signals from the result lines BA, B appear, for example, as follows: 10010110 10000100 00000100 At another input with eight bits the following signal is applied continuously: 11111111 From these four signals the multiplexer BMx selects the signal corresponding to the predetermined group size RGS. In the 8-way AND circuit AU, using the selected signal and the mask MASK, via the selection lines SELl, of the relevant ones. Depending on the combinations of group size RGS and mask MASK, several FIFOs, and therefore outputs, are selected. For example: RGS 1: 11111111 output BMx 01110000 MASK 01110000 selected FIFOs RGS 2: 10010110 output BMx 15 11110000 MASK 10010000 selected FIFOs RGS 3: 10000100 output BMx 00001111 MASK 00000100 selected FIFOs The selection lines SELl, SEL8 are also connected to the comparator circuits associated with the FIFOs. These generate signals from them which are applied, via the selection lines SELA, SELD, to the comparator circuits CPI and CPII, there 25 processed and applied, via the selection lines SELl and SELII, to the comparator circuit CP. As remains to be described, by this means a choice can be made between two outputs which are equally appropriate to the assumed conditions.

Figure 3 shows the detailed construction of a comparator circuit. The diagram is self-explanatory and therefore will not be described in detail. One section of the circuit determines whether the two applied occupancy levels, here CA and CB, are equal or not. If they are equal, the complement of the last evaluation, stored in a flip-flop FF, is selected by the multiplexer VMx. If they are unequal, the same multiplexer VMx selects a comparison result produced in another part of the circuit.

The output signal of the multiplexer VMx causes the lower of the two occupancy levels to be switched through, by means of a multiplexer CMx. It also causes a mask to be produced with which the signals on the result lines BI are produced from the signals on the result lines BA and BB; its third function is to be stored in the flip-flop FF, in complementary form, when one of the associated outputs, here the outputs 01, 04, is actually selected.

The example just described has the advantage of rapid operation. The speed is only determined by the propagation delays in the various comparator circuits. The result is available for all stages almost instantaneously and simultaneously. The timing for the FIFOs actually to receive input data can be determined by the mask

MASK.

Whether the cells to be distributed to the outputs 01, 08 originate from different inputs, as in the example discussed, is of no significance for the present invention.

The determination of the loading of individual outputs can also be achieved by completely different means -han by establishing the occupancy level of buffers. The 15 loading can also be determined by traffic measurement devices. The corresponding io, measured traffic load then takes the place of the occupancy levels Cl, C8. The o evaluation remains unchanged. It is preferable to use devices for establishing the S. loadings which are already present for other reasons.

f

S

0 a

Claims (15)

1. A method for distributing ATM cells to a group of lines, wherein for each ATM cell that line is selected which was least loaded by the cells preceding the cell under consideration.

2. A method as claimed in claim 1, wherein for lines which have buffers associ- ated with them, the occupancy level of the buffers is determined, and from any group, that line is selected whose associated buffer has the lowest occupancy level.

3. A method as claimed in claim I, wherein of two lines being considered, the one is selected which was not chosen during the last selection.

4. A method as claimed in claim 3, wherein groups with more than two lines are subdivided into two sub-groups with an equal, or approximately equal, number of lines, wherein each sub-group with more than two lines is likewise subdivided into sub-groups, and wherein of two groups being considered, that one is selected which was not chosen during the last selection. 15

5. A method as claimed in claim 3 as appended to claim 2, or claim 4 as ap- .o pended to claim 2, wherein for unequal occupancy levels of the buffers the selection is made according to the occupancy level, and for equal occupancy levels of the buffers the selection that is made is dependent on the last selection process.

6. A method of distributing ATM cells to a group of lines via a distribution cir- cult, the distribution circuit including first buffer store means in which incoming ATM cells are stored, a header detector detecting the header information for each cell, first control means responsive to the header information to control the input and the output of the first buffer store means, second buffer store means in which cell information relating to each cell is stored by the first control means, second control 25 means responsive to the header information to select one or more lines suitable to carry each cell, the method including the steps of selecting from the one or more lines the line that was least loaded by the preceding cell.

S7. A method as claimed in claim 6, including the steps of monitoring the load of each line and comparing the loads generated on each of the suitable lines by the pte- ceding cell to determine which line was least loaded.

8. A method of distributing ATM cells to a group of lines substantially as herein described with reference to the accompanying drawings.

9. A circuit arrangement for distributing ATM cells to a group of lines, wherein a selection facility is provided which, for each ATM cell, selects that line which was least heavily loaded by the preceding cells.

A circuit arrangement as claimed in claim 9, wherein with lines having buffers assigned to them, the selection facility includes a facility for determining the occupancy levels and an evaluation unit, which select the buffer with the lowest occupancy level and the line assigned to that buffer.

11. A circuit arrangement as claimed in claim 9, wherein storage elements are provided, each of which is assigned to two lines, wherein the storage elements have inputs into which information can be entered specifying which of the two associated lines was last selected for an ATM cell, and wherein an evaluation unit is provided which, based on the contents of the storage elements, always enables that one of the associated two lines which was not selected the last time.

12. A circuit arrangement as claimed in claim 11, wherein storage elements are provided, each of which is assigned to two sub-groups with an equal, or nearly equal, number of lines, wherein the storage elements have inputs into which information can be entered specifying which of the two associated sub-groups was last selected for an ATM cell, and wherein the evaluation unit, based on the contents of the storage elements, selects that line which was not *foe selected the last time.

13. A circuit arrangement as claimed in claim 9, wherein the group is •20 subdivided hierarchically into sub-groups and individual lines in such a way that there are alway, two selections possible in the group and in each sub-group, and wherein the evaluation unit simultaneously specifies a selection for the group and each sub-group.

14. An ATM cell distribution circuit including a method of distributing ATM 25 cells to a group of lines via a distribution circuit, the distribution circuit including first buffer store means in which incoming ATM cells are stored, a header detector detecting the header information for each cell, first control means responsive to the header information to control the input and the output of the first buffer store means, second buffer store means in which cell information relating to each cell is stored by the first control means, second control means responsive to the header information to select one or more lines suitable to carry each cell, line load monitoring means to monitor the load of each line generated by the preceding cell, and comparator means to determine the least loaded line suitable to carry the present cell.

1 5. An ATM cell distribution circuit substantially as herein described with reference to the accompanying drawings. DATED THIS SIXTEENTH DAY OF SEPTEMBER 1993 ALCATEL N.V. *too .0 so .6, I,* S S. to 6 0* S ABSTRACT In order to evenly distribute traffic in an ATM system, and to avoid bottlenecks, the load on each line (01 to 08) is monitored (Cl to CS) and lines suitable for transmitting a particular cell are identified from the header information in the cell (MASK). The loads on the lines generated by the previous cell are compared (CPA, CPB, CPI, CPII, CP), and the least loaded line is selected to catry the new cell. v