AU638766B2

AU638766B2 - Improved HD-MAC television signal decoding arrangement

Info

Publication number: AU638766B2
Application number: AU65976/90A
Authority: AU
Inventors: Mohammad-Reza Haghiri
Original assignee: Philips Gloeilampenfabrieken NV
Current assignee: Koninklijke Philips NV
Priority date: 1989-11-14
Filing date: 1990-11-12
Publication date: 1993-07-08
Anticipated expiration: 2010-11-12
Also published as: EP0428216B1; AU6597690A; EP0428216A1; JPH03175789A; DE69016933D1; FR2654566A1

Description

63876 O R I G I NA L PHF 89607 0R S S 0*SO

S

S..

S S 5. 0 *0 5 0 0 *5 S S 0

S

S S

OS

COMMONWEALTH OF AUSTRALIA PATENTS ACT 1952 COMPLETE SPECIFICATION FOR THE INVENTION ENTITLED: "IMPROVED HD-NAC TELEVISION SIGNAL DECODING ARRANGEMENT" The following statement is a full description of this invention including the best method of performing it know to

US,.-

-I-

SPHF 89.607

IA

26-10-1990 Improved HD-MAC television signal decoding arrangement.

The present invention relates to an arrangement for decoding television signals which are previously encoded at the transmission end with a view to transmission at a predetermined field frequency via a limited passband analog channel which involves a processing operation for reducing the quantity of information components to be transmitted, in such a manner that said transmission is effected either at a first rate at said field frequency or at a second rate at twice lower field frequency or at a third rate at a four times lower field frequency, information components about the motion and the 10 selected rate being also transmitted.

0@e* *s C A previous French Patent Application No. 8805010, filed on April 15, 1988, desc ibes more specifically a television signal decoding axiangement intended for incorporation in the receiving section of a high-definition television picture transmission system.

Such a system includes, in its transmission section, a stage for transmitting coded information components which correspond to the said pictures and are transmitted via an analog channel. This channel has a limited passband composed with the passband which would require the transmission of all the high-definition information components. The transmission via this channel, which is a compatible channel since it allows the transmission of television signals of the normal current standard (625 lines, 50 Hz, 2 1) consequently involves a reducing, or 25 compression processing, of the quantity of information components to be transmitted, and this processing is effected with, for example, the aid of an encoding arrangement of the type described in the above-cited document.

The decoding device described in this previous application basically includes first of all three processing branches for the information components transmitted, and Fig, 1, taken from said document, shows these three branches, which in a general manner are

L

PHF 89.607 2 26-10-1990 denoted by the reference numerals 101 to 103.

The branch 101 comprises arranged one after the other, a dynamic interpolation circuit 111 (for inserting zeros which are to be re-established after transmission via the analog channel 10, because of the sub-sampling which has been effected before this transmission), a multiplexer 112 receiving motion information components originating from a so-called digitally-assisting TV channel 20, and a spatial postfiltering circuit 114 which supplies a picture denoted by 1250 1, 50 Hz, 2 1, 1440 picture elements/line.

The branch 102 comprises, arranged one after the other, a dynamic interpolation circuit 121, a delay circuit 122, an adder 123 for adding together the outputs of the circuits 121 and 122, a spatial postfiltering circuit 124, a picture recovering circuit formed by two series- .arranged memories 125 and 126 receiving the motion information 15 components transmitted via the channel 20, and an adder 127 and a chan-eover switch 128, which on the one hand receives the output from the o memory 125 and on the other hand the output of the adder 127 and which also supplies a picture denoted by 1250 1, 50 Hz, 2 1, 1440 picture element/line.

The branch 103 comprises, arranged one after the other, a dynamic interpolation circuit 131, a multiplexer 132 which also receives ri motion information components originating from the channel 20, a temporal filter 135, a spatial filter 136, a delay circuit 137, and a e change-over switch 138 which alternately receives the output of this delay circuit and the output of the filter 136 for supplying also a picture denoted by 1250 1, 50 Hz, 2 1, 1440 picture element/line.

•The outputs of the branches 101, 102, 103 are applied to the respective inputs 141, 142, 143 of a switching circuit 140 which has for its object to select, as a function of a decision signal also 30 transmitted by the digitally-assisting channel 20, that output branch that is suitable and finally to supply the signals constituting the high-definition pictures to be reconstructed, In the foregoing, it was stated that the original pictures, as they are of the high-definition type, must have been compressed for transmission via the analog channel. In the case described in the cited document, this compression has been effected, at transmission, in a coding arrangement which comprises three processing

L

PHF 89.607 3 26-10-1990 branches which are arranged in parallel and each receive the sequence of original high-definition pictures, a circuit for taking the decision about the transmission rate, which produces from the original pictures and pictures processed by the said branches a decision signal which is applied towards the digitally-assisting channel, and a switching circuit for switching the outputs of the branches in accordance with the output signal of the decision circuit, this coding arrangement being characterized: in that the consecutive original pictures being defined by their order 2k-1, 2 2k, 2k+1, etc... in the said sequence, the coding arrangement also includes a motion estimation stage for supplying information components about the motion of blocks forming the pictures of a predetermined parity, for example of the order 2k+1, relative to the corresponding blocks of the pictures of the opposite parity, which 15 here are of the order 2k and 2k+2, surrounding them; in that the branches, which supply three compressed *picture sequences containing the same number of samples to be transmitted at the field frequency, themselves each comprise a separate spatial filter; and in that the decision taking circuit comprises, arranged in parallel, three paths for calculating the distortion between the original pictury and the three respective processed pictures available downstream of the first, second and third spatial filters of O6 II the three branches, and a circuit for comparing the three distortions and to select the index of the branch corresponding to the weakest of these distortions, the second of these three calculating paths receiving the motion information components relating to each picture block with a view to a recovery of an approximation of pictures of a predetermined parity from the two pictures of the opposite parity surrounding each of 30 them.

Using the structure of the coding device thus defined, the original high-definition, pictures which here comprise 1152 lines of 1440 picture elements divided spatially into blocks of 16 lines of 16 picture elements, are transmitted via the analog channel at a temporal rate which varies in dependence on the motion contained in each block.

These three possible transmission rates of the picture blocks are here as follows: PHF 89.607 4 26-10-1990 the 20 milliseconds (20 ms) rate, in accordance with which the information components corresponding to a picture are transmitted in one single field, at the field frequency equal to 50 Hz; the 40 milliseconds (40 ms) rate, in accordance with which the information components are transmitted in two consecutive fields, at a twice lower frequency (25 Hz); the 80 milliseconds (80 ms) rate, in accordance with which the information components are transmitted in four consecutive fields, at a four times lower frequency (12.5 Hz).

So as to be compatible with the MAC standard intended here to ensure their transmission, the pictures at the input of the analog channels comprise 576 lines 1152/2) of 720 samples 1440/2) and the two fields composing these pictures then comprise 288 lines of 720 picture elements each. The actually transmitted fields will 15 then be regrouped in periods of 80 ms, that is to say in sequences of four fields T 1

T

2

T

3

T

4 which are the transmitted and received fields and consequently constitute the input fields of the decoding device described hereinafter.

S Figs. 2 to 4 shows, in accordance with each of the three transmission rates, the positions of the samples in the block to be transmitted and the field number assinged to them to recover them during their transmission. Put more precisely, in the Figs. 2a to 2c which 0* a relate to the 20 ms rate, Fig. 2a shows in a general manner the position of the samples to be transmitted at 50 Hz depending on whether they o* 0 belong to the transmitted field T 1 and T 3 (samples represented by Data@ crosses) or T2 and T 4 (samples represented by circles). In the Figs. 2a to 2c and the subsequent Figures (3a to 3c, 4a to 4b) the 0 points indicate the missing samples of a high-definition picture block S: shown. Figs. 2b and 2c show in a specific manner for this same picture 30 block the samples which were transmitted via the fields Ti and T 2 (Fig. 2b) and the fields T 3 and T 4 (Fig. 2c), respectively, the samples being referenced using the corresponding field index 1, 2, 3 or 4.

Similarly, Fig. 3a shows in a general manner the position of the samples (in a twice greater number relative to the preceding case, and to be transmitted at 25 Hz, with a twice longer time interval) depending on whether they belong to the transmitted fields PHF 89.607 26-10-1990 T2 and T 4 (circles) or T 1 and T 3 (in which case crosses should replace the circles), and Figs. 3b and 3c show in a specific manner for the same block, the samples transmitted by the fields T 1 and T 2 (Fig. 3b) and by the fields T 3 and T 4 (Fig. 3c).

Finally, Fig. 4a shows in a general manner the position of the samples (in a four times greater number than the number used in the case of the transmission at 50 Hz, and to be transmitted at 12.5 Hz, with a four times longer time interval) and Fig. 4b shows in a specific manner for the same block, the samples transmitted by the fields T 1

T

2

T

3 and T 4 At the output of this decoding arrangement, there correspond to the transmitted fields T 1 to T 4 which are received sequentially at the input of the decoding arrangement, four decoded fields, denoted D 1

D

2

D

3

D

4 Each of these decoded fields 15 can, of course, contain picture blocks corresponding to any of the possible transmission rates (20, 40 or 80 ms), since the encoding at the transmission end provides, a block-wise switching at the output of the processing branches corresponding to each transmission rate. These nonsub-sampled blocked will be denoted tn(20), tn( 40 tn( 8 0), according to the 20, 40 or 80 ms rate at which they correspond and by denoting the field index n. Each transmitted field Tn that generally contains information components about three rates 20, 40 and 80 ms, which will be denoted by Tn(20), Tn( 40 These designations having been defined, the decoded fields are obtained from the transmitted information components in the following manner: decoding the blocks t 1 (20) is obtained from the transmitted informations T 1 and similarly the decoding of the blocks t 2 t 3 t 4 is obtained from the transmitted 30 information components T 2

T

3

T

4 respectively.

decoding the blocks ti(40) is obtained from the transmitted information components T 1 (40) and T 2 (40) and decoding the blocks t 3 (40) is obtained from the transmitted information components T 3 (40) and T 4 The blocks relating to the decoded fields D 2 and D4, for the 40 ms rate, have actually not been transmitted, but, in contrast thereto, for each missing block, the corresponding motion information (or displacement vector) has PHF 89.607 26-10-1990 0 S. 0 So S S

S..

S

9 0 P been transmitted: for each block of the second field the displacement vector 2 for each block of the fourth field the displacement vector 4 Decoding blocks, in this case at the 40 ms rate, is then, as described above, obtained, for the second and fourth non-transmitted field, by means of a motion-compensated temporal interpolation. The principle of this motion compensation operation is to take the half-sum of adjacent transmitted fields in the estimated direction of motion between them with the aid of the displacement vectors. Put more precisely, by using the preceding and subsequent field blocks as well as the corresponding displacement vectors, this operation can be written: t 2 (40) 1/2 ti(40) displaced by the vector -V 2 +1/2 t 3 (40) displaced by the vector +2 t 4 (40) 1/2 t 3 (40) displaced by the vector -V 4 +1/2 t 5 (40) displaced by the vector +V 4 decoding the blocks t(80), t 2 t 3 t 4 (80) is obtained from the transmitted information components

T

1

T

2

T

3 (8 T).

A basic circuit diagram, shown in Fig. 5 shows these operations in a block diagram: the sub-sampled data T Tn( 4 transmitted at the respective rates of 20, 40, 80 ms are applied to the corresponding spatial interpolation filters FS(20), respectively, intended to recover the samples which are missing because of the sub-sampling operation, this interpolation at a rate appropriate for each transmission rate results in the blocks t 1 t 2 t 3 t 4 (20) being available at the output of the filter FS( 2 blocks t 2 t 3 t 4 (80) at the output of the filter 30 FS(80), and at the output of the filter FS(40), on the one hand the blocks t 1 t 3 (40) which were not temporaly interpolated, on the other hand blocks t 2 t 4 (40) which have been submitted to the motion-compensated temporal interpolation in a circuit here denoted

FIT;

a switching circuit S receiver in parallel the interpolated or non-interpolated blocks the blocks tn( 2 0) and the blocks tn(80), and selects those blocks which correspond to S S 00 5

S

PHF 89,607 26-10-1990 the transmission rate according to the output signal of the decision circuit transmitted via the digitally-assisting channel The principles described so far have however disadvantage, as is shown in rig. 6, when operations are effected at the edge of the picture block, by reason of what is commonly denoted the specture H of the filters, Filtering at the edge of a block B c (for a filtered point DA, for example) often implies, actually, that data must be available at the extei'ior of this considered block Bc here in a block iV, These exterior data may have been transmitted at the same rate as those of the block considered, but it is also possible that they were transmitted at a different rate, and, in the latter case have not been sampled in accordance with a sampling pattern compatible with the said filtering, This situation is particularly annoying for the second processing path which recovers the transmitted information, at 15 the transmission rate of 40 ms, as the motion compensation procedure used for the temporal interpolation of the non-transmitted blocks may reject the point DA outside the block B v The non-prepublished French Parent Application no, 8913091 has obviated this drawback, which becomes apparent at the edge of the block, by proposing a technical solution by means of which it is possible to effect the filtering operation even in this limit situatiot, This solution is made operative in three different *to embodiments of the decoding arrangement, a.o In the first embodiment thus described, the television signal decoding arrangement basically includes: six series-arranged field stosres, whose inputs and outputs supply seven consecutive fields T4k+1 to T4k+7 which are transmitted via the analog channel at the field frequency; a switching circuit which receives at seven 30 inputs the respective seven consecutive fields T4k+1 to T4k+7; a first decoding path which receives the fields T4k+1, T4k+2, T4k+3 or the fields T4k+1, T4k+3, T4k+4 and which comprises, arranged in series, a first pattexn recovery circuit operating at the second rate, a first spatial interpolation filter, and a first motion compensation circuit; a second decoding path which receives the fields T4k+1, T4k+ 3

T

4 k+4 or the fields T4k+5, T4k+6, T4k+7 and PHF 89.607 8 26-10-1990 which comprises, arranged in series, a second pattern recovery circuit operating at the second rate, a second spatial interpolation filter, and a second motion compensation circuit, the two motion compensation circuits being intended to act simultaneously and only on one field out of two; an adder for adding together the outputs of the first and second decoding paths; a third decoding path which receives the fields T4k+1 to T4k+ 4 and which includes, arranged in series, a pattern recovery circuit operating at the first rate and a third spatial interpolation filter; a fourth decoding path 4hich receives the fields T4k+1 to T4k+4 and which comprises, arranged in series, a pattern recovery circuit operating at the third rate and a fourth spatial 15 inteirolation filter; to enable the final determination of the decoded 16 fields D4k+1 to D4k+4 "orresponding to the transmitted coded fields 0 T4k+1 to T4k+4, change-over means for selecting depending on the fir"d to be decoded, one of the five outputs constituted by the outputs the four decoding paths and the output of the adder.

In a second embodiment which utilizes the same solution but at a lower cost because of the simplification of the circuits, the television signal decoding arrangement basically includes: six series-arranged field memories, whose inputs and outputs supply seven consecutive fields T4k+1 to T4k+7 transmitted Svia the analog channel at the field frequency; a switching circuit which receives a, seven inputs the seven consecutive fields T4k1 to T4.+; a first decoding path which receives three fields 30 from the input fields of the switching circuit and which comprises, arranged in series, a first pattern recovery circuit operating at the second rate, a first spatial interpolation filter and a delay circuit, the first path supplying information components without motion compensation; at the output of the first spatial interpolation filter, a second decoding path comprising, arranged in series, a motion compensation circuit, an auxiliary memory, and an adder for adding PHF 89.607 26-10-1990 together the outputs of the motion compensation circuit and the auxiliary memory, the first and second decoding paths being followed by a change-over switch for selecting the output of the first decoding path or the output of the second decoding path depending on the field to be decoded; a third decoding path which receives the fields T4k+1 t' T4k+ 4 and which comprises, arranged in series, a pattern recovery circuit operating at the first rate and a second spatial interpolation filter; a fourth decoding path which receives the fields T4k+1 to T4k+4 and which comprises, arranged in series, a pattern recovery circuit operating at the third rate and a third spatial interpolation ilter; to enable the final determination of the decoded 15 fields D4k+1 tu

T

4 k+ 4 corresponding to the transmitted encoded fields T4k+1 to T 4 k+4 change-over means for selecting, depending on the field to be decoded, either the output of the change-over switch which selects the output of the first or the second decoding path, or the output of the third decoding path, or the output of the fourth decoding path.

In a third embodiment, which constitutes the best embodiment of the said solution, and in which a new simplification of .90 the circuits leads to a still further reduction of the manufacturing cost, the decoding arrangement basically includest six field stores divided on the one hand into two input memories and on the other hand into four intermediate memories incorporated in an intermediate storage and switching element; the intermediate storage and switching element; B. a first decoding path which receives three 30 fields from among the fields available in the intermediate storage and switching element, and which comprises, arranged in series, a first pattern recovery circuit operating at the second rate, a first spatial interpolation filter and a delay circuit, the first path supplying information components without motion compensation; at the output of the first spatial interpolation filter, a second decoding path comprising, arranged in series, a motion compensation circuit and an adder whose first input is connected to the PHF 89.107 26-10-1990 output of the motion compensatj.- circuit and the second input to an output of the intermediate storage and switching element, the first and second decoding paths being followed by a change-over switch selecting the output of the first decoding path or the output of the second decoding path depending on the field being decoded; a third decoding path hich receives the fields T4k+1 to T4k+4 and which comprises, arranged in series, a pattern recovery circuit operating at the first rate and a second spatial interpolation filter; a fourth decoding path which receives the fields T4k+1 to T4k+4 and which comprises, arranged in series, a pattern recovery circuit operating at the third rate and a third spatial interpolation filter; to enable the final determination of the decoded 15 fields D4k+1 to D 4 k+ 4 corresponding to the transmitted coded fields T4k+1 to T4k+4, change-over means for selecting depending on the Sfield to be decoded, either the output of the change-over switch selecting the output of the first or of the second decoding path, or the output of the third decoding path, or the output of the fourth decoding path.

To make these embodiments of the decoding arrangement operative, it is necessary, as has been described in the foregoing, to have the possibility to effect, before interpolation, a Edmpling pattern "recovery at 40 ms, and that whatever the type of the block By (sea Fig. 6) next to the considered block BC. For this recovery, in all the possible configurations, one proceeds in the following manner in connection with Figs. 7 and 8 (which show portions of the picture pattern showing the mode of reconstruction of the sampling pattern at ms inside a picture bZod;k 80 ms and inside a picture block 20 ms) and 30 with Figs. 9a to 9d (Whic shoi thf decoding diagrams of four consecutive fields, respectively) and Fig. 9e (which recapilutates in an identical diagram the decoding operations with respect to these four fields).

To recover the 40 ms pattern inside a 80 ms block (denoted M40 in Fig. an interpolation of the data &t 80 ms

(T

1 (80) and T 3 respectively, transferred by the fields Tj and T3. In Fig. 7 which shows a portion of the picture arranged in a PHF 89.607 11 26-10-1990 grid-like pattern, these transmitted data TI(80) and T 3 (80) are represented by a circle, and the points of the 40 ms patternby a cross.

It will be seen that the data T 1 (80) and T 3 (80) provide directly only half the points of the 40 ms pattern, along only one line out of two (in the csc- illustrated in Fig. 1, along the first and third lines, where the crosses overlap the circlez). The missing points (points of the type C, represented here by a cross, on the second line) are obtained by a horizontal interpolation, in accordance with an expression of the type C A B wherein A and B are 80 ms data (circles) surrounding the missing points (crosses).

To recover the 40 ms pattern (which again is denoted in Fig. f) inside a 20 ms block, this time an interpolation of the data transmitted by the field T 3 in the present case, is employed.

The points of the pattern M40, represented in Fig. 8 by a cross, are 15 then obtained in the following manner.

A given directly by T 3 data transmitted and an represented in Fig. 8 by a circle.

E A B F C D G C D E, F, G being the missing points in the 40 ms pattern to be recovered.

To recover the 40 ms pattern within a 40 ms block, the necessary data are of course available, by reason of the transmission effected. Finally, to recover the 40 ms pattern at the junction of two blocks corresponding to the different transmission rates, the missing ~points are, as in the foregoing, obtained by a horizontal interpolation of the type A bB cd wherein A is the point of the pattern to be recovered, B and C are the points of the transmitted data nearest to A, o and b and c are weighting coefficients corresponding to the respective 30 positions of the points B and C relative to a point A, on the same horizontal line.

The following Table 1 summarizes for each decoded field DI, D 2

D

4 the transmitteA data necessary for the recovery of the 40 ms pattern: -1 PHF 89.607 26-10-1990 Table 1 T, (80),

D

1 T 1 (40)

T

3 T 1 (80)

D

2 Ti (40),

T

3 T 1 (80),

D

3 Ti (40),

T

3 T 1 (80),

D

4

T

3 (40),

T

3 (20),

T

3

T

2

T

3

T

2 (40), T 3 (40)t TOO4)

T

3

T

3

S.

C C

**CC

C.

C

CC.

CCC.

C

CC S

C.

C U *5S C

BC

C C

T

3

T

4 (40),

T

7

T

5

T

6 In the foregoing, mention was moreover made (in connection with Fig. 5) of the existence of the interpolation filters Fs(2O) and Fs(8O). The following Table 2 summarizes, for each decoded field Dto D 4 the transmiitted data necessary for the filtering operating effected by F 5 0 S eC~' Table Z

D

2 034

T

1

T

2

T

3 TOO8)

T

1

T

2 (80)1 T 3 (80)1 TOOB)

T

2

T

3 TOO8)

T

1

T

2

T

3 TOO8) and similarly table 3 summarizes for each decoded field D, to D 4 the transmitted data necessary for the filtering operation effected by Fs(2O).- PHF 89.607 26-10-1990 Table 3 D T 1

D

2 T2(20)

D

3

T

3 04 T 4 From the data given by these Tables, it can be derived that the field D1 is obtained in accordance with the following decoding scheme, shown in Fig. 9a, wherein the following functions appear: recovering the 40 ms pattern, designated RM40, from the transmitted fields Ti, T2 T 3 (see Table 1) and in accordance with S 15 the indications of Fig. 7 or Fig. 8 as described hereinbefore; spatial interpolation, effected by a spatial S* interpolation filter of the type FS(40) as mentioned in the foregoing, from the recovered 40 ms pattern, the interpolation resulting in the availability of the decoded blocks recacvery of the 20 ms and 80 ms patterns designated and RM80, from the transmitted fields TI, T 2

T

3

T

4 spatial interpolations denoted 1S20 and IS80 and effected by the above-mentioned filters FS(20) and FS(80), from the 20 ms and 80 ms patterns, to have the decoded blocks t 1 (20) and t 1 (80) available; selection of the output blocks t 1 t 1 t(80) of the interpolation filters FS(20), FS( 4 FS(80), each block t 1 (20) or t 1 (40) or ti(80) being selected in accordance with the indication supplied by the outiut signal of the decision circuit, 30 transmitted via the digitally assisting channel 20, the selection having for its result that finally there are available different consecutive blocks of the field to be decoded, and consequently of the decoded field itself, DI in the case illustrated by this Fig. 9a.

Similarly, the field D 2 is obtained in accordance with a similar decoding scheme, represented in Fig. 9b and in which this time the following functions appear (the functions identical to the preceding functions are given the same references and are indicated VHE 89.607 14 26-10-1990 herebelow): recovery of the pattern RMI40 (id6Dtical function); spatial interpolation by filter F,( 4 0) (identical function) which makes the blocks tj(40) available; recovery of the pattern RM40 from the transmitted fields T 1

T

3

T

4 and spatial interpolation equally effected by a filter FS(40), these two operations this time making the blocks t 3 (40) available; -recovering the patterns RM20 and RMBO (identical functions) and spatial interpolations by filters FS(20) and Fs( 8

O)

(identical functions) which make the blocks t 2 (20) and t 2 respectively, available; motion compensation, denoted CM440 and taking the blocks t 1 (40) and t 3 (40) corresponding to the original transmitted fields, as well as their neighboring blocks to supply, from these bl'ncks and the neighboring blocks and taking the motion information components transmitted by the digitally assisting channel 20 into account, the see a bl~ocks t 2 (40) corresponding to the original non-transmitted fields, 6 goe the compensation consisting in these circumstances in taking, in an adder A provided at the output of the two memories M which receive the tran~smitted motion information components V with a view to allowing a goes shift by V, the half-sum of the blocks tj(40) and t 3 taking account of the motion occurring between the fields to which these blocks correspond; selecting (identical function) from the compensated blocks t 2 as well as from the blocks t 2 (20) or t 2 supplied as previously, depending on the output signal of the decision circuit, to have ultimately the decoded field D 2 available, The field D 3 is obtained in accordance with a decoding *:ouoo 30 schemie ,'denticA to that by means of which it was possible to obtain tXhe field 0 1 as is shown in Fig. 9c, in which the only differences with respect to Fig. 9a are the following points: the recovery of the pattern RM440 is this time effected on the basis of the transmitted fields TI, Ti31 TO the output blocks of the interpolation filters

FS(

2

FS(

4 FS(BO) are now denoted L 3 t 3 t 3 PHF 89.607 15 26-10-1990 Finally the field D4is obtained in accordance with a decoding scheme identical to that by means of which it was possible to obtain the field 02, but for one exception. Actually as is shown in the corresponding Figure 9d, the transmitted fields employed for the recoveries of the pattern RM40 are the following: T 1

T

3

T

4 for the blocks t 3 (40) as in the preceding, and T 5

T

6

T

7 for the blocks t 5 respectively. In fact in this fourth decoding case resulting in the decoded field D 4 not only the total of four transmitted fields T, to T 4 must be used, but also the following total nf four new transmitted fields T 5

T

6 1 T 7 1 Ts must be involved in this decoding operation.

Finally, it is possible to group in one same scheme the decoding operations of Figs. 9a to 9d which results in the combined '~*scheme of Fig. 9e, whose structure will become obvious from the superposition of the four Figs. 9a to 9d. It will be noted that, to effect these coding operations, use must be made of data belonging to C...e -be a seven transmitted fields T 1

T

2 1 T 3 1 TV, T 5 1 T 6 f T 7 0(Tkl oT% in the general case).

"00 To obtain these fields T, to T 7 six field stores must be provided. Fig. 10 shows the first embodiment of the decoding arrangement described hereinbefore. This arrangement first of all comprises six field stores 201 to 206, whose six outputs supply, in the case in which the field D4 is decoded, the respective transmitted fields T, to T 6 and at whose six inputs then the respective transmitted fields T 2 to T 7 are present. A switching circuit 207 provided to take at the opportune moment the inputs and/or outputs of the appropriate store outputs, receives the seven fields T 1 to T 7 via seven appropriate connections connected to those one* of these *CC* inputs or outputs which are suitable.

The fields T 1 1 T 3

T

4 are applied to a first pattern recovery circuit 208 at the second rate (40 ms in the present description), and the fields T 5

T

6

T

7 are applied to a similar second circuit 209. These circuits 208 and 209 are followed by a first and a second spatial interpolation filter 210 and 211# thereafter by a first and a second motion compensation circuit 212 and 213 whose outputs constitute the two inputs of an adder 214. Moreover, the fields T, to T4are applied to two pattern recovery circuits 216 and 217 operating PHF 89.607 26-10-1990 at the first and at the third transmission rate (20 and 80 ms in the present case), and themselves are followed by the spatial interpolation filters 218 and 219, respectively. Thereafter, a change-over switch 215 selects, as a function of the number of the field and the transmission rate of the information present for decoding, either the output of the adder 214, or the output of the filter 218, or the output of the filter 219, the information thus selected corresponding to the respective blocks Y 4 40), tY20) and tY80). For decoding the fields D 2 this change-over switch 215 effects the same selection. In the case in which the fields D 1 or D 3 are decoded, for which the motion compensation does not occur, the change-over switch 215 renders it possible to select directly the outputs of the filters 210 or 211, each of these two outputs being capable of supplying the blocks t 3 (40) or t 5 In the second embodiment shown in Fig. 11 the decoding device still comprises the six field stores 201 to 206 and the third and so fourth decoding paths including the circuits 216 to 219. A switching .0 circuit 307 replaces the switching circuit 207 of Fig, 10. The decoding arrangement furthermore includes a first decoding path without motion compensation, which takes the fields designated D, E, F and includes, arranged in series, a pattern recovery circuit 208 operating at the second rate (40 ins), a spatial interpolation filter 210 and a delay sees **socircuit 211. The fields D, E, F arxe the fields T 1

T

2 V T 3 for decoding the field D 1 the fields T11 T 3 ,T for decoding of the 3, T4 fields D 2 and D 3 and the fields T 5 1 T 6 0 T 7 for decoding of the field D 4 decoding device also includes a second decoding path with motion compensation, which receives the output of the first decoding path and comprises a motion compensation circuit 312, which 30 receives the output of the spatial interpolation filter 210, an auxiliary memory 313, which receives the output of the motion compen~sation circuit 312, an adder 314 for adding together the outputs of the motion compensation circuit 312 and of the auxiliary memory 313, and a change-over switch 316 which selects, depending on the field to be decoded the output of the first decoding path or the output of the second decoding path, that is to say either the output of the delay circuit 211 (this circuit renders it possible to have the same delay as PHF 89.607 26-1C 1990 in the decoding path with motion compensation available) or the output of the adder 314. In its turn a change-over switch 315 allows the selection of either the output of the change-over switch 316 (blocks of the type tn( 4 or the output of the third decoding path (blocks of the type tn( 2 or the output of the fourth decoding path (blocks of the type tn(80)), and consequently to supply finally the decoded fields DI to D 4 The structure of the embodiment of Fig. 11 can be justified in the following manner. It will be noted in the case of Fig.

10, that decoding the blocks t 1 (40) and t 3 (40) requires only one single pattern recovery circuit, a single spatial interpolation filter, and no motion compensation (see also the corresponding Figures 9a and 9c) while decoding the blocks t 2 (40) and t 4 (40) requires two pattern recovery circuits, two spatial interpolation filters and two 15 motion compensation circuits (see the corresponding Figs, 9b and 9d).

Put more precisely, during the decoding of the blocks t 2 there must be calculated: ti(40) compensated for the vector -V t 3 (40) compensated for the vector +V 2 and, during decoding of the blocks t 4 one must calculate in the same manner: -4 t 3 (40) compensated for the vector -V 4 t 5 (40) compensated for the vector +V 4 Then it is established whether it is possible to effect the decoding in the following manner: decoding of the blocks t 1 ,t a pattern recovery at the second rate (40 ms) and a spatial interpolation by means of which it is possible to obtain the information t 1 (40) from the fields T 1

T

2

T

3 present at the 30 input of this path; a motion compensation furnishes the term t 1 compensated for the vector which is then stored.

decoding the blocks t 2 the same circuits as sub ensure the pattern recovery at the second rate (40 ms) and the spatial interpolation, with a view of obtaining the information t 3 (40) from the fields T 1

T

3 PHF 89.607 26-10-1990 the motion compensation renders it possible to obtain the term t 3 (40) compensated for the vector +92, and the half-sum of this term t 3 (40) thus compensated for the vector +12 and the previously stored term (that is to say compensated for the vector -V2) finally results in the information t 2 decoding the blocks t 3 similarly, a pattern recovery at the rate 40 ms and a spatial interpolation render it possible to obtain the information t 3 (40) from the fields T 1

T

3

T

4 the motion compensation renders it possible to obtain the term t 3 compensated for the vector -V4, which is also stored.

decoding the blocks t 4 15 similarly, a pattern recovery at the rate 40 ms and a spatial interpolation render it possible to obtain the information t 5 (40) from the fields T 5

T

6

T

7 now present at the input of the decoding path; the motion compensation renders it possible to obtain the term t 5 (40) compensated for the vector +V4, and the half-sum of this term and the term which was previously stored finally results in the information t 4 change-over means then allow, as previously, to effect the selection of the information components t 1 t 2 t 3 or t 4 This final result is consequently obtained in a decoding arrangement (the arrangement shown in Fig. 11) which relative to the decoding arrangement of Fig. 10, has some fewer circuits, but also an additional memory 313. This additional memory is omitted in the third 30 embodiment described in the foregoing which has the following structure,

S

namely the auxiliary memory 313, four of the six field stores 201 to 206 and the change-over switch 307 are replaced by an intermediate storage and switching elerent, whose characteristics will be described in greater detail hereinafter.

Put more precisely, the decoding arrangement comprises, in accordance with this preferred embodiment shown in Fig. 12, substantially the same elements as the decoding arrangement of Fig. 11, PHF 89.607 26-10-1990 with the exception of the second decoding path, from which the auxiliary memory 313 has been omitted. The field stores 201 to 204 (not shown in Fig. 12, but ultimately represented in Figs. 13 to 15d) are now provided inside an intermediate storage and switching element 407, and on the one hand perform the role if delay lines which have already been assigned to them in Figs. 10 and 11 and on the other hand the role of the memory 313 of Fig. 11. The further elements (first, third and fourth decoding paths, and the change-over switches) are interchanged relative to Fig. 11 and bear the same references.

Fig. 13 is a more detailed representation of the structure of the intermediate storage and switching element 407, whose inputs and outputs have been given the letters A to L. This element 407 has three inputs A, B, C, whi(,4h are connected to the input of the field *q store 206, to the output of this store, and to the output of the field store 205, respectively. The connections between the outputs D to L and the other circuits of the decoding arrangement are defined hereinafter, Ba 4 in connection with the description of the mode of operation of the element 407f which will now be described in detail while taking into consideration a time interval of 100 milliseconds during which five fields succeed each other, and which includes five 20 millisecond stages which are indicated as referen~ced in the respective Figures 14 and to The first stage is an initialisation stage and the four ~further stages allow decoding of the fields Dlt, D 2

,DD,

respectively. These four decoding stages are cyclically reproduced, while the initialisation stage is only realised one single time at the beginning of the decoding operation of a television transmission.

During the initialisation stage, described with reference to Fig. 14, the two first fields T.j and T 2 which correspond to the S 30 first fields to be decoded of the television transmission are shown at the output of the field stores 205 and 206 (see Figs. 12 and 13), and therefore apply tD the inputs C and B of the intermediate element 407.

From these inputs they are sent, via the delay lines L2and Lwhich produce a delaylt I towards the four field stores 201 and 204 where they are entered, the field T, in the stores 201 and 203 and the field Tin the stores 202 and 204, respectively, The following Table (Table 4) collects these inforriation PHF 89.607 26-10-1990 components entered into the intermediate storing element 407 during the first initialisation stage and shows that the information components corresponding to the three rates 80 ms, 40 ms and 20 ms are entered in separate memory zones Z 1 Z2, Z 3 of the memories 201 to 204: Table 4 I Memory zones: I ZI Z 2

Z

3 I Memory 201 I T1R( 8 0) I T1R(40) T1R(20) SMemory 202 1 T2R(80) I T2R(40) I T 2R (20) I I Memory 203 I T1R( 8 0) I T1R(40) T1R(20) I Memory 204 I T2R(80) T2R(40) I T2R(20) 15 The index R indicates that the writing operation is delayed by a period t relative to the information components present at the inputs (B and C here). The presence of the two delay lines L 1 and L2 and this delayed writing operation are justified in the sequel of this description.

During the second stage, the stage in which the field

D

i is decoded and which is described with reference to Fig. 15a, the fields T 2

T

3

T

4 are present at the output of the memory 205, at the output of the memory 206, and at the input of the latter, respectively, (see Figs. 12 and 13) and are applied to the inputs C, B, A of the intermediate storing element 407.

The content of the memory 201 (that is to say the field S! T entered in the preceding stage) is read in synchronism with the

S.

30 fields T 2 and T 3 present at C and B, and these fields TI, T2'

T

3 are sent towards the outputs D, E, F which supply the information components necessary for the 40 ms pattern recovery (and represented in Table 1).

The content of the memories 203 and 202 (that is to say

T

1 and T 2 after the preceding initialisation stage) is read with a delay 't relative to reading of the store 201. As elsewhere the delay produced by the delay lines L 2 and L which receive the respective PHF 89,607 26-10-1990 fields T 3 present at B and field T 4 present at A, is equal to "C the fields T 1

T

2

T

3

T

4 can be simultaneously applied to the respective points K, L, J, I, to feed the pattern recovery circuits at the first and third rates. The information components thus furnished are shown in Tables 3 and 2 respectively.

Simultaneously, the output M of the motion compensation circuit 312 furnishes the terms ti(40) compensated for the vecto:

V

2 which are then sent towards the point G of the intermediate storage element 407, for being entered into the zones Z 2 of the memories 201 to 204. Still simultaneously, the information components and T 2 stored during the preceding stage in the memories 203 and 204, are transferred to the memories 201 and 202.

The following Table (Table 5) collects the information components read during this second decoding stage of the field DI; Table 0Soo a.

*mj j Memory zonest I Z I

Z

2 I Z 3

I

Memory 201 IT 1 (80) i T 1 (40) T 1 (20) I Memory 202 I T2R(80) I T 2 (40) I T2(20) I 466. Memory 203 I TR(80) I TIR(40) TIR(20) I D o Memory 204 I T2R(80) I T2(40) I T29(20) I goes*: while the following Table (Table 6) collects the information components 9 entered during this same second stage: 6 PHF 89,607 22 26-10-1990 Table 6 Memory zones: I Zi Z 2

Z

3

I

I Memory 201 I T 1 R(80) (1/ 4 )t1R( 4 0)V2 I SMemory 202 I T 2 R(80) (1/ 4 )tlR( 4 0)V2 I T2R( 20 I Memory 203 I T3R(80) (1/4)t 1 R(40)V 2 I Memory 204 T 4 R(80) (1/ 4 )tlR( 4 0)V2 As for table 4, the index R in the Tables 5 and 6 indicates the existence of a delay for the performance of the 15 indicated operation.

*During the third stage, which is the stage in which the 055o field D 2 is decoded and which is described with reference to Fig, the content of the memory 201 is read in synchronism with the fields I T 3 and T 4 appearing at the respective points C and B. Then at D, E, F the information components necessar' for the 40 ms pattern recovery in accordance with 7able 1 is obtained.

The content of the field memory 201 is preserved, as it must be utilized during the subsequent stajes, The content of the memories 202 to 204 is read with a delay i relative to the input information components, This reading operation and the output of the delay lite L 2 apply to the points I, J, K, L the following information components: on the one hand the terms ti(40) compensated for the vector #2 and previously stored in the memories M 1 M2, M3,

M

4 these terms then being sent towards the add.r 314, and on the 30 other hand the information components required by the pattern recovery circuits operating at the first and the third rates.

Tables 7 and 8 collect the information components which are respectively read and entered during this third decoding stage of the field D 2 PHF 89.607 26-10-1990 Table 7 Memory zones ZI Z2 Z3 I Msmory 201 I TI(80) (1/4)t1R(40)V2 I Memory 202 T 2

R(

8 0) I (1/ 4 )tlR( 4 0)V2 I T2(20) SMemory 203 I T 3 (80) I (1/ 4 )tIR( 4 0)V2 I Memory 204 I T4R( 8 0) I (1/ 4 )tR( 4 0)V 2 I I Table i 4 S I Memory zones Z 1 I Z 2 I Z 3

I

o•e 0 I Memory 201 T 1 (80) I I I Memory 202 T 2 R(80) I i i Memory 203 T3R(80) T3R(40) T3R( 20 I Memory 204 T3R( 80 T3R( 4 0) I T3R(20) I The index R indicates, as in the preceding, a delay for performing the operation accompanied by this index.

During the fourth stage, in which the field D3 is decoded and is described with reference to Fig, 15c, the contents of the memories 201 and 204 are read in synchronism with the field T 4 now 30 present at the point C. Then, at D, E, F, the information components necessary for the 40 ms pattern recovery are obtained. The contents of the memories 202 and 203 are read with a delay e with respect to the input information components. This reading operation and the outputs of the delay lines L, and L 2 apply to the points I, J, K, L the information components required by the pattern recovery circuit operating at the first and the third rates.

Simultaneously, the motion compensation circuit provides PHF 89.607 26-10-1990 the terms t 3 (40) compensated for the vector V which are then stored in the memories 201 to 204. The information components

T

2

T

3 (80) are preserved in the memoriej 201 to 203.

The Tables 9 and 10 c7llect the information componento which are read and entered, respsctively, during this fourth stage of Jecoding the field D 3 Table Memory zones; I 9 2

Z

3 Memory 201 T 1 I Memory 202 T 2 R(O) I I see* S 15 Memory 203 1 T3R(80) I Tp(40) T 3 o Memory 204 T 3 (80) I 3R3

B.

e S Ta sees 000 I Memory zones 1 X2 23 1 Memory 201 T 1

R(

8 0) I (1/4)t 3 A(40)V 4 0 MEemory 202 T 2 R(80) I (l/ 4 )t3R( 4 0)V4 I SOBS Memory 203 T 3 R(80) I (1/ 4 )t3R( 4 0)V4 Memory 204 T 4 .(80 I (1/ 4 )t3R( 4 )V4 T 4 0 During the fifth stage, the stage in which the field D 4 is decoded which is described with reference to Fig. 15d, this time the fields T 5

T

6 1

T

7 are available at the points C, B, A to allow the %s pattern recovery. In a manner similar to the operations perfnrmed during the third stage, the contents of the memories 201 to 204 are )ead with a delay t relative to the input information components. This reading operation has for its result that, at the points I, J, Kf L,

I

PHF 89.607 25 26-10-1990 there are available on the one hand the terms t 3 (40) compensated for the vector #4 and previously stored in the memories 201 to 204, these terms then heing conveyed towards the adder 314, and on the other hand the information components required for the pattern recovery circuits operating at the first and third rates, Moreover, in a manner which is completely similar to what has been effected during the first initialisation stage, the field T is stored in the memories 201 and 203 and the field T 6 in the memories 202 and 204. Tables 11 and 12 collect th. information components which are read id entered respectively during this fifth stage of decoding the field D 4 Table 11 *9 Memory zones; ZI I Z Z I Memory 201 I T 1 R(80) (1/ 4 )t3R( 4 0)V4 I Memory 202 T 2 R(80) (1/ 4 )t3R(40)V4 Memory 203 I T 3

R(

8 0) 1 (1/ 4 )t3R( 4 0)V4 Memory 204 I T4R( 8 0) (1/4)t 3 R(40)V 4 T4R(20) Table 12 *see I Memory zones: I Z 4 I Z 5 I Z 6 30 I Memory 201 I T5R(80) I TSR(40) I T 5 I Memory 202 I T6R(80) T6R( 4 0) I T6R(20) Memory 203 T5R(80) I T5R( 4 0) T5R(20) I Memory 204 T 6 R(80) I T6R(40) I T6R( 20

I

One can now, as ainounced in the foregoing, justify the presence of two delay lines L

I

and L 2 and the shift by a delay value PHF 89.607 26-10-1990 of writing the memory. Referring to Fig. 12, the value e corresponds to the sum of the delays caused by the recovery of the 40 ms pattern (circuit 208) of the spatial interpolation (circuit 210) and of the motion compensation (circuit 312). This valuel' also corresponds to the temporal shift between the outputs D, E, F and I, J, K, L of the element 407, as well as to the temporal shift between its output H and its outputs D, E, F. A study of the Figs. 14 and 15a to 15d and Tables to 12 also learns that the delays produced by the delay lines LI and

L

2 and the read and write shifts of the memories 201 to 204 result in a correct shift between the outputs D, E, F and the outputs H, I, J, K,

L.

In Fig. 13, the change-over switches denoted Ci, C 2

C

3 controlled at the field frequency and provided in the intermediate storage and switching element 407 ensure, as does also the multiplexer 15 MUX, at the appropriate instants, the correct switching of the received fields circulating through this element. These change-over switches, shown distinctly in the Figure might alternatively be combined in one single change-over circuit ensuring in a similar manner the appropriate switching between the intermediate stores 201 to 204, the delay lines

L

2 and the outputs D, E, F, H, I; J, L of the element 407.

To resume the preceding description, the decoding arrangement consequently comprise whatever the three embodiments proposed in the non-prepublished French Patent Application No. 8913091 mentioned hereinbefore, the following sub-assemblies: field stores, for storing compatible interlaced input pictures (625 lines, 50 Hz; 2 1) at a rate of 13.5 Mbits/second; recovery circuits for recovering three types of sampling patterns (rates 20, 40 and 80 milliseconds) corresponding to the Figs. 2a, 3a, 4a, respectiv ly, utilizing in an appropriate manner 30 the data stored in the field stores; spatial filtering circuits for the interpolation of the missing samples of these sampling patterns; motion compensation circuits utilized for the recovery of the even fields T 2 and T 4 processed in the milliseconds path, this compensation being realized in accordance with the prir.-ple already mentioned of the half-sum of the adjacent fields

(T

1 and T 3 for T21 T 3 and T 5 for T 4 ete in the PHF 89.607 26-10-1990 direction of the motion esti .ated between the fields by means of the displacement vectors; a change-over sub-assembly for selecting, as a function of the decision signal transmitted by the digitally assisting TV channel DATV, one of the signals originating from the 20, 40, millisecond paths.

Putting the functions thus defined into effect can be expressed in a schematic manner in Fig, 16. The decoding arrangement shown there comprises to that effect: a storage sub-assembly 510 containing the field stores and receiving the transmitted data, in this case at a frequency of 13.5 MHz; a pattern recovery sub-assembly 520, which includes a S* 20 ms pattern recovery circuit 521, a 40 ms pattern recovery circuit 522 oe* 15 and 523, and a 80 ms pattern recovery circuit 524, each of the circuits of this sub-assembly being connected to appropriate memories of the subassembly 510; r a spatial filtering s4- assembly 530, which includes filtering circuits 531 to 534 arranged at the outputs of the respective pattern recovery circuits 521 to 524; a motion compensation sub-assembly 540, comprising two memories 542 and 543, which are addressed by the displacement vectors transmitted via the digitally assisting TV channel 20, and an adder 544 for adding the outputs of these memories together; a change-over sub-assembly 550 here intended to select either the output of the filtering circuit 531 of the 20 ms path, S or the output of the filtering circuit 534 of the 80 ms path, or the output of the filtering circuit 532, or the output of the adder 544, the change-over sub-assembly comprising to that effect a change-over switch 551, which operates at a frequency of 25 Hz, and a change-over switch 552 which functions at a frequency of 54 Hz.

When the field to be decoded is the first or the third field (field obtained at the output of the change-over switch 552 D

I

or D 3 the circuits utilized for the recovery of D0 and D 3 are respectively, at the output of the storage sub-assembly 510: the circuits 521 and 531 of the 20 ms path; the circuits 524 and 534 of thO 80 ms path; PHF 89.607 28 15/04/93 the circuits 522, 532, of the 40ms path without motion compensation, followed by the change-over switch 551.

In the case of a recovery of an even field D 2 or D 4 the circuit utilized always includes the circuits 521, 531 of the 20ms path and the circuit 524, 534 of the 80ms path, but the path is this time with motion compensation and employs the two branches of this path namely: the circuits 522, 532 and the memory 542; the circuits 523, 533 and the memory 543; the adder 544, followed by the change-over switch 551.

In the foregoing it was found that, on the one hand, from the point of view of bulk ot the arrangement, the decoding of the field D 4 was pazticularly expensive as regards circuits, since it involves the necessity of using two motion S compensated interpolations to have t 4 (40) available, and data belonging to seven fields to recover the 40 ms pattern, in the third and fifth fields, and on the othe rhand that the compensation suo-assembly and one of the filtering circuits 0 0 (here the circuit 533) were only used for the recovery of one S: field out of every two fields, to obtain the decoded fields D 2 and D 4 The invention has for its object to provide a decoding S arrangement in which a more efficient uqe is made of the circv ts during the recovery, the numt of circuits and their complexity being moreover significantly reduced, and these S measures being adopted without any change in the quality of S the pictures, To this effect the invention relates to the decoding arrangement described in the *pening paragraph of this 3 specification characterized in that it comprises: a storage and switching sub-assembly including field memories arranged in series and being coupled to receive block-ilse said signals and to delay them before a selective switching to decoding paths of said decoding arrangement; a pattern recovery and filtering sub-assembly for effecting the recovery of the fields of the original pictures, NR2% in picture blocks and as a function of said selected transmission.:rate,...and* q®m*prisin .rst*. seconj. and third 0 lu o* 0 S 0.

so* g g o 5 OSSS 55 5555 55 555* 555 555* PHF 89.607 15/04/93 decoding paths coupled to receive f ields available in said storage sub-assembly, each C. C OS OS OS S S 0 0S 0 S 0 000 S 0 0 *05 S 0 S See ego S. S 0 0 0 0050 00 *560 OS e 0 0 0 S0 so0

S

00 0 5 0 APHF 89.607 29 26-10-1990 decoding path comprising a spatial interpolation filter; a motion compensation sub-assembly coupled to receive said motion information components for, alternately, temporarily storing a motion compensation signal during the recovery of fields of a predetermined parity, or participating, using said motion compensation signal, in the recovery of fields of the opposite parity, said subassembly comprising a fourth decoding path, with motion compensation coupled to an output of said storage sub-assembly and comprising a spatial interpolation filter, a memory which is Fadressed by said motion compensation information components, and, at the output of this memory, two parallel arranged branches, one of which comprises a change-ovex circuit and the other branch comptises a connecting link to a first input of an adde,.,, the spatial interpolation filter of said second decoding path being coupled to a second input of said adder; and a change-'over switch for seleci- in accordance 4 with the transmission rate corresponding to each block, an output of the 4000V first path, an output of the second path or an output of the third path.

.4With the structure of 'the arrangement thus proposed, the motion compensation sub-assembly is much 5impler and, moreover, operates in a continuous manner. These results are obtained from the fact that the decoding arrangement anticipates the motion compensation operation by generating a compensated half-signal and storing it temporarily during a field period (in this case 20 ins) in the auxiliary memory stage to add it to the subsequent compensated half signal. Instead of effecting the motion compensation operation at half the field frequency and with an intermittent operation of the motion compensation subassembly, this operation is realized at the field frequency, by consecutive half-compensations which are made complete two-by-two, and *:with a regular functioning of this said sub-assembly.

ease*: 30 on the other hand, since one wants to limit in principle, (for reasons of costs) the number of memories, the compensated halfsignal evaluated by anticipation is sub-,sampled by a factor of 2 (in accordance with ai Une-quincunx structure, which does not degrade the spatial resolution of the pictures in the paths corresponding to the second transmission rate) before being stored in the auxiliary memory stage and is not spatially interpolated again until after its recovery by this stage, previous to its addition to the subsequent compensated PhT! 89.607 30 26-10-1990 half-signal.

Particulars and advantages of the invention will now become more apparent from the followA~nj description, as well as from the accompanying drawings, which are given by way of non-limitative examples and in which, Figs. 1 to 16 referring to prior solutions; Fig. 1 shows an example of a dehcoding arrangement having three spatial-temporal sampling structures adapted to the displacement speeds found in~ the pictures, and to that effect comprising arranged in parallel, three branches for processing transmitted information components to be decoded; Figs, 2 to 4 show, in accordance with that one of the three transmission rates that is associated with the sampling structures, the positions of the samples in the picture blocks to be a 04V transmitted and the field number assigned to them to mark them during .00 their transmission; 5 is a basic circuit diagram intended to illustrate the main operations effected on decoding; Fig. 6 shows at a greatly enlarged stcale a picture block and a portion of the picture blocks surroun~ing it so as to specify tre @see filtering problems at block edges; Figs. 7 and 8 are portions of the patterned picture which show the mode of sampling pattern recovery corresponding to t~he intermediate transmission rate (40 ms in this case), inside a block corresponding to the slowest transmission tate and inside a block corresponding to the fastest transmission rate, respegtively; Figs. 9a to 9d respectively show the decoding schemes of the first, second, third and fourth fields and Fig. 9e recapitulates 30 in a similar scheme the decoding operations relating to these four fields; Figs. 10 to 12 show the three embodiments of the deealing arrangement by means of which it is possible to introduce the presentation of the decoding arrangement according to the invention; Fig. 13 shows in a more detailed manner the structure of the intermediate storage and switching element of Fig. la and Figs. 14 and 15a to 15d illustrate the mode of operation of this element in PHF 89,607 31 26-10-1990 accordance with the opereting stages of the decoding arrangement itself; Fig. 16 shows, in a schematic manner, a view of the total functions put into effect in these embodiments of the previously described decoding arrangement and which does not include the present invention; Fig. 17 is, in a similar manner, a view of the totality of the same functions for the case of a decoding arrangement according to the invention; Figs. 18 to 21 show a detailed embodiment of a decoding arrangement according to the invention, in which the functions described and referenced in Fig. 17 are put into effect, The principle on which the structure of the decoding 15 arrangement according to the invention is based, will be described first, in connection with Fig. 17, to be compared with Fig. 16 to discover the essential differences.

The decoding arrangement of Fig. 17 includes a storage sub-assembly 610, in which from now on not only the presence of field memories as previously, regrouped into a principle memory stage 615, but also the presence of an auxiliary storage stage will be noted, which will be described in greater cs-ail in the sequel of the present description. The decoding arrangement also includes, as in the foregoing, three paths 20 ms, 40 ms, 80 ms, but the 40 ms path is organised differently from the case shown in Fig. 16. The 20 ms and ms paths remain the same, o1 which the first path is composed of the ms pattern recovery circuit 521 and the filtering circuit 531, and the se'o'Ad path is composed of the 80 ms pattern recovery circuit 524 and 'he filtering circuit 534, As previously, the circuits 521 and 524 are 30 incorporated in a pattern recovery sub-assembly 620, and the circuits 531 and 534 in a filtering sub-assembly 530. The 40 ms path now comprises a single pattern recovery circuit 522 and two filtering circuits 532 and 533.

The decoding arrangement is provided, as in the foregoing, with a motion compensation sub-assembly which here is denoted by reference numeral 640 and includes the following elements: a single memory identical to the memory 542 and addressed by the displacement 4 PHF 89.607 32 26-10-1990 vectors transmitted via the channel 20, an adder identical to the adder 544 but whose second input is this time connected to the output of the filtering circuit 533, a sub-sampling circuit 645 arranged at the output of the memory 542 and a change-over circuit like an interruptor 646 provided at the output of this sampling circuit and being controlled at a frequency of 25 Hz. The outpi of this interruptor 646 is applied to the auxiliary storage stage 650, whose output is applied to the filtering circuit 533 of the 40 ms path. The output of the adder 544 is applied, as in the case illustrated in Fig. 16, to a change'*over subassembly which is identical to the sub-assembly 550 and therefore having the same reference numeral.

Thus, when the field to be decoded is the first or the third field, and one wants to obtain the recovery of the decoded fields *go D and D 3 at the output of the change-over switch 552, the circuits euaployed are the same circuits as in the case of Fig. 16, namely; th cicis52,51ofte2 m ah the circuits 521, 531 of the 20 ms path; o-the circuits 522, 534 of the 80 ms path; iecl followed by the change-over switch 551 (which it this case is in the position in which it is connected to the output of the filtering circuit 532), the change-over switch 552 effecting, as in the foregoing the selection between the output of the circuit 531 (20 ms path), the output of the circuit 534 (80 ms path) or the output of the change-over switch 551 (40 ms path, without motion compensation). Moreover, the memory 542, which is addressed by the displacement vectors as in the foregoing, permanently stores the output signal of the filtering circuit 532 and thereafter transfers it to the auxiliary storage stage 650 via the subsampling circuit 645 and the interruptor 646, When the field to be decoded is now the second or the :30 third, field, the circuits used are always the circuits 521, 531 and the circuits 524, 534, for the 20 ms and 80 ms paths, restectively. In contrast thereto, the change-over switch 551 is kept in the position (not shown in Fig. 17) in which it is connected to the output of the adder 544. Because of this fact, in these decoding stages the two branches of the 40 ms path are active, that is to say on the one hand the branch which, connected to a first input of the adder 544, includes the patterai recovery circuit 522, the filtering circuit 532 and the PHF 89.607 26-10-1990 memory 542, and on the other hand the branch which, connected to the second input of the adder 544, includes the filtering circuit 533 for filtering signals having passed through the auxiliary storage stage 650.

The foregoing description relates to a basic structure of a decoding arrangement according to the invention, but, obviously, the invention is not limited to such an embodiment. It is more specifically possible to propose an improved version of such an arrangement, in which the auxiliary storage stage is actually formed by two field stores provided within the memory stage 615 principal the decoding arrangemkmnt. The corresponding detailed embodiment will now be described with reference to Fig. 18 and to the similar Figures 19 to 21.

The decoding device of Fig, 18, whose mode of operation will be explained in detail hereinafter, first of all eae 15 comprises an input signal memory sub-assembly 710. This sub-assembly 710, intended to receive the previously encoded and transmitted television signals and to delay them in the appropriate manner before s their selective switching (as a function of the field to be decoded) towards the other circuits of the decoding arrangement, comprises an input series arrangement here formed by three field stores 711, 712, 713, As irdicated in Fig, 18 these three memories are associated with three del.~y circuits 811 to 813 which render it possible to have available, at their output, far a current field Cn+3 at the O input of the decoding arrangement, three preceding fields Cn2 Cn+11 Cm which are separated trora each other by time intervals *0000: having a duration of 20 milliseconda, The decod~inq arrangement of Fig. 18 also includes a pattern recovery and filtering sub-assembly 720. This sub-assembly 720, 0s intenaed to effect the recovery of the fields of the original pictures by the consecutive recovery of the picture blocks and as a function of the transmission rate of the encoded signals, includes a sampling pattern recovery stage 721 followed by a spatial filtering stage 725.

The stage 721 comprises a first, a second and a third pattern recovery ciz;-:uit 722, 723, 724, respectively, arranged for recovering the pattern at first, second and third rates respectively 40, 80 ins), This stage 721 Teceives four consecutive fields supplied by the sub-assembly 710. The stage 725 comprises a first, a PHF 89.607 34 26-10-1990 second and a third circuit 726, 727, 728 for filtering the output signals of the respective circuits 722 to 724. A change-over switch 729 arranged downstream of these three filtering circuits 726 to 728 allows the selection, as a function of the decision signal transmitted by the digitally assisting TV channel 20, that one of the outputs of these filtering circuits that corresponds to the transmission rate selected for the relevant block.

The decoding arrangement of Fig. 18 finally includes a motion compensation sub-assembly 730. This sub-assembly 730 receives the motion information components transmitted via the digitally assisting TV channel 20 and is intended to store in a temporary manner a motion compensation signal or to participate with the aid of this signal, in a recovery of the non-transmitted field with motion compensation, The S. first of the two stages, the temporary storage stage, takes place during 15 the period of time in which the decoding arrangement is busy recovering the decoded transmitted fields, while the second of these two stages, the recovery stage with motion compensation takes place during the period of time in which the decoding arrangement is busy in recovering these non-transmitted fields, The motion compensation sub-assembly 730 comprises, arranged one after the other, a pattern recovery circuit 731 operating at the second rate, a filtering circuit 732 for filtering the output of the circuit 731, a memory 733 receiving the transmitted motion information components, a sub-sampling circuit 734, a change-over circuit 735 including two change-over switches 735a an 3 35b arranged in parallel, and an auxiliary storage stage comprising here the two field tores 711 and 712. The overall duration of the processing operation in the sub-assembly 730 is equal to' and this value is the value of B the delay produced by each of the delay circuits 811 to 813. The two memories 711 and 712 play the role of the auxiliary storage stage 30 m.edioned hereinbefore with reference to Fig. 17, The mode of operation of the decoding arrangement of Fig. 18 will now be described, examining successively the different decoding stages corresponding to the recovery of the different fields, denoted Dn+I, Dn+ 2 Dn+3$ Dn+4. These stages are reproduced periodically, and not more than four of these stages will be described, for example corresponding to the decoding which yields the four decoded fields DI, D 2

D

3

D

4 The description thus obtained can be I PHF 89-607 26-10-1990 generalized.

The first stage described is the stage in which the field Dis recovered, and which will be the same as for the recovery of the frame D 5

D

9 I D etc The references C indicated at the output of the memories designate hereinafter the consecutive transmitted input fields, as received by the decoding arrangement, while the references designate in a similar manner these same input fields but delayed by means of the delay circuits 811 -to 813 associated with the memories 711 to 713 by a period It corresponding to the processing time in the sub-assembly 730, in this first operating stage, in which C 3 is the current field present at the input of the decoding arrangement, the pattern recovery circuits 722, 723, 724 of the stage 721 of the sub- **.assembly 720 apply to the respective filtering circuits 726, 727, 728 of off* the stage 725 of the said sub-asembly three signals obtained by arranging the contents (supplied by the sub-assembly 710) of the field stores 711, 712, 713 in accordance with the sampling patterns 44.: provided for each transmission rate (20, 40, 80 ins) aad shown In the respective Figs. 2a, 3a, 4a (relative to the sub-rates), Put more precisely, the field D 1 to be recovered will be obtained from the samples originating from C 1

C

2 if the transmission rate was ms and from the samples of Cl('ft') C 2

C

3 if o the transmission rate was 80 ins, 1At the output of the filtering circuits 069 726, 727, 728, which allow the re-insertion of the missing samples in the sampling pattern, the change-over switch 729 selects as a function of the decision signal which it receives, that one of these three outputs which is associated with the selected transmission rate. At the output of the change-over switch 729, which Is simultaneously the output of the sub-assembly 720 and the output of the decoding arrangement# the decoded field D, (1250 lines, 1440 picture elements/line) is thus progressively recovered, During this first operating stage, the motion compensation sub-assembly 730 ensures the recovery of a first halfcompensated field in the following manner: 36 by recovering the sampling pattern corresponding to the 40 mns rate, with the aid of the pattern recovery circuit 7.71 recei ving the fields C 2 and C 3 gPHF 89,607 36 26-10-19 (b by spatial filtering with the aid of the filtering circuit 732, which is identical to the filtering circuit 727 and also intended to re-insert missing samples in~to the 40 ms sampling pattern; by half-compensation of the motion with the aid of the memory 733 which receives the motion information components (displacement vectors V) transmitted via the channel 20 and supplies a field D 2 which is called the first half-compensated field, and each sample of which having the coordinates X, originates from the output field of the filtering circuit 732# shifted by taking therefrom the samples respectively; by sub-sampling in line quincunx of the first halfcompensated field thus obtained, this sub-sampling effected by the circuit 734 being intended to modify the rate of the samples of ;*Poo this first half-compensated field before its storage in the auxiliary storage stage formed, as described in the foregoing, by the stores 711 0 e~ and 712 which are temporarily disconnected from the input series C arrangement (711, 811, 712, 812t 713, 813) and connected again in parallel to the output of the circuit 734 with the aid of a position, called the parallel position, of the change-over circuit 735 acting on the input of the stores 711 and 712, between the output of the rJelay circuit 811 and the input of the store 711, and between the output of the delay c,'rcuit 812 and the input of the store 712 (this modification feet 00*0 6 of the connections of the stores 711 and 712 is effected under the 9 control of the decision signal not shown so as not to overcrowd the Figure, but which acts on the change-over circuit 735 exclusively when the decision signal indicates that the 40 ms rate has been selected, and the stores 711 and 712 again contain the samples of the input signals from the instant at which the decision signal, indicating the selection of the 20 ms or 80 ms rate, has given the command to the change-over eggs#: 30 circuit 735 to return to its so-called series position).

The operations occurring during the first decoding step are thus terminated, The second step is the step in which the field D2 Is recovered, which as Indicated in the foregoing will be identical for the recovery of the field D~p D101 D2n+20 etc., In this second operating step, described with reference to Fig, 19 and in which, in the example despribed, C 4 is the current field present at the input of the decoding arrangement, C1 to C 3 the PHF 89.607 26-10-1990 fields present at the output of the $tores 711 to 713 to

C

4 the delayed fields pxe~ent at the input of the said stores, the recovery is this time obtained from samples originating from C 2

C')

f or the 20 ms transmissi on rater f rom C 3 (t t C 4 (re f or the 40 ms rate, and fronm 1

C

2

C

3

C

4 for the 80 ms rate.

Dluring th4a~ setnnd operating step, the motion co~ipensation sub-assembly 730 ensures the recovery of a second halfcompensated field in the following manner: by ecoveria Uie 40 mus Pattern, also with the aid of the pattern recovery circuit 7$l, wh34,h this time receives the fields C, and C 4 Mb by, spaticl fiJ.4er$ as in the foregoing with the aid of the filteriftq circitit 732 which re-inserts the missing samples; by at'-ion half -compepiation with the aid of the memory 733 'dch, this 'timet supplies from the vectors V a field ~aD 2 denoted second half compensated field obtained by taking front the memory the intensitV of the samples X and V and by attributing it to the samples of the coordinates X(; by adding# ir an adder 736 provided at the output of the memory 733, this second halt-oompensated field applied to an input of the said adder and the first halfV-compensated field stored during the preceding step in the auxiliary storage stage, the said first halfa compensated field being applied to the other input of the said adder by the assembly formed. by the pattern recovery circuit 723 and the 4 ~filtering circuit 727f front the samples stored in the stores 711 and 712 during the last 20 milliseconds, and the adder 73G supplying from its output the compensated field D 2 which results from the average of the two half -compensated. fields D 2 and D 2 oe: 30 The change-over switch 729 then selects, as a function of the decision signal indicatingt as in the foregoing, the 20, 40 or ms rate, that one of the three output signals of the filtering circuit 126 (20 ms rate), of the adder 7136 (40 ms rate), or of the filtering circuit 728 (80 ms rate) which i'.orresponds to the indicated rate, and from its output supplies th6 ecdod field D 2 (125 lines, 1440 picture elementolline).

The third stage is the stajg\ in which the field D 3 is PHF 89.607 38 26-10-1990 recovered, which actually is identical to the stage in which the field Dis recovered, C 5 this time being the current field present at the input of the decoding arrangement. This third stage corresponds to Fig'.

in which similarly to what has been described for the first st-,e, a first half-compensated field D 4 is obtained and stored in the auxiliary memory stage and read during the fourth stage, That fouzth stage, the stage in which the field D 4 is recovered, is identical to the stage in which the field D 2 is recovered, C 6 being in this case the current field present at the input of the arrangement. The fourth stage corresponds to Fig. 21, in which similarly to what has been described for the second stage, a second half-compensated field

D

4 is obtained and added to the first half-compensated field

D

4 in the adder 736.

The operation of the decoding arrangement then develops in a sequence of stages in which there is a regular alternation cf identical first stages in which the fields D 1

DD

5 D etc. ar~e recovered providing more specifically the temporary storage of a first half-compensated field, determined to some extent by 0: anticipation, on the one hand and of identical second stages in which the fields D 2 1 D 4

D

6 1 etc... are recovered, providing for the determination of a second half-compensated field and its addition to the previously determined first half-compensated field on too*the other hand. obviously, the adder~ 736 which effects this addition during stages of the second type m-*st, during stages of Lhe first type preceding them, been neutralized by keeping at a zero value, during a sst these stages, the signal present at that input of 'this adder whichi I,s connected to the output of the. memory 733, the other input of the adder receiving in all the cases both durin 'g the first stages and during the second stages, the output from the filtering circuit 727 of the 40 ms branch,

Claims

2. A decoding arrangement as claimed in claim 1, characterized in that the change-over circuit includes an interrupter and in that the storage sub-assembly includes an auxiliary storage stage arranged in series with said interrupter. 3, A decoding arrangement as claimed in claim 1, a characterized in that the change-over circuit comprises two parallel-arranged change-over switches and in that first and second field memories of the storage sub-assembly are each arranged in series with one of the said change-over switches. 4, A decoding arrangement as claimed in any of the claims 1, 2 or 3, characterized in that the change-over circuit is preceded by a sub-sampling circuit sub-sampling by a factor 2, S: 5. A decoding arrangement substantially as described herein with reference to Figures 17 to 21 of the accompanying drawings. Dated this fifteenth day of April 1993. N.V. PHILIPS' GLOEILAMPENFABRIEKEN 422 o 0,000 0 tooo