AU630674B2

AU630674B2 - Watchdog timer circuit

Info

Publication number: AU630674B2
Application number: AU51164/90A
Authority: AU
Inventors: Ronald Christopher Shaw Fox; Frederick Dennis Montano
Original assignee: Alcatel Australia Ltd
Current assignee: Nokia Services Ltd
Priority date: 1989-03-23
Filing date: 1990-03-09
Publication date: 1992-11-05
Anticipated expiration: 2010-03-09
Also published as: AU5116490A

Description

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DRIGIM

COMMONWEALTH OF AUSTRALIA PATENTS ACT 1952-1969 COMPLETE SPECIFICATION FOR THE INVENTION ENTITLED

S

"WATCHDO)G TIMER CIRCUIT" S. S The following statement is a full description of this invention, including the best method of performing it known to us:- I- This invention relates to a circuit arrangement for providing a reset signal to a microprocessor, particularly, though not exclusively, a microprocessor associated with a telephone subset, when the microprocessor becomes latched in an undefined state. This state can be brought about by, for example, electrical interference or an event nconsistent with the normal operation of the microprocessor's software.

Such circuits, generally referred to as watchdog timer circuits, are known and are arranged to reset the microprocessor when the microprocessor fails to provide a service signal at predetermined regular intervals, which would occur when the microprocessor becomes latched. Such timer circuits com- Sprise a dedicated integrated circuit containing a plurality of gates and associated circuits as well as external circuit components.

It is an object of the present invention to provide a watchdog timer circuit in which only some of the gates in the integrated circuit are used for providing the watchdog function, the remaining gates being free to use in other circuits associated with the microprocessor.

0*e It is a further object of the present invention to provide a watchdog timer arrangement for use in a telephone subset, the said timer only functioning when the subset is in certain predetermined modes.

According to a first aspect of the present invention there is provided a method of providing a reset signal to a processor when the processor fails to generate a regular service signal pulse, said method comprising the steps of providing a first gate means an input of which is coupled to the processor's service signal pulse output, a second gate means whose output is coupled to the processor's reset signal input, said second gate means having a first and a second output voltage state respectively depending on whether a first or a second voltage state is present at the input thereof, said first voltage output state representing a reset signal, maintaining said second voltage state at an input of the second gate means with storage capacitor means while ever regular service signals are applied to the input of the first gate means, thereby maintaining a second output voltage state at the output of said second gate means until said regular service pulses cease.

According to a second aspect of the present invention there is provided a circuit arrangement for providing a reset signal to a processor when the processor fails to generate a regular service signal pulse, said arrangement comprising a first gate means an input of which is coupled to the processor's service signal pulse output, a second gate means whose output is coupled to the processor's reset signal input, said second gate means having a first and a second output voltage state respectively depending upon whether a first or a second voltage state is present at an input thereof, said first voltage output state representing a reset signal, a storage capacitor means coupled between the input of said second gate means and a voltage supply rail, and charge cira cult means including time constant means for charging said storage capacitor means and maintaining a charge thereon sufficient to maintain said second voltage state at the input of said second gate means whenever the voltage state at the output of the first gate means represents the presence of a ser- "vice signal at its input.

S In a preferred embodiment of the circuit arrangement of the present invention utilised to reset a microprocessor incorporated in a telephone subset, the first gate means forms part of a flip-flop circuit which is set by the presence of signals from the subset's hook-switch, the microprocessors dial pulse (DP) pin, and a voltage monitor circuit arranged to monitor the microprocessor's power supply, and cleared by the presence of a service pulse from the microprocessor. The flip-flop circuit will only permit the circuit arrangement to provide a reset signal to the microprocessor under certain conditions, viz. on initial power-up, when in the off-hook mode, and when a partially discharged dry cell used to provide power to the microprocessor in the on-hook mode, is replaced by a fully charged dry cell. At all other times the circuit is prevented from transmitting a reset pulse to the microprocessor 3 U_ _iii_ which, during this time, is in a state where it draws minimal current and has no need, nor does it provide service pulses.

In order that the invention may be readily carried into effect, embodiments thereof will now be described in relation to the drawings, in which: Fig. 1 is a schematic circuit of a first embodiment of the present invention.

Fig. 2 is a schematic circuit of a second embodiment of the present invention.

Fig. 3 is a schematic circuit of the present invention adapted for use in IA.. a telephone subset.

Referring to Fig. 1, the circuit comprises a service signal input termi- *see nal 1 coupled to the input of a first inverter gate GI, via a filter arrangement comprising capacitor Cl, diode Dl and resistors Rl and R2. The filter arrangement filters out any DC component which may be present in the service signal from the microprocessor (not shown), and resistor R2 ensures a logical low level at the input of gate GI. The output of gate Gl is coupled serially to a first and seond time constant network. The first time constant network o comprising a capacitor C2 and resistor R3, and a second time constant network comprising the capacitor C2, resistor R3 and resistor R4; capacitor C2 and resistor R3 be'tg common to both networks. Associated with each network is a respective diode. Diode D3 selects the duration of the reset pulse, and diode D2 shunts the relatively high value resistor R4 to provide a charge/discharge circuit for capacitor C2. The junction of capacitor C2 and resistor R3 is coupled to the input of a second inverter gate G2 whose output is coupled to a "Reset Pulse" output terminal 4.

In operation, initially when power is connected to the microprocessor, the microprocessor will require resetting. At this initial stage there is no charge on the plates of capacitor C2, and therefore the voltage state at the input of gate G2 is HIGH causing the voltage state at the output thereof to be LOW. The latter voltage state is recognised by the microprocessor, whose re-.

set pin is coupled to output terminal 4I, as a reset signal and the microprocessor resets. At the samie time, because of -the LOW voltage state at the output of gate G2, diode D3 is rendered conducting and brings into effect the first time constant network in a circuit comprising V voltage rail, capacitor 02, resistor R3, diode D3 to earth (LOW). Capacitor 02 begins to charge and the first time constant network starts to pull the voltage on input of gate G2 down from voltage rail potential towards the negative input threshold voltage of the gate at a rate determined by the values of capacitor 02 and resistor R3. The delay provides time for the power applied to the micro- 1~..processor to reach a magnitude where it can at least recognise and react to a *reset pulse from the watchdog circuit. When the negative input threshold :voltage is eventually reached the output voltage state of gate G2 changes to :HIGH and therefore the reset signal is removed from terminal )4.

Capacitor 02 now begins to discharge relatively slowly through the second time constant network comprising capacitor 02, resistors R3 and R4. The time constant of this network is such that before the positive threshold voltage at the input of gate 2 is reached, a service pulse arrives from the microprocessor. This pulse is filtered by diode Dl and resistor Ri and applied to :*,the input of gate Gi as a positive going pulse. As a result the voltage state at the output of gate G1 changes briefly. During this brief period, diode D2 *0::is rendered conducting and thereby provides a charging circuit for capacitor 02 via resistor R3, diode D2 to the output of gate Gi. Capacitor 02 charges until the brief changed voltage state at the output of gate G1 ceases. Now capacitor 02 again begins to discharge through the second time constant network. This charge and discharge cycle continues as described above while ever service pulses arrive from the microprocessor.

In the event of a latched condition in the microprocessor a service pulse does not arrive, and the voltage at the input of gate G2 rises to the positive threshold which thereupon alters the state of the output of gate 2 to LOW which is, as described above, recognised by the microprocessor as a reset signal.

Referring to Fig. 2, this circuit includes a modified timle constant network comprising capacitor C2, resistor R5 and diode D4 to provide an extra long reset pulse to accommodate power supplies having a very slow power-up time.

In operation, initially when power is connected to the microprocessor, the microprocessor requires resetting. At this initial stage there is no charge on the plates of capacitor C2, and therefore the voltage state at the input of gate G2 is HIGH causing the voltage state at the output thereof to be LOW. The latter voltage state is recognised by the microprocessor. At the same time, because of the LOW voltage state at the output of gate G2 diode D3 is rendered conducting and brings into effect the modified time constant network in a circuit comprising V+ voltage rail, capacitor C2, resistor R5 and diode D3 to earth (LOW). Capacitor C2 begins to charge and the network starts to pull the voltage on the input of gate G2 down from voltage rail potential towards the negative input threshold voltage of the gate at a rate determined by the values of capacitor C2 and resistor R5. The value of resistor R5 is chosen to provide a time constant longer than the power-up time of the power supply.

Referring to Fig. 3, the circuit is similar to that of Fig. 1 except that |i a NAND gate is substituted for the inverter gate Gl and forms part of a flipflop circuit comprising resistors, R7, R8, R9, R10 and Rll and a transistor TR1. A voltage detector means (not shown) monitors the level of voltage on the microprocessor's power supply and extends a signal when this level falls below a predetermined value to alter the state on input 2 of gate GI. The base of transistor TRI is coupled via resistor Rll to the dial pulse (DP) pin of the microprocessor and the collector of transistor TRI is coupled to the hook-switch of the associated telephone subset to detect a change from the onhook mode of the hook-switch to the off-hook mode. This flip-flop circuit arrangement enables the watchdog circuit only under certain circumstances, namely: 1. Initial power-on, that is when power is initially connected to the subset's microprocessor.

2. When the subset is in the off-hook mode.

3. When a voltage dip occurs, that is, when the internal dry cell used to power the microprocessor in the on-hook mode becomes partially discharged and it is subsequently replaced by a fully charged dry cell.

The operation of the initial power-on has already been described in relation to Fig. 1. Thereafter, when the subset is in the on-hook mode, transistor TRI is turned off and since input 2 is HIGH because the voltage detection is detecting normal voltage, the output state of gate GI is LOW disi abling the watchdog circuit. No reset signal is produced at terminal 4 and there is negligible current drain.

When the subset is brought into the off-hook mode a signal is extended from the subset's hook-switch via capacitor C3 to the collector of transistor TR1 for a brief period while capacitor C3 charges through resistor R10. The input 1 of gate GI is pulled to earth (LOW) because diode Dl is reversed biased and neglibible current flows through resistor R7. The output of gate Gl becomes HIGH. This turns on transistor TR1 through resistor R8. Turning on transistor TR1 causes the collector of the transistor to remain LOW (earth) and the flip-flop is placed in its set state, that is the state of its output is HIGH. While the flip-flop is in the set state the watchdog timer starts timing and will cause the microprocessor to reset after a predetermined time interval unless the flip-flop is cleared in the meantime.

When the subset is brought into the off-hook mode, as well as the extension of the signal from the hook-switch to the collector of TR1, the hook switch extends a continuous signal to the DP pin of the microprocessor to activate normal off-hook functions including the generation of a series of pulses at its WD (watchdog) service pin. Since diode Dl is forward biased and 7 I has a lower impedance than resistor R7, the HIGH pulse is extended from the microprocessor service output to input 1 of gate 1 via capacitor Cl.

Capacitor 02 now becomes fully charged.

To maintain the watchdog circuit functioning, resistor RII couples the DP output of the microprocessor to the base of transistor TRI. This causes the flip-flop to set whenever the subset is in the off-hook mode by keeping transistor TRI turned on. The flip-flop is still momentarily cleared by the watchdog service signal from the microprocessor, since as mentioned above, diode Dl has a lower impedance than resistor R7. Since, however, this signal is AC coupled through capacitor C3 the HIGH on input 1 of gate GI is not main- 9OOO t ained due to the fact that transistor TRI is held on and pulls input 1 LOW through resistor R7. This means that the output of gate GI goes HIGH again having been low momentarily, that is, cleared for only a short time. The flip-flop will remain set while the subset is off-hook except for a short period when the flip-flop is cleared by the service signal. Lring these short periods when the flip-flop is being cleared capacitor C2 in the watchdog timer becomes fully charged preventing the microprocessor from being reset. This sequence continues until the subset goes on-hook whereupon a pulse from the watchdog service output of the microprocessor will cause the flip-flop to remain cleared, that is, the output of gate GI is LOW since transistor TRI is no S longer turned on by the DP output of the microprocessor. The flip-flop circuit remains cleared and the circuit is prevented from transmitting a reset pulse to the microprocessor which, during this time, is in a state where it does not provide service pulses, and the watchdog does not provide reset signals unless the monitoring circuit detects a low dry cell voltage.

If the voltage supply of the microprocessor falls below the predetermined value the voltage detector will pull input 2 of gate Gl LOW. This causes the flip-flop to set and so enable the watchdog timer. The flip-flop will remain set until the voltage detector signal goes HIGH (normal voltage) and a service

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pulse is received from the microprocessor as a result of the watchdog circuit sending a reset pulse to the microprocessor.

While the present invention has been described with regard to many particulars, it is to be understood that equivalents may be readily substituted without departing from the scope of the invention.

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Claims

1. A method of providing a reset signal to a processor when the processor fails to generate a regular service signal pulse, said method comprising the steps of pro- viding a first gate means an input of which is coupled to the processor's service signal pulse output, a second gate means whose output is coupled to the processor's reset signal input, said second gate means having a first and a second output voltage state respectively depending on whether a first or a second voltage state is present at the input thereof, said first voltage output state representing a reset signal, maintaining said second voltage state at an input of the second gate means with storage capacitor means while ever regular service signals are applied to the input of the first gate means, thereby maintaining a second output voltage state at the output of said second gate means until said regular service pulses cease.

A method as claimed in claim 1, wherein said processor is incorporated in a telephone subset circuit.

3. A method as claimed in claim 2, wherein under predcternined tclephone cir- cuit conditions the output of the first gate means is brought into the second output voltage state in the absence of regular service pulses thereby disabling the reset signal provision during said telephone circuit conditions.

4. A method as claimed in claim 3, wherein a predetermined telephone circuit S 20 condition is in on-hook condition.

A circuit arrangement for providing a reset signal to a processor when the processor fails to generate a regular service signal pulse, said arrangement comprising Sa first gate means an input of which is coupled to the processor's service signal pulse S. output, a second gate means whose output is coupled to the processor's reset signal input, said second gate means having a first and a second output voltage state re- spectively depending upon whether a first or a second voltage state is present at an input thereof, said first voltage output state representing a reset signal, a storage capacitor means coupled between the input of said second gate means and a voltage supply rail, and charge circuit means including time constant means for charging said stor- age capacitor means and maintaining a charge thereon sufficient to maintain said second voltage state at the input of said second gate means whenever the voltage state at the output of the first gate means represents the presence of a service signal at its input.

6. A circuit arrangement as claimed in claim 5, wherein said charge cir- cuit means includes a first charge circuit coupling the output of said first gate means to the capacitor storage means via a serially connected first diode means and a time constant means, whereby when the voltage state at the output of the first gate means represents the presence of a service signal pulse at o its input the said first diode means is rendered conducting thereby permitting said storage capacitor to charge.

7. A circuit arrangement as claimed in claim 6, wherein said charge cir- cuit means includes a second charge circuit coupling the output of the second gate means to the capacitor storage means via a serially connected second di- ode means and a time constant means, whereby when the first voltage state is S present at the output of said second gate means said second diode means is S rendered conducting thereby permitting said storage capacitor to charge until a voltage state is reached at the input of said second gate means to cause the voltage state at its output to change to a state representing a reset signal.

8. A circuit arrangement as claimed in claim 7, including a discharge circuit coupling said capacitor storage means to the output of the first gate means via time constant means, said discharge circuit permitting said storage capacitor means to at least partially discharge when the voltage state at the output of the first gate means represents an absence of a service signal pulse at its input.

9. A circuit arrangement as claimed in any one of claims 5 to 8, wherein said gate means are inverters.

A circuit arrangement as claimed in any one of claims 5 to 8, wherein said gate means are NAND gates. i-- 12

11. A circuit arrangement as claimed in claim 10, wherein at least one input of said first gate means is coupled to monitoring signal means such that when a moni- toring signal is present the voltage state at the output of the first gate means is such that the voltage state of the output of the second gate means represents a non-rcset state, irrespective of the presence of a service pulse signal on an input of said first gate means.

12. A circuit arrangement as claimed in claim I 1, wherein said processor forms part of a telephone subset circuit arrangement, and said monitoring signal is a signal produced by the said subset's hook-switch means.

13. A circuit arrangement as claimed in claim 12, wherein said first gate means together with a transistor means forms part of a flip-flop circuit, said flip-flop circuit being set by a monitoring signal provided when the telephone subset is in the off-hook mode, thereby maintaining a charge on the capacitor storage means whenever the voltage state of the said first gate means represents the presence of a service signal pulse at its input, and cleared when the telephone subset is brought into the on-hook mode whereupon the output of the second gate means represents a non-reset state irrespective of the presence of a service pulse signal on an input of said first gate means.

14. A circuit arrangement as claimed in claim 13, wherein a telephone subset 20 voltage monitoring signal means is coupled to a further input of said first gate means such that when a signal is present thereon the flip-flop will set while the telephone subset is in the on-hook mode to cause a reset signal to be extended to the processor means by the second gate means. 5. A circuit arrangement substantially as herein described with reference to Fig- ures 1 to 3 of the accompanying drawings. DATED THIS SEVENTH DAY OF JULY 1992 ALCATEL AUSTRALIA LIMITED C,