AU622681B2 - Electro-optic device - Google Patents

Description

1 i ii i :i: OPI DATE 12/12/89 APPLN- I D 36980 89 PC AOJP DA 07 p, PcAOJP DA 0 N BER PCT/GB89/00539 INTERNATIONAL APPLICATIO U& E UNER E PATENT COOPERATION TREATY (PCT) (51) International Patent Classification 4 International Publication Number: WO 89/11675 G02F 1/03 Al (43) International Publication Date: 30 November 1989 (30.11.89) (21) International Application Number: PCT/GB89/00539 (81) Designated States: AT (European patent), AU, BE (European patent), CH (European patent), DE (European pa- (22) International Filing Date: 18 May 1989 (18.05.89) tent), FR (European patent), GB (European patent), IT (European patent), JP, LU (European patent), NL (European patent), SE (European patent), US.

Priority data: 8811689.2 18 May 1988 (18.05.88) GB Published With international search report.

(71) Applicant (for all designated States except US): BT&D Before the expiration of the time limit for amending the TECHNOLOGIES LIMITED [GB/GB]; Whitehouse claims and to be republished in the event of the receipt of Road, Ipswich, Suffolk IPI 5PB amendments.

(72) Inventor; and Inventor/Applicant (for US only) SHAW, Robert, Norman [GB/GB]; 11 Hunters End, Trimley, Ipswich, Suffolk IPIO OXH (GB).

(74)Agent: ROBERTS, Simon, Christopher; British Telecommunications public limited company Intellectual Property Unit, 151 Gower Street, London WC E 6BA (GB).

(54)Title: ELECTRO-OPTIC DEVICE 1 r ELECTRODE AVERAGING CIRCUIT R COMPARATOR c 42 L p i ^1 r (57) Abstract A method of minimising voltage induced drift in electro-optic devices, the optical state of which is controllable by the application of an electrical potential between first and second electrodes of the device, the method comprising controlling the electrical potentials applied to the first and second electrodes such that in use the average potential difference between the first and second electrodes is substantially zero.

PCI/GB89/00539 w089/11675 ELECTRO-OPTIC DEVICE The present invention relates to electro-optic devices and in particular but not exclusively to lithium niobate electro-optic waveguide devices.

With lithium niobate (LNB) devices such as directional couplers and Mach Zehnder (HZ) interferometers, there exists the problem that in order to achieve a given level of extinction, switching or modulation, continually greater electrode potentials are required throughout the operating life of the device. This phenomenon is known as voltage induced drift. Ultimately a limit is reached where the driving electronics are supplying their maxiaun potential and it is no longer possible to achieve the desired performance. Alternatively the device may fail catastrophically with electrode breakdown caused by the high applied potential. Moreover, there is a further disadvantage of using high electrode potentials with directional couplers, in that the extinction ratio is impaired relative to that attainable with lower electrode potentials.

Clearly devices subject to such drift are unsuitable for any long term systems applications such as telecommunications or optical signal processing, because there is no lono term certainty that any particular device output corresponds to a certain applied potential.

One method which has been suggested as a means of overcoming the problem of voltage induced drift in electro-optic devices for long term systems use is to WO 89/11675 PCT/GB89/00539 divert part of the device's optical output to a detector in order to monitor the drift so that the bias voltage can be varied to track it. The disadvantages of this hypothetical arrangement are twofold: first, the difficulty of monitoring part of the optical output and deriving the required bias level; second, the drift tends to continue at a near linear rate, consequently higher and higher bias levels are still required.

The present invention seeks to provide a means of controlling voltage induced drift.

According to a first aspect, the present invention provides a method of minimising voltage induced drift in electro-optic devices the optical state of which is controllable by the application of an electrical potential between first and second electrodes of the device, the method comprising controlling the electrical potentials applied to the first and second electrodes such that in use the average potential difference between the first and second electrodes is substantially zero.

According to a second aspect, the present invention provides a method of controlling an electro-optic device the optical state of which is controllable by the application of an electrical potential between first and second electrodes of the device, the method comprising the steps of applying a first electrical potential to the first electrode, and applying a second potential to the second electrode, characterised in that one or both of the first and second electrical potentials is/are adjusted so that, in use, the average potential difference between the first and second electrodes tends to zero.

According to a third aspect, the present invention provides a driving arrangement for electro-optic devices, which arrangement comprises electrode driving means to supply both positive and negative drive voltages, _1 .i, r ~1 1 -1 WO 89/11675 PCT/GB89/00539 -3averaging means to generate an average signal indicative of the average electrode voltage, and control means for controlling said electrode driving means in response to said average signal, which control means cdaes said electrode driving means to supply positive or negative drive voltages as necessary to maintain, in use, a substantially zero average electrode voltage.

According to a fourth aspect, the present invention provides a driving arrangement for electro-optic devices, which arrangement comprises a data input to receive an input data stream of known disparity, and control means responsive to the input data stream for controlling said electrode driving means to supply positive or negative drive voltages as necessary to maintain, in use, a substantially zero average electrode voltage.

Preferred embodiments will now be described by way of example only with reference to the accompanying drawings, in which: Figure l(a) shows a schematic plan view of a conventional Mach-Zehnder interferometer: Figure l(b) shows schematically a cross section, on the line A-A, through the interferometer of Figure l(a); Figure l(c) shows the transfer characteristic of a device such as that shown in Figure l(a); Figure 2 shows schematically an arrangement for driving an electro-optic device, such as the interferometer of Figure according to the method of the present invention; SFigure 3 shows schematically an electro-optic device driving arrangement' according to the present invention, for use with electrode drivers capable of providing a DC offset; Figure 4 shows schematically an arrangement similar to that shown in Figure 3, but suitable, for use with 0 i/ WO 89/11675 PCT/GB89/00539 -4 electrode drivers which are incapable of providing a DC offset; Figure 5 is a schematic logic state diagram for the arrangements shown in Figures 3 and 4; Figure 6 shows schematically an electro-optic device driving arrangement for use with systems in which there is constant data disparity.

To facilitate an understanding of the invention the operation of a typical electro-optic device, in this case an MZ interferometer, will first be described. An HZ interferometer is formed on a z-cut lithium niobate substrate 1, typically 40mm long, 10mm wide and imm thick, and comprises an input waveguide 2 and an output waveguide 3 coupled by a pair of waveguide portions 4, 4' which form the arms of the. interferometer. The arms are about 10Om apart. The waveguides are about Sum wide and are formed in the substrate by the selective diffusion of titanium. An optical input to the input waveguide 2 will generally be provided by means of an optical fibre aligned therewith. Similarly, an optical fibre 11 will generally aligned with the output waveguide 3 to receive the optical output. On the surface of the substrate, over the arms 4, there is, optionally, formed a buffer layer 5 comprising a dielectric such as silica or alumina. In the absence of a buffer layer, voltage induced drift is less of a problem, but, unfortunately, Soptical attenuation is very high. Consequently, a buffer layer is invariably used, despite the problems of voltage induced drift. Electrodes 6, 6' of aluminium or gold are S 30 formed on the buffer layer 5 and are aligned with the arms 4, The underside of the substrate is metallised 7.

One electrode 6 and the metallisation 7 are connected to ground. The other electrode 6' is supplied with a modulating signal. The potential on the electrode 6' Lj:: i r WO 89/11675 PCT/GB89/00539 establishes an electrical field between the two electrodes, some of which passes through the waveguides.

The vertical component of this electric field passing through the interferometer arms causes a change in their I refractive index, increasing the index in one and decreasing it in the other.

As a result of the difference in refractive indices there is a phase difference between the outputs of the two arms, producing constructive or destructive interference when the outputs are combined. The resulting transfer characteristic, showing the light output against electrode voltage for a constant light input, is presented in Figure 1(c).

The transfer characteristic of an MZ interferometer is essentially a periodic cos squared function, the peaks of which correspond to points, of constructive interference, the troughs to destructive interference. The electrode voltage that is the potential difference between the two electrodes, required to drive the output from a peak to a trough is called the switching voltage V The voltage required to obtain the output peak nearest to -ero volts is the phase bias voltage V A typical switching voltage for 20mm long electrodes, on z-cut LNB, is about The phase bias voltage can be any value up to the switching voltage.

As should by now be clear, voltage induced drift involves the phase bias voltage changing during the life of the device.

In accordance with the present invention we minimise voltage induced drift by driving devices subject to such drift in such a way that the average electrode voltage tends to zero. A zero or near zero average electrode voltage is achieved by using both positive and negative drive pulses. In outline a suitable driving arrangement WO 89/11675 PCT/GB89/00539 -6would comprise: two electrode drivers, one for each polarity; and an averaging circuit to monitor the electrode voltage; a comparator having some hysteresis, connected to the averaging circuit and used to monitor the electrode voltage; the output of the comparator being used to select the appropriate one of the drivers so as to minimise the average electrode voltage.

A suitable device driving arrangement is shown schematically in Figure 2. An MZ interferometer comprises a z-cut LNB substrate with waveguide regions 11 formed therein. Optical input signals are supplied by an optical fitre 12 aligned with one end of the waveguide 11. A second optical fibre 13 is aligned with the opposite end of the waveguide to receive optical output signals. Associated with each interferometer arm is an electrode 14 and 14'. The optical output of the device is controlled by the potential applied across the two electrodes. In practice the phase bias voltage Vo is applied to one or other of the electrodes so that when the switching voltage Vi is applied the device operates between a peak and a trough in the electro-optic transfer characteristic. Thus the electrode voltage has an AC component corresponding to the switching voltage Vi and a DC component corresponding to the phase bias voltage Vo.

The phase bias voltage must be taken into account in determining the average electrode voltage and this may be more easily done if Vo is applied to one electrode, Vi being applied as appropriate to the other. The alternative, shown in Figure 2, is to ground one electrode, and apply Vo and Vi, as appropriate, to the other electrode. The phase bias voltage source 15 is connected between electrode 14 and ground. Also connected to electrode 14 are switching means 16 switchable to connect it to either positive source 17 or negative source i r~ JI I WO 89/11675 PCT/GB89/00539 7 -7- 13. Controlling the switching means 16 directly or indirectly is a comparator 19. The comparator will normally be associated with, or part of, the control electronics 20, to ensure that the switching means changes states either during a break in transmission or synchronously with a transition in the incoming data.

Averaging means 21 generate a value corresponding to the long term average electrode voltage, which value is monitored continuously or periodically by the comparator.

If the comparator monitors the average values only periodically, the un-monitored periods should not be so long that significant voltage induced drift occurs. As very many variables (including: electrode voltage, humidity, temperature, material, crystal orientation, defect density, device design, etc) influence the rate of drift, it is not practical to attempt to specify a universally acceptable upper limit for the length of the un-monitored periods. Clearly where there is likely to be rapid drift, eg 1 volt per hour, it would be desirable to monitor the average at least once a minute. Where there is likely to be a low drift rate, eg ImV per hour or less, the average may be monitored as infrequently as once an hour or even less. However, there appears to be no particular advantage to having long intervals between assessment of the average, while there are clear disadvantages. Preferably, therefore the average is monitored several times a minute. More preferably the average is monitored at least once every hundred milliseconds.

In Figure 3 an alternative arrangement is shown in Ss---lightly greater detail. This embodiment is designed to cater for electrode drivers .which have the facility for offsetting their outputs to an externally defined level.

The data input 30 feeds via an amplifier 31 into data t t 1 1 1 1 WO 89/11675 Pcr/GB89/005i9 -8steering logic 32 and delay means 33. The delay means 33 feeds into the C input of an edge-triggered data latch (a D-type flip-flop) 34. The Q output of data latch 34 feeds an input of each of first and second AND gates 36 and 37 of the data steering logic 32, one, 36, directly, the other via an inverter 35. The second and final input of each of the two AND gate 36 and 37 serves as the data steering logic connection of the output of amplifier 31.

The outputs of the AND gates, 36 and 37 trigger respective ones of'a pair of electrode drivers 38 and 39. The first electrode driver, 38 is driven by AND g;ate 37 and provides positive-going switching voltages to one electrode of the electro-optic device 50, the other electrode of the device being grounded. The second electrode driver, 39, similarly provides negative-going switching voltages. The outputs of the electrode drivers are also connected to an electrode averaging circuit 40 which provides feedback to the D input of the data latch 34. The delay element 33 and the data latch 34 are provided to ensure that switching between electrode drivers occurs during a logic-low state in the data bit pattern to give synchronized transparent operation. The electrode averaging circuit comprises an RC circuit 41 and a comparator 42, the RC circuit being connected between the outputs of the electrode drivers and the summing input of the comparator 42, the second, reference input of which is grounded. The RC circuit 41 provides some hysteresis in order to prevent too frequent switching between the electrode drivers. The phase bias voltage Vo is provided by the DC offset output of the electrode drivers and should be chosen to be less than Vr/2.

For a device with a transfer characteristic as shown in Figure Ic, the logic state would be aligned to node #2 by offsetting the outputs of the two electrode drivers i

I^~

l ll l l WO 89/11675 PC]/GB89/00539 -9by +lV. Thus the ground electrode would be at zero volts and a logic would appear as either +4V when the positive driver is selected or -2V when the negative driver is selected. The comparator input is then the actual average electrode voltage and includes the phase bias offset.

Figure 4 illustrates a further embodiment which uses electrode drivers which do not have a DC offset capability. The arrangement differs from that shown in Figure 3 only in that the phase bias voltage is applied to the ground electrode, but with opposite polarity to give the same electrode difference voltage as in the previous embodiment. Additionally the reference contact of the comparator 42 in the electrode averaging circuit is connected to the ground electrode, and hence -Vo, rather than to ground. Again the magnitude of the phase bias voltage should be chosen to be less than Vr/2. With reference to Figure Ic, logic will now be OV and logic would appear as either +3V when the positive driver is selected or -3V when the negative driver is selected. By connecting the reference input of the comparator to the negative phase bias voltage, the comparator now operates with the same difference voltage as the electrodes.

Figure 5 shows an illustrative logic state diagram for the embodiments shown in Figures 3 and 4. This figure is largely self explanatory, but it is uorth noting the action of the comparator. Initially, "l"s in the input data cause the positive electrode driver, 38, to operate, ,with "O"s requiring a zero output from the electrode drivers. Hence a "I1" initially causes the voltage on the summing input of the comparator to rise. When the comparator's threshold is exceeded, its output changes |e WO 89/11675 PCr/GB89/00539 10 level, in this case going from low to high. At the next transition in the input data, the data-latch output Q changes state, in this case also from low to high.

Consequently the next in the input data results in a pulse from the negative electrode driver 39. The negative electrode driver is used for all data "l"s until the comparator's opposite threshold is reached, which results in the comparator's output changing state. On the next input data transition the data-latch output Q changes lo state, with the consequence that subsequent "l"s in the input data stream result in the positive electrode driver 38 supplying the switching voltage Vi. Clearly the comparator's threshold levels should be set such that voltage induced drift is kept to an acceptably low level.

;Figure 6 shows a yet further embodiment, devised for systems in which there is constant data disparity in the code of the input data. The majority of constant disparity data codes do in fact have an average mark-to-space ratio of 50/50 because of the way high-speed receiver designs work, and for such data codes a very simple driving arrangement is possible. The primary difference between this embodiment and those illustrated in Figures 3 and 4 is that the switching between electrode drivers is not controlled by means of an electrode averaging circuit 40 connected to the D input of the edge triggered data latch but rather a clock generator, in this case a square-wave generator is connected in place of the averaging circuit 40. The effective mark-to-space ratio of the clock generator is set to give zero average electrode difference voltage for the code disparity and phase bias voltage used. Since the phase bias voltage required varies from device to device, it is preferable to employ a clock generator having a variable mark-to-space L iii L i -IL- i. _i:l i -ii -r 1 i -iil--l .I L---*CLLI. -C 9~ WO 89/11675 PCF/GB89/00539 11 ratio so that the ratio can be set according to the phase bias voltage used for any particular device.

With a constant disparity data code having a mark-to-space ratio of 50/50, the condition for zero average electrode voltage is given by: 0 0.5Vo m (Vo Vi) (0.5 m)(Vo Vr) for 0<m Where Vo is Vi is and m is Solving for m the phase bias voltage the switching voltage the mark-to-space ratio.

m gives: 0.5 Vi Vo 2 Vi io For a device with the transfer characteristic shown in Figure Ic the mark-to-space ratio of the square-wave generator would be set to favour the negative electrode driver by the ratio 0.0833 to 0.9167. Of course it is not essential, merely preferable, that the clock generator provides a square-wave output, any suitable waveform or pulse shape can be used. Where a non-square-wave output is provided, thresholding means may be provided, and/or appropriate substitution be made for the D-type flip-flop 34.

Switch S1, which would probably not be provided in any real-life implementation of the circuit, illustraieg te e choice between the phase-bias arrangements of the embodiments shown in Figures 3 and 4. Hence, where the electrode drivers have a DC offset capability the phase bias is applied to the 'live' electrode; alternatively where no DC offset capability exists the (negative) phase-bias is applied to the ground electrode.

i r i i i I I WO 89/11675 PCT/GB89/00539 12 While the invention has been described in terms of embodiments in which separate positive and negative electrode drivers are provided, this has been for ease of description. It is of course not essential to provide totally separate electrode drivers, although such an arrangement does offer advantages in certain circumstances, all that is necessary is that the electrode means can provide both positive and negative drive voltages.

A

1 'NiI\~ i ir~:

Claims (8)

1. A method of minimising voltage induced drift in electro-optic waveguide devices, other than liquid crystal devices, the optical state of wbich is controllable by the application of an electrical potential between first and second electrodes of the device, the method comprising controlling the electrical pontentials applied to the first and .ond electrodes such that in use through the application of both positiv voltages and negative voltages to one of said electrodes the long term average pontential difference between the first and second electrodes is substantially zero.

2. A method of controlling an electro-optic waveguide device, other than a liquid crystal device, the optical state of which is controllable by the application of an electrical potential between first and second electrodes of the device, the method comprising the steps of applying a first electrical potential to the second electrode, characterised in that one or bcth of the first and second electrical potentials is /are adjusted,with the potentials applied to said first electl-- alternately being positive and negative as necessary,so that,in use,the average potential difference between the first and second electrodes tends to zero. 3, A method as claimed in claim 1 or claim 2 wherein said second electrode is held at ground potential.

4. A driving arrangement for electro-optic devices,which arrangement comprises electrode driving means to supply both positive and negative drive voltages,averaging means to generate an average signal indicative of the average electrode voltage,and control means for controlling said electrode driving means in response to said average signal,which control means causes said electrode driving means to supply positive or negative drive voltages as necessary to maintain,in use ,a substantially zero average electrode voltage SUnited -i i WO 89/11675 PCIrGB9/0039 14 A driving arrangement for electro-optic devices, which arrangement comprises a data input to receive an input data stream of know disparity, electrode driving means to supply both positive and negative drive voltages, and control means responsive to the input data stream for controlling said electrode driving means to supply positive or negative drive voltages as necessary to maintain, in use, a substantially zero average electrode voltage.

6. A driving arrangement as claimed in claim 4 or claim wherein the control means is configured to ensure that, in the presence of an input data stream for the control of said elactro-optic device, switching between positive and negative drive voltages occurs only during a logic-low state in the input data stream.

7. A driving arrangement as claimed in claim 6 as dependent on claim 5, wherein the control means comprises clock generation means to produce a stable -control signal which determines the ratio of the incidence of positive drive voltages to the incidence of negative drive voltages, said ratio being a function of said know parity.

8. A driving arrangement as claimed in claim 7 wherein the control means further comprises an edge-triggered data latch, the data latch having a first input to receive said stable control signal, a second input to receive said data, the output of the data latch controlling the switching between the different polarity drive voltages, the arrangement being such that switching between electrode driver polarity occurs only during a logic-low state in the input data bit pattern, thereby ensuring i I synchronized transparent operation. 1 1 s I 15

9. A driving arrangement as claimed in any one of claims 4 to 8, wherein the electrode driving means comprises two electrode drivers, one for positive voltage pulses, and one for negative voltage pulses. A driving arrangement as claimed in any one of claims 4 to 9 in operative association with an electro-optic device.

11. An electro-optic device wherein the voltage induced drift in the device is reduced according to the method of any one of claims 1 to 3. DATED this 7th day of February 1992 BT D TECHNOLOGIES LIMITED Attorney: PETER HEATHCOTE Fellow Institute of Patent Attorneys of Australia S. of SHELSTON WATERS g S