AU6154296A - Distributed write data drivers for burst memories - Google Patents
Distributed write data drivers for burst memoriesInfo
- Publication number
- AU6154296A AU6154296A AU61542/96A AU6154296A AU6154296A AU 6154296 A AU6154296 A AU 6154296A AU 61542/96 A AU61542/96 A AU 61542/96A AU 6154296 A AU6154296 A AU 6154296A AU 6154296 A AU6154296 A AU 6154296A
- Authority
- AU
- Australia
- Prior art keywords
- write data
- data drivers
- distributed write
- burst
- memories
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
- G11C7/109—Control signal input circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
- G11C7/1018—Serial bit line access mode, e.g. using bit line address shift registers, bit line address counters, bit line burst counters
- G11C7/1021—Page serial bit line access mode, i.e. using an enabled row address stroke pulse with its associated word line address and a sequence of enabled column address stroke pulses each with its associated bit line address
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
- G11C7/1096—Write circuits, e.g. I/O line write drivers
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US497354 | 1983-05-23 | ||
US08/497,354 US5598376A (en) | 1994-12-23 | 1995-06-30 | Distributed write data drivers for burst access memories |
PCT/US1996/009098 WO1997002571A1 (en) | 1995-06-30 | 1996-06-06 | Distributed write data drivers for burst memories |
Publications (1)
Publication Number | Publication Date |
---|---|
AU6154296A true AU6154296A (en) | 1997-02-05 |
Family
ID=23976526
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
AU61542/96A Abandoned AU6154296A (en) | 1995-06-30 | 1996-06-06 | Distributed write data drivers for burst memories |
Country Status (2)
Country | Link |
---|---|
AU (1) | AU6154296A (en) |
WO (1) | WO1997002571A1 (en) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6545942B2 (en) * | 2001-02-21 | 2003-04-08 | Fujitsu Limited | Semiconductor memory device and information processing unit |
US11211103B1 (en) * | 2020-08-18 | 2021-12-28 | Micron Technology, Inc. | Burst clock control based on partial command decoding in a memory device |
Family Cites Families (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0547890A3 (en) * | 1991-12-17 | 1993-12-08 | Sgs Thomson Microelectronics | A read/write memory with interlocked write control |
-
1996
- 1996-06-06 WO PCT/US1996/009098 patent/WO1997002571A1/en active Application Filing
- 1996-06-06 AU AU61542/96A patent/AU6154296A/en not_active Abandoned
Also Published As
Publication number | Publication date |
---|---|
WO1997002571A1 (en) | 1997-01-23 |
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