AU609343B2 - Image coding and decoding device - Google Patents

Description

To: The Commissioner or Patents DIWV1SONAL APPLICATION L. Lodged .i 7•.

hi-I 609343 PATENTS ACT 1952 COMPLETE SPECIFICATION Form

(ORIGINAL)

FOR OFFICE USE Short Title: Int. Cl: Application Number: Lodged: Complete Specification-Lodged: Accepted: Lapsed: Published: Priority: Related Art: TO BE COMPLETED BY APPLICANT Name of Applicant: Address of Applicant: MITSUBISHI DENKI KABUSHIKI KAISHA 2-3, MARUNOUCHI 2 CHOME

CHIYODA-KU

TOKYO 100

JAPAN

Actual Inventor: Address for Service: GRIFFITH HACK CO.

601 St. Kilda Road, Melbourne, Victoria 3004 Australia 'DO 0 Complete Specification for the invention entitled: IMAGE CODING AND DECODING DEVICE The following statement is a full description of this invention including the best method of performing it known to me:- I S GRIFFITH HACK CO PATENT AND TRADE MARK ATTORNEYS MELBOURNE SYDNEY PERTH

I

IMAGE CODING AND DECODING DEVICE BACKGROUND OF THE INVENTION Field of the Invention The present invention relates to an image coding and decoding device, and more particularly to an image coding and decoding device which can efficiently code and decode the motion image signals so as to transmit and record the signals by the interframe coding.

Description of the Prior Art FIG. 3 is a block diagram which shows a transmitting section of an image coding transmitter in the prior art. In FIG. 3, numeral 2 designates a motion compensating circuit, numeral 6 designates a differential section, numeral 8 designates a coding and decoding circuit, numeral 11 designates an adder, and numeral 13 designates a frame memory.

0a o° FIG. 4 is a block diagram which shows a motion Svector detecting section in the motion compensating circuit 2. In FIG. 4, numeral 14 designates a differential section, numeral 16 designates a distortion operator, and numeral 18 designates a comparator.

o The operation of the device will be described.

0o In the motion compensating circuit 2, using digitally transformed input signals 1 and previous frame reconstruction signals 3 stored in the frame memory 13, with the picture element blocks of the prescribed size oo0.

o N1 x N 2

(N

1

N

2 being plus integers) used as a unit, a block which has the most similar pattern to the block of the input signal is detected from the previous signals, and signals of the detected block are outputted as predicting signals 4, and index information 5 indicating motion vectors being position shift between the position of the block and that of the input signal block is transmitted to the receiving side.

An example of the motion detecting method is shown in FIG. 4.

Assuming that the input signal block be the previous frame signal block be the number of the searched blocks be L (L being plus integer), the matching distortion between the blocks be di(17), and K N 1 x N 2 (S S'i (St' iK),

K

ds -s IS S' i L dl i=l J ij Among di(ll) estimated by the differential section 17 and the distortion operator 16 based on the above formulas, the block having the smallest matching distortion value is detected by the comparator 18, and the block signal is transformed into the predicting signal 4 block by block, and the index information 5 of the block motion vectors is outputted. However, in FIG. 4, the hardware composition is simplified by applying the serial process to the distortion operation and the ao oc 2 I- L. comparing process at each searching block. In FIG. an example of the arrangement of the searching vectors is shown.

Differences between the predicting signals 4 estimated as above described and the input signals 1 are taken, and the differential signals 7 are coded by the coding and decoding circuit 8, and then the coded information 9 is transmitted to the receiving side and at the same time the differential decoded signals 10 by decoding the coded information and the predicting signals 4 are added thereby the reconstructed signals 12 are obtained. After one frame of these reconstructed signals 12 are stored in the frame memory 13, they are read out as the previous frame reconstructed signals 3 at the next coding.

In the coding and decoding circuit 8, coding is executed only when the value of the differential signals 7 is larger than a prescribed threshold value, and the picture element supplementing (the value of the predicting signals 4 can be made equal to that of the reconstructed signals 12 by making naught the differential reconstructed signals without coding) is performed in other cases thereby the generating information content can be restrained.

Since the motion compensating device in the prior art is constituted as above described, the searched vectors are limited in number, resulting in the most .944 o 0 44 44 4 444 4 44 0 4 3 suitable motion compensation being made impossible because of the image being out of the searched range in case its movement is too much extensive. Furthermore there is another problem in that in case of the deterioration of the picture quality, or in case of the changing of scenes, the matching precision between frames is low, and the restraint effect of the predicting error signal component does not appear, causing the increase of the generating information and the deterioration of the picture quality.

FIGS. 10 and 11 are block diagrams which show the coding section of the conventional image signal progressive build-up coding and decoding device, and the composition model of the decoding section, which are, for example, disclosed in the column "Vector Quantization of the Image Signal" of the Journal of the Institute of Television Engineers of Japan, Vol. 38, No. 5, pp.

452 457 (1984). In the coding section in FIG. numeral 101 designates the input signal vectors which block the input image signal system of the static image data by the unit of the sample m x n n being integers), numeral 102 designates a subtractor which finds the residual signal vectors 103 between the input signal oa a vectors the previous stage decoded vectors delayed by one frame, numeral 128 designates an average value separated and normalized vector quantization decoder, 4s tc numeral 110 designates the amplitude coded data, numeral .04 04 129 designates the amplitude coded data, numeral 130 designates the output vector index coded data, numeral 114 designates a code assignment circuit, numeral 115 designates the coding device output signals, numeral 117 designates the residual signal decoded vectors, numeral 118 designates an adder which adds the residual signal decoded vectors to the front stage decoded vectors delayed by one frame, numeral 119 designates the decoded vectors, and numeral 120 designates a frame memory for delaying the decoded vectors by one frame.

In the decoding section in FIG. 11, numeral 115 designates the coding device output signals obtained in the coding section, numeral 124 designates a coding assignment circuit which inverts the coding assignment, and numeral 131 designates an average value separated and normalized vector quantization decoder which carries out the average value separated and normalized vector quantization decoding.

First, the principle of the vector quantization will be described briefly. The input signal systems of K pieces as a whole shall be made input vectors x (x 1 2, Xk}. Then a set of N pieces of the representative points (that is, the output vectors) yi (Yil, Yi2 y.

2 Yik. of K-dimensional Euclid signal space RK (xE R shall be made Y N] The vector quantizer searches the output vector yi which is in the shortest distance from the output vectors, and it defines the "output vector as follows: 04 if d(x, yi) d(x, VZ) for all 2 x y i Where d(x, y) indicates the distance between the input and output vectors (distortion). Then the input vector x is transmitted or recorded by the index i of the output vectors, and substituted by yi at the reconstruction state.

The average value separated and normalized vector quantization supplies the average value separated and normalized of the input vectors of the vector quantizer so as to limit the distribution of the output vectors on the superunit spherical surface in the multidimensional signal space. Let the input signal vectors be S IS1, S2, SK}, and the average value p, the amplitude a, and the average value separated and normalized vectors x are represented respectively as follows:

K

S =l S2 (S 2]1/2 K Z= Z (S k )/O x {xl x2'

X

K

Where as the approximate formulas of the amplitude a, following formulas can be used.

6 mr S 1

K

C 1 ff Is II Z=l o max S min S The scalar quantization of the average value p and the amplitude a, and the vector quantization of the average value separate input vectors x can make the generality of the vector quantizer with the limited number of output vectors much wider so as to develop its coding performance.

The operation of the image signal progressive build-up decoder in the prior art will be described. In FIG. 10, at the first stage of coding, the frame memory 120 which stores the prestage decoded results is left cleared, and the input signal vectors 101 pass through the subtractor 102 as they are, and the average value separated and normalized vector quantization is performed as the residual signal vectors 103 in the average value separated and normalized vector quantizer 128, thereby the coding data 110 of the average value, the coding data 129 of the amplitude, the coding data 130 of the output vector index, and the residual signal decoded vectors 117 are outputted. Each of the coded data 110, 129, 130 is converted into the suitable code words by the code assignment circuit 114 and then transmitted. The residual signal decoded vectors 117 pass through the adder 118, as they are, and are written as the decoded S~7 vectors 119 to the frame memory 120. At the second coding stage, in the subtractor 102 the residual signal vectors 103 are obtained by subtracting the previous stage decoded vectors from the input signal vectors 101.

The residual signal vectors 103 are quantized into the average value separated and normalized vectors in the average value separated and normalized quantizer 128, thereby the coding data 110 of the average value, the coded data 129 of the amplitude, the coded data 130 of the output vector index, and the residual signal decoded vectors 117 are outputted. Each of the coded data 110, 129, 130 is converted into the suitable code words in the code assignment circuit 114 and then transmitted.

The residual signal decoded vectors 117 are added to the 15 front stage decoded vectors in the adder 118 so as to renew the frame memory 120 as the decoded vectors 119.

Oo These processes are followed by the same coding on operations repeated at each stage so as to transmit each of the coded data 113, 129, 130, resulting in renewing the frame memory 120.

In FIG. 11, when the decoding starts, the frame c memory 120 which stores the previous stage decoded results is left cleared. The coding device output signals 115 obtained in the coding section are inversed a S 25 with respect to the code assignment in the code assignment circuit 124 so as to produce each of the coded data 110, 129, 130. Each of the coded data 110, 8 129, 130 is inputted into the average separated and normalized vector quantization decoder 131, where the residual signal decoded vectors are obtained from the decoded average value and the amplitude reconstructed vectors. In the adder 118, the residual signal decoded vectors 117 are added to the front stage decoded results of the frame memory 120 so as to renew the frame memory 120. These operations are repeated at each stage.

Since the image signal progressive reconstruction coding device in the prior art is composed as above described, it is difficult to control the amount of the coded information generation and the reconstructed image quality suitably in wider range.

FIG. 16 is a block diagram which shows a composition 0 15 example of a transmission section of an interframe coding i' o device disclosed, for example, in the Technical Report 2of the Institute of Electronics and Communication on o Engineers of Japan IE84-1 In FIG. 11, numeral 201 designates the digitalized motion image signal system, numeral 207 designates a subtractor for obtaining the interframe differential signals, numeral o o 208 designates the interframe predicting signals formed from the past time frame which already finished coding, numeral 209 designates the interframe differential o 25 signal system, numeral 210 designates a block discrimination section which quantizes the interframe o differential signals 209 of the predicting error to 9 naught, and discriminates block by block whether the coding at the next stage needs or not, numeral 211 designates the threshold value for the block discrimination, numeral 212 a coding control section which decides the threshold value 211, numeral 213 designates a coding and decoding section which encodes and decodes the blocks judges as the significant predicting errors (they are called as the significant blocks or the blocks whose predicting errors are regarded as naught are called ineffective blocks) in the block discriminating section 210, numeral 214 designates the decoded predicting error signals obtained in the coding and decoding section 213, numeral 215 designates an adder which adds the predicting signals 208 to the decoded predicting error signals 214, numeral 216 designates the decoding image signal system, o o numeral 217 designates a frame memory which forms the interframe predicting signals 208 using the decoded S° image signal series 216, numeral 218 designates the 0 coded data obtained in the coding and decoding section 213, numeral 219 designates a variable length coding section which encodes the coded data 218 in variable oa length, numeral 220 designates a buffer for smoothing where the variable length coding data system processes a in the variable length coding section 219 is transmitted 25 at the constant transmitting speed, numeral 221 designates 25 at the constant transmitting speed, numeral 221 designates 0 the data that count the variable length coding data system per frame (the amount of the generated 10 1' I I

~-L

information per frame), numeral 222 designates a line interface section for transmitting the smoothed data system by the buffer 220 into the transmission line, and numeral 223 designates the transmission signals.

FIG. 17 is a block diagram showing a composition example of the coding control section 212 in FIG. 16. In FIG.

17, numeral 232 designates a register for delaying the threshold value 211 in frame period, numeral 233 designates the threshold value delayed by the register 232, and numeral 234 designates a table ROM. FIG. 18 is a diagram which explains the characteristics to be written in the table RAM 234.

The operation of the device will be described. The digitalized image signal system 201 is converted into the interframe differential signals 209 through the So subtraction between the interframe predicting signal 208 by the subtractor 207. The interframe predicting signals 208 are formed using the reconstruction image signal system of the past time frame whith has finished coding and local decoding in the transmission section, therein some other methods like the motion compensation C, 0 :o °are sometimes applied. The interframe differential signals 209 come near to naught in the case of no change o 0o or movement in a subject, and the block discrimination °9 25 section 210 discriminates the significant blocks or the "IS insignificant blocks so as to transmit only the data making the insignificant blocks recognized as they are, 11 -z I- product value to the input vector among a set of normalized /2 resulting in compressing the amount of the information.

In order to discriminate blocks, the sum of the absolute value of the blocked interframe differential signal system is found and compared with the threshold value 211. Let the blocked interframe differential signal system be Ej (j 1, 2, k) and the threshold value be T then the discrimination of the blocks is executed as follows: k if K E IC I T then insignificant block j=l n k K E IE I T significant block j=l J n Where with respect to the blocks recognized as significant, the interframe differential signals 209 are encoded. The coding and decoding section 213 encodes S2; the significant blocks and then decodes them so as to output the decoded predicting error signals 214 and the °o coded data 218. There are various coding and decoding methods, but they have little relationship to the invention and the detailed description shall be omitted here. The decoded predicting error signals 214 are added by the adder 215 to the interframe predicting signals 208 so as to form the decoding image signal system 216. The decoding image signal system 216 is Sstored in the frame memory 217, and used for forming the I interframe predicting signals in the next frame and so 00 12 PFr i p-lforth. On the other hand, the coded words are assigned to the coded data 218 in the variable length coding section 219 corresponding to generation frequency of each data. The buffer 120 smoothes the speed so as to transmit the variable length coding data system at the constant transmitting speed, and counts the variable length coding data system per frame and outputs them as the information amount 221 per frame to the coding control section 212. The line interface section 222 transmits the speed smoothed variable length coded data as the transmission signals 223 into the transmission line.

The coding control section 212, referring to the table ROM 234 by using the threshold value 221 given the frame delay by the register 232 and the amount of OO information, outputs the new threshold value 211. Let the previous threshold value 233 be Tn_ and the 0 information amount 221 in the encoded frame using this o T n be B then the new threshold value T (211) is ~osn-i n-i' n obtained as shown in FIG. 18. Between the threshold value and the information amount, there is a hyperbolic 0 relation as shown in FIG, 18. In FIG. 18, there are 0o° four curves written, which vary according to the width of the movement of a subject. When B and T are n-i n-1 ;o 25 given, the most suitable curve is chosen among the Splural curves stored in the table ROM 234. Then the 0o0 •point B* of the amount of information is looked for o 64 13- 0 0 I I! Z__r along the chosen curve. Where B* is the information amount admitted to one frame in accordance with the transmission speed. When the point of the amount of information becoming B* is decided on the chosen curve, the threshold value at the point is read as T n In other words, according to the relation between the threshold value T of the frame which finishes the n-1 coding and the information amount Bnl, the characteristic curve corresponding to the amount of motion is decided and controlled so as to obtain the necessary threshold value to attain the aimed information amount as the new threshold value T from the curve.

n Since the interframe coding device is constituted as above described, delay is always produced in S15 controlling the threshold value for smoothing the amount o o OO 1 ,o of the information. Accordingly it is disadvantageous a a0 in that when the subject is transferred from the static 00 o° state to the dynamic state or from the dynamic state to >oo* the static state, the extreme time lapse may be produced or the focusing of the picture quality is likely to delay.

°O a FIG. 23 is a block diagram showing a composition 0 example of a transmission section of an image signal °0 progressive reconstruction coding device in the prior S" 25 art using the vector quantizer, which is disclosed, for au example, in the Technical Report of the Institute of oa0, Electronics and Communication Engineers of Japan IT85-61 14

QMMWA

a 0 a -4 0 0 a 4- -1 Er .ILU~ M11 I (1985) titling "Image High Performance Coding by Vector Quantization" In FIG. 23, numeral 301 designates the input signal vectors which block the input signal system of the static image data and so on by every sample m x n n being natural numbers), numeral 302 designates a subtractor which obtains the residual signal vectors of the input signal vectors 301 and the previous stage decoded vectors 319 delayed by one frame, numeral 303 designates the residual signal vectors, numeral 306 designates an average value coding and decoding device which finds the average value within block at each vector and gives the high performance coding and decoding to the average value and outputs the average value coded data 308 and the average value decoded value 309, numeral O .307 designates a normal vector quantization coding and decoding device which converts the residual signal vector 303 into the normalized output vectors and the amplitude 0E gain through the inner product vector quantizer and outputs the vector quantization coded data 310 and the amplitude reconstructed output vector 311, numeral 308 designates the average value coded data, numeral 309 designates the average value decoded value, numeral 310 designates the vector quantization coded data, numeral 311 designates the amplitude reconstructed vector, Snumeral 312 designates a first adder which adds the o average value decoded value to the amplitude Il 15 4 4 o o 4

ISI

L

reconstructed vector so as to find the residual signal decoded vector 315, numeral 315 designates the residual signal decoded vector, numeral 316 designates a second adder which adds the residual signal decoded vector 315 to the front stage decoded vector 319 delayed by one frame so as to obtain the decoded vector 317 at each stage, numeral 317 designates the decoded vector at each stage, numeral 318 designates a frame memory which delays the decoded vector by one frame, numeral 319 designates the previous stage decoded vector outputted from the frame memory 318, numeral 320 designates a coding assignment circuit which transforms the average value coding data 308 and the vector quantization data 310 into the coded words using the variable length coding and then outputs the coded words, and numeral 324 designates the coded output data.

The operation of the device will be described. In Iii FIG. 23, at the time of the first stage coding, the frame memory 318 is left cleared. The input signal vectors 301 are not at all processed in the subtractor 302, but outputted as the residual signal vectors 303 as they are. In the normalized vector quantization coding device 307, the average value of the residual signal vectors 303 is estimated, and then the average value is subjected to the high performance coding using the DPCM coding method or the like so as to output the average value coded data 308 and the average value decoding value 16 00 0 '4 4 0 04 3 _W rl l- k 309 locally decoded. On the other hand, with respect to the normal vector quantization, the residual signal vectors 303 are converted through the inner vector quantizer into the normalized output vectors and the amplitude gain, and the vector quantization coding data 310 and the amplitude reconstructed output vectors 311 are outputted.

The operation principle of the inner product vector quantizer will be described referring to FIG. 24. In the inner product vector quantizer, the average value separation and normalization is given, and a set of the normalized output vector yi arranged on the unit superspherical surface of the multidimensional signal space, Y [y 1 y2' N] is used. That is, thp normalized output vector yi satisfies the following conditions simultaneously.

C C C o 0 04 4-~ 0

*CCC

K

K 2 1/2 Yil I Yij 1, j=l1 E yj- 0 j=1 1 Cjo.

"0~ '4 £6 o 400 44 '4D 4 4 '4 '4 The input vector x to the inner product vector quantizer is converted through the operation process of the following formulas into the normalized output vector yi which gives the maximum inner product value to the input vector x, and the maximum inner product value is given as the amplitude gain g of the input vector x.

if I(x, I(x, y9) for all Z 17 0 6 1 A1 4

K

vi) E (xjy i 1 j=l

J

vi g Ix, yi) I yilcos |xjcos9 The amplitude gain g found as the scalar quantity is encoded and decoded independently, and the coded data together with the index i of the normalized output vector yi are outputted as the vector quantization coding data 310. At the same time, the normalized output vector y.

is multiplied by the local decoding value g of the amplitude gain g thereby the amplitude reconstructed output vector yi* (311) is obtained.

yi* g -i o a c *The average value decoded value 309 and the amplitude reconstructed output vector 311 are added in o the first adder 312 thereby the residual signal decoded 4a ar vector 315 is obtained, and then the residual signal decoded vector 315 is added in the second adder 316 to the previous stage vector 319 delayed by one frame. The Sdecoding vector 317 of each stage being output of the second adder 316 is written in the frame memory 318 and Sdelayed by one frame. On the other hand, the average Svalue coded data 308 and the vector quantization coding g data 310 are converted into suitable code words respectively in the code assignment circuit 320 and then 18 -output vector as follows: 0 4 5 1 b- i ;i ,i transmitted as the coded output data 324. At the second I stage and so forth, the above-mentioned coding processes are repeated and executed one after another with respect to the residual signal vectors 303 between the input signal vectors 301 and the previous stage decoded vectors 319 stored in the frame memory 318.

Since the image signal progressive reconstruction coding device is constituted as above described, the block in coding at each stage is always same in size, and when the block size is made larger the operation scale of the inner product vector quantizer becomes larger in proportion to the dimension number of the vector, and when the block size is made smaller it is difficult to decrease the amount of the coded information at the first stage significantly.

FIG. 28 is a block diagram showing a composition example of an interframe vector quantizer in the prior art disclosed, for example, in Murakami et al. "The Vector Quantization Method Interframe Coding Simulation" in the draft 1175 of the annual meeting 1983 of the Institute of Electronics and Communication Engineers of Japan. In FIG. 28, numeral 401 designates the input image signal system, numeral 402 designates a subtractor which performs subtraction to the interframe predicting signals, numeral 403 designates the interframe predicting signals, numeral 404 designates the interframe differential signals, numeral 439 designates 19 4 -6 a vector quantization coding section, numeral 440 designates the coded data, numeral 441 designates a vector quantization decoding section, numeral 416 designates decoded interframe differential signals, numeral 417 designates an adder which adds the decoded interframe differential signals 416 and the interframe predicting signals 403, numeral 418 designates the decoded image signal series, numeral 419 designates a frame memory which gives frame delay to the decoding image signal system 418 and forms the interframe predicting signals 403, numeral 420 designates a variable length coding section, numeral 421 designates a buffer for smoothing the speed, numeral 422 threshold value, numeral 423 designates a line interface and numeral 424 designates transmission signals.

FIG. 29 is a block diagram showing a composition example of the vector quantization coding section 439.

o09 a In FIG. 29, numeral 428 designates an average value o separation and normalization section, numeral 429 420 designates the normalized vectors, numeral 431 designates a code book which stores the output vectors, numeral 432 designates the output vectors, numeral 433 designates a f edistortion operation section which finds distortion Sne between the normalized vectors 429 and the output vectors Sp0, 25 432, numeral 436 designates the distortion found in the distortion operation section 433, numeral 437 designates a minimum distortion detecting section which detects the 20 It a tL 7 minimum value from the distortion 436, numeral 430 designates the average value and the amplitude which are separated by the average value separation and normalization section 428, numeral 434 designates a block discrimination section, numeral 422 designates the threshold value used for discriminating the blocks, numeral 435 designates the block discrimination information, numeral 438 designates the index of the output vectors giving the minimum distortion, and numeral 440 designates the coded data.

The operation of the device will be described. The interframe predicting signals 403 are subtracted from E the input image signal system 401 by the subtractor 402, j thereby the input image signal system 401 is converted into the interframe differential signals 404. Since the 3 interframe differential signal has little power in comparison to the original signal, it can be encoded with i little coding error. The interframe differential signal K 404 is encoded in the vector quantization coding section S 20 439 (the coding method is described afterwards). Then the threshold value 422 is used as a parameter. The coded data 440 encoded in the vector quantization coding section 439 is decoded in the vector quantization decoding section 441 thereby the decoding predicting differential signal 416 is obtained. The interframe predicting signal 403 and the decoded interframe S differential signal 416 are added in the adder 417 21 8 I r -iL III i r II thereby the decoding image signal system 418 is obtained. The decoded image signal system 418 is stored temporarily in the frame memory 419 and supplied with the frame delay thereby the interframe predicting signal is formed. On the other hand, the coded data 440 is subjected to variable length coding in the variable length coding section 420 and stored temporarily in the buffer 421 and subjected to speed smoothing process, and then passes through the line interface 423 and outputted as the transmission signal 424. In the buffer 421, the threshold value 422 in proportion to the data storage amount subjected to variable length coding is outputted and given to the vector quantization coding section 439 so as to control the information amount. Control of the coding and the information amount in the vector quantization coding section 439 will be described. The input signals to be subjected to the vector quantization are the interframe differential signals 404. The signals 404 are blocked (vector) in the average value separation and normalization section 428, and subjected to the average value separating and normalizing process.

If the blocked input signals are represented as S [S 1 2, I Sk], the average value separating and normalizing process is expressed for example as follows: k k-I average value m: m k E S.

j=l

J

22- 9 El I__ k amplitude g: g k E Is. m| j=l J average value separate normalization: x. m)/g The normalized vectors X [xl, x 2 x k obtained as above described are separated from the scalar quantity being the average value and the amplitude, and therefore unified with respect to the probability distribution in comparison to the vectors S before the average value separation and normalization, resulting in the effect to improve the efficiency of the vector quantization as hereinafter described. The distortion between the normalized vector 429 and the output vector 432 read from the code book 431 is found in the distortion operation section 433. In the minimum oo 15 distortion detecting section 437, the minimum value o a among the distortion 436 between the output vectors o\ stored in the code book 433 and the input vectors 429 is detected, and the index number 438 of the output vector giving the minimum distortion is outputted.

This process is the vector quantization. This is expressed in formulas as follows: a'a distortion d: k d(x, yi) Z Ix. Yijl j=l

J

23 010 10 j wherein yj [Yil' i2' Yik] output vector The maximum inner product value P is given as the max correction amplitude 413 (hereinafter referred to as which approximates x, namely the magnitude of the average value separated input vector x as shown in the following formulas.

i k 2 1/2 1 k 1 Yij 1, J Lj=l I D

K

j=l Pmax P(x, i IxI ily cos6.

cos6 g The correction amplitude g is subjected to the high efficient coding in the amplitude coding device 415, and converted into the amplitude coding data 418. In the coding data multiplier 420, the average value coding data 417, the amplitude coding data 418 and the index I 15 419 are multiplied, and transmitted as the output data i 421 for the coding device in accordance with the i prescribed format.

j The decoding operation will be described. The 1 output data 421 for the coding device are separated in the coding data multiplication separating section 422 into the average value coding data 417, the amplitude coding data 418 and the index 419 in accordance with the prescribed format. The average value coding data 417 24 llr 'I i'T I

-L

are decoded through the average value decoding device 423, and converted into the average value decoding value 425 (hereinafter referred to as Similarly Y [yl' Y2' Yi' tN] represents the contents of the code book.

vector quantization Q: Q(X) i wherein d(x, yi) d(x, ym) for m i In this case, the coding process is the mapping from x to i, and the mapping from i to yi (reading-out of the code book) becomes the decoding process. i corresponds to the index 438. The average value and the amplitude 430 are used cogether with the threshold value 422 to discriminate the blocks in the block discriminating section 434. When the threshold value 422 is made Th, the block discrimination is expressed as follows: Iml Th and g Th insignificant block o00 0 0 Iml Th or g Th significant block oQ 0 As for the insignificant block, the interframe e, differential signal of the block is treated as 0.

0 a 20 Consequently, the average value, the amplitude 430 and the index 438 need not be transmitted in this case. The coding data 440 outputted from the vector quantization 0 "0"0 coding section 439 comprises the average value, the 0o 0oo.° amplitude 430, the block discrimination information 435 o ,25 and the index 438, but since the block discrimination information 435 only is valid in the case of the 4 25 0 12 insignificant block, the information generating amount can be controlled by the threshold value 422.

Since the interframe vector quantizer in the prior art is constituted as above described, the control range of the irformation amount is small. Consequently, if the information amount is suppressed to the minimum, the changed parts on the screen are left behind as the insign"'icant blocks, resulting in producing so-called "pin hole noise".

FIGS. 2 -1 34 are block diagrams showing a composition example of a vector quwitization coding device and a decoding device using vector quantization technology in the prior art disclosed, for example, in "Image High Efficiency Coding by the Vector Quantization" in the Technical Report of the Institute of Electronics 0 and Communication Engineers of Japan IT85-61 (1985). In 0, i FIG. 33, numeral 501 designates the input signal vectors, numeral 502 designates an average value separating ocircuit which sepa;ates the average value component within the vector from the input signal vectors, numeral 503 designates the average value within the vector, numeral 504 designates an average value coding section, 4 numeral 505 designates the average value separated input vectors, numeral 506 designates an inner product I, 3 operation section which finds the inner product value of the average value separated input vector and the 8 normalized output vectors as hereinafter described, 26 13 numeral 507 designates a code book ROM which stores a plurality of normalized output vectors, numeral 508 designates the address signals, numeral 509 designates the normalized output vectors, numeral 510 designates an address counter, numeral 511 designates the inner product value calculated in the inner product operation section 506, numeral 512 designates a maximum inner product detecting section which finds the maximum value among the plurality of inner product values, numeral 513 designates the correction amplitude defined by the maximum inner product value, numeral 514 designates the strobe signals, numeral 515 designates an amplitude coding device, numeral 516 designates an index latch which takes the address signals, numeral 517 designates the average value coding data, numeral 518 designates the amplitude coded data, numeral 519 designates the 0 index, numeral 520 designates a coding data multiplexing 00 aA I section, and numeral 521 designates the coded output 00 data.

20 In the composition example of the vector quantization decoding device in FIG. 34, numeral 522 designates a coded data demultiplexing section, numeral 0044 0 524 designates an amplitude decoding device, numeral 528 designates a code book ROM, numeral 525 designates the average value decoded value, numeral 526 designates the 04- 0 amplitude decoded value, and numeral 527 designates the Sdecoded vector.

00"laPe 4 r 27 14 The operation of the vector quantization coding will be described. The input vectors 501 (hereinafter referred to as constituted by the input signal system blocked every k pieces (k indicates integer being 2 or more) are processed in the average value separating circuit 502 according to the formulas shown downwards, and subjected to separation of the average value 503 (hereinafter referred to as within the vectors therefrom and transformed into the average value separated input vectors 505 (hereinafter referred to as The input vector S, the average value p within the vector, and the average value separated input vector X are expressed as follows: S [Sl, S2, S k 4 4 4) 4~n 4 4 *G 4)44 k S Z S (j 1, 2, k) j=l x. S. p 3 X [XI, X 2 Xk] i" 20 42 4.

0 44~ 4b 44 4l 4 4 The average value p is subjected to the high efficiency coding in the average value coding section 504, and converted into the average value coded data 527.

The average value separated input vector X is inputted in the inner product operation section 506, and converted 28 15 x1-.

through the inner product vector quantization coding process as hereinafter described into the correction amplitude 513 as hereinafter described and the index 519 as hereinafter described. The average value separated input vector X is normalized with its magnitude IXi E X. into a plurality of normalized input S j=1 3 vectors and N pieces (N being natural number) of normalized output vectors 509 [hereinafter referred to as Yi (i 1, 2, formed according to the statistical property of the normalized input vectors X* are writtin in the code book ROM 507. When the average value separated input vector X is inputted in the inner product operation section 506, the address counter 510 is reset and starts the counter operation of the period N. Then the normalized output vectors yi on the address, which are indicated by the address signals 508 outputted 00 b C from the address counter 510, are inputted sequentially 0000 Sfrom the code book ROM 507 into the inner product 0 a 'IO0 0 a operation section 506, and the inner product 511 (hereinafter referred to as P(x, i 1, 2, N) 0 between the average value separated input vector X and N pieces of the normalized output vectors yi is calculated 7" according to the following formula, and then outputted.

o 0 k -j 0 ooo o o 00 29 16 Among N pieces of the inner product P(x, yi; obtained by the calculation, the maximum inner product value P is max detected in the maximum inner product detecting section 512, and then the address signals 508 showing the address within the code book ROM 507 of the normalized output vector yi giving the maximum inner product value are taken in the index latch 516 at timing synchronized with the strobe signals 514. The taken-in address signals 508 are the index 519 to discriminate the prescribed normalized output vectors yi, and transmitted to the coding data normalization section 520. On the other hand, the maximum inner product value Pmax is given as correction amplitude 513 (hereinafter referred to as to simulate amount Jxj of the average value separated input vector x as shown in the following j formulas: So 2 1/2 1 y y li Y j ij 0 0 j=l Pmax P(x, Yi Il Ii cos i X Cos g 20 The correction amplitude g is subjected to the high efficiency coding by the amplitude coding device 515 and converted into amplitude coded data 518. In the coding data multiplexing section 520, the average value coded data 517, the amplitude coded data 518 and the index 519 are multiplied, and then transmitted as the coding device output data 521 according to the prescribed format.

30 17 The decoding operation will be described. The coding device output data 521 are separated in the coded data demultiplexing section 522 according to the prescribed format into the average value coded data 517, the amplitude coded data 518 and the index 519. The average value coded data 517 are decoded through the average value decoding device 523 and converted into the average value decoding value 525 (hereinafter referred to as In similar manner, the amplitude decoded value 526 (hereinafter referred to as are outputted from the amplitude decoding device 524. From the code book ROM 517 the normalized output vectors yi being on Sthe address instructed by the index 519 are read out, and the recording vectors 527 (hereinafter referred to 15 as to the input vector s are obtained through the 0 po rocess of the following formulas.

s constituted as above described, it is impossible thatS k io <o s. g Yij c 0Since the vector quanizer in the prior art is 00 the content of the code book is renewed during coding operation, thereby approximation of the decoded vector may be deteriorated to the unusual input vectors with different properties.

0 0 o 31 18

C

FIG. 36 shows an example of an image coding method in the prior art. In FIG. 36, the side A indicates the transmitting side and the side B indicates the receiving side.

In FIG. 36, numeral 601 designates an input buffer which inputs the digitized image signals and outputs them suitably to the coding section at the next stage, numeral 603 designates a frame memory which stores the image signals after coding and decoding before the present image signals by one frame, numeral 602 designates a subtractor which carries out the subtraction between the output of the input buffer 601 and the output of the frame memory 603, numeral 604 designates a quantization coding device which gives the quantization and coding to the output of the frame memory 603, numeral oo" 605 designates a quantization decoding device which 6 00 decodes the signals after the quantization coding, numeral ooo 606 designates an interframe adder which adds the moo 0:o quantization decoding output and the output of the frame memory 603, and writes the result to the frame memory 603, numeral 607 designates a variable length coding device which assigns the variable length code to the quantization coding output corresponding to the generating frequency of each code, numeral 608 designates a transmitting buffer which stores the variable length coding output, numeral 609 designates a transmitting buffer control section which monitors the control of 32- I 19 writing and reading in the transmitting buffer 608 and the storage amount of the transmitting buffer and then transmits the monitoring result to the input buffer 601, numeral 610 designates a dummy data adding section which adds the dummy data to the output of the transmitting buffer, and numeral 611 designates a line interface section.

Numeral 612 designates a line interface section on the receiving side, numeral 613 designates a dummy separating section which deletes the added dummy data, numeral 614 designates a variable length decoding section which decodes the variable length code, numeral 615 designates a receiving buffer which stores the signals after the variable length decoding, numeral 605' is a quantization decoding section which gives the uooo S1 quantization decoding to the output of the receiving o o0o0 buffer 615, numeral 603' designates a frame memory which :00 'Coo C' 0 o stores the decoded image signals before the present C 000 ooo image signals by one frame, and numeral 606' designates an interframe adder which adds the output of the quantization decoding section 605' and the output of the frame memory 603' and then writes the result to the frame memory 603' The operation of the device will be described.

The inputted image signals 701 are written to the input buffer 601. The input buffer performs writing and o reading by the unit of the image frame, but it has the 33 20 composition of double buffer because reading may be performed during writing.

The coded and decoded image signals 702 before the present image signals by one frame are outputted from the frame memory 603. In the interframe subtractor 602, the interframe differential signals 703 are obtained by subtracting between the present image signals 701' read from the input buffer and the image signals 702. The interframe differential signals 703 are encoded by the quantization coding device 604, and become the quantization coded signals 704. FIG. 37 shows an example of characteristics of the quantization coding device. The quantization coded signals 704 are inputted in the variable length coding device 707, and transformed into the variable length code 706 corresponding to the o frequency of each coded signal.

o so At the same time, the quantization coding signals o 704 are inputted in the quantization decoding device 605, o O and then are outputted as the coded and decoded differential signals 705. FIG. 38 shows an example of Scharacteristics of the quantization decoding device.

The coded and decoded differential signals 705 are *o inputted together with the image signals 702 into the interframe adder 606, and become the coded and decoded ooo 25 image signals 702' and are written to the frame memory 603 for the coding to the next frame.

04 34 r- 21 On the other hand, the variable length codes 706 are inputted in the transmitting buffer 608. The transmitting buffer outputs the data in accordance with the requirement from the transmission line side after storing the variable length codes over the definite amount, and has the composition of double buffer (buffer buffer because writing and reading must be performed at the same time. The transmitting buffer control section 609 controls writing and reading of the transmitting buffer. For example, when the buffer #1 is at writing operation and the buffer #2 is at reading operation, the transmitting buffer control section 609 monitors the storage amount of the buffer and if the storage amount becomes more than the prescribed set 15 value, the transmitting buffer control section 609 ono o00o demands ceasing of output of the data to the input buffer 601.

a 0 the Receiving the demands, the input buffer 601 ceases vu, the output of the data to the next stage. The transmitting buffer control section 609 detects the pause of the input data to the transmitting buffer 608, °Juo and ceases writing to the buffer #i1 and makes the situation of waiting for reading. The buffer #2 during reading ceases reading if the residual amount becomes S 25 less than the prescribed set value, and it waits for the buffer #1 to be in the situation of waiting for reading.

When the buffer #1 is in the situation of waiting for 22reading, the buffer 42 and the buffer f1 are read out continuously. The buffer #2 is in the situation of waiting for writing.when the residual amount becomes zero.

When the buffer #2 is in the situation of waiting for writing, the transmitting buffer control section 609 demands to start the output of the data to the input buffer 608.

In this process, before the buffer #1 gets in the situation of waiting for reading, there becomes the situation that the transmitting buffer 608 cannot output any data.

The dummy data adding section 610 outputs the data with the dummy data added thereto so as to continue the transmission of the data to the transmission line without break while the transmitting buffer 608 cannot output oou the data.

The data with the dummy data added thereto are o subjected to conversion of electric level in the i 20 transmission line interface section 611 so as to meet the characteristics of the transmission line, and then outputted to the transmission line. On the receiving 0o. side, the signals inputted through the transmission line 04C are subjected to phase conversion of electric level in 25 the transmission line interface section 612, and the oo dummy data added in the dummy data adding section 610 ai are cleared in the dummy separate section 613 thereby aa only the data about the images are outputted.

36 The output is processed in the variable length decoding section 614 by the reverse treatment with respect to that in the variable length coding section 607, and then inputted in the form of the quantization coded signals 704 into the receiving buffer 615.

The receiving buffer has the composition of double buffer, because writing and reading are performed at the same time. In the receiving buffer, the stored data are variable in amount so as to take matching with respect to time between the signal speed inputted from the transmission line side and the speed of the image decoding section at the rear stage.

For example, if the processing speed of the image decoding section at the next stage is low, the stored amount of the receiving buffer is increased. On the contrary, if the processing speed is high, the receiving buffer acts at the small stored amount.

o The quantization coded signals 704 are decoded by the quantization decoding device 605' and outputted as the coded and decoded differential signals 7051 in similar manner to the transmitting side.

The coded and decoded image signals 702' before the present decoding image by one frame are outputted from the frame memory 603', and are added to the coded and decoded differential signals 705' in the interframe adder 606', and the resulted signals are written as the coded and decoded image signals to the frame memory 603' and also outputted to outside.

37 Let the necessary time to decode one image memory on the receiving side be TD, and let the average time to encode one image memory on the transmitting side be Tc, and unless TD T the data are accumulated one after another in the receiving buffer resulting in overflowing.

Since the transmitting side transmits the variable length coding data, the number of the data transmitted by one frame is not kept constant.

In other words, the time interval TB at which the code corresponding to the lead of the image frame can be

T

B

T

D once in a while.

Accordingly, unless T D min T B on the receiving side, it causes the overflowing of the receiving buffer.

Since the image coding device in the prior art is constituted as above described, one frame decoding time

T

D on the receiving side is inevitably set to a small value so that T min T As a result, the scale of the device on the receiving side becomes much larger than that on the transmitting side.

SUMMARY OF THE INVENTION It is an object of the present invention to substantially alleviate at least one of the abovementioned disadvantages in the prior art.

According to one aspect of the invention there is provided an image signal progressive build-up encoder/ decoder comprising: a substractor which estimates residual signal 38 44 vector showing a residual between one of input signal vectors made from a series of input image signal by means of dividing into lattice-shaped plural samples m x n n: positive integer) and an input signal vector of the previous frame; an average value encoder/decoder which calculates average value within block of residual signal vector, and performs redundancy reduction coding of the average value; a normalized vector quantization encoder/decoder which utilizes the residual signal vector as input vector and subtracts the average value from each element of the input vector and obtains the normalized output vector having the maximum inner product value to the input vector among a set of normalized output vectors with average value 0, amplitude 1 generated so that total of distortion is minimized based on the distribution of normalized input vectors of which amplitude becomes 1, and obtains index to indicate the normalized output vector, and also o performs redundancy reduction coding and decoding of the amplitude gain of the input vector given by the maximum inner product value, and the decoded amplitude gain is multiplied by the detected normalized output vector thereby the amplitude reconstructed output vector can be obtained; a sample value encoder/decoder which performs S redundancy reduction coding and decoding of m x n samples in the 4 ,residual signal vector sample by sample; a switch which adaptively controls ON/OFF operation of the average value encoder/decoder, the normalized vector quantization encoder/decoder and the sample value encoder/decoder 4 based on the control signal frame by frame; 26 a vector reconstructor which selects adaptively the decoded average value, the decoded residual signal vector by adding the decoded average value to the amplitude reconstructed output vector, and the decoded sample value based on the control signal frame by frame control signal, and then outputs them as the decoded vector; and, a coding controller which generates the control signal and enables the adaptive control operation of the switch, each encoder/decoder and the vector reconstructor corresponding to the number of coded samples each frame.

According to another aspect of the invention there is provided an image signal progressive build-up encoder wherein to same one input image frame, the input signals are performed redundancy reduction coding and decoding and reconstructed image signals are delayed by one frame period, and the residual signals between the input image signals and the delayed signals are a 0 0 S 0 performed redundancy reduction coding and decoding frame by frame respectively and operation is repeatedly performed thereby high So quality and resolution image is built up progressively as time 20 progresses, said encoder comprising: oo a vector/subvector transformer which forms latticeshaped am sample x bn line b, m, n: natural number, and am ao a x m, and bn b x n) residual signals into an L-dimensional (L am x bn) vector, and forms lattice-shaped m x n average ~25 values calculated within the blocks of a sample x b line residual 4 signals respectively into a K-dimensional (K m x n) subvector; an average value encoder and decoder which performs redundancy reduction coding and decoding of the arithmetic means of the sample within the residual signal subvector; 39A 27

I

K-dimension normalized vector quantization encoder and decoder which treats the residual signal subvector as K-dimension input vector, and performs vector quantization of the input vector through the inner product operation of K dimensions into K-dimension normalized output vector of average value 0 and amplitude 1, and performs redundancy reduction coding and decoding of the amplitude gain of the residual signal subvector given by the inner product value between normalized output vector and the input vector; a subvector/vector de-transformer which arranges samples within the decoded K-dimension residual signal subvector obtained by multiplying the normalized output vector and the decoded amplitude gain, and each element of the K-dimension amplitude reconstruction output vector corresponding to latticeshaped m sample x n line subvector is added to the decoded average value, thereby performs interpolation of the decoded i o residual signal vector having the L dimensions; and performs decrease size of the lattice-shaped block of the residual signals S o 0 o step by step and to execute the coding and. decoding operation 4 4 r i 12Q repeatedly 4 4 I easW66 39B 4£ «0 a4 28 i -~IUIT*i~-Pi~iiy- BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram illustrating inner composition of a motion compensation circuit in a first embodiment-of the invention; FIG. 2 is a diagram illustrating steps of process of the motion compensation circuit in FIG. 1; FIG. 3 is a block diagram of a transmitting section of an image coding transmitting section in the prior art; 00.0 0 0)0 P 0o 0 0 0 COO 000Q 0000 000 0

COW"

09 0 0 V 0 0 C C GO(I 0 0 U FIG. 4 is a block diagram illustrating inner composition of the motion compensation circuit in FIG. 3; FIG. 5 is an arrangement diagram of searching vectors in the motion compensation circuit in FIG. 3; FIG. 6 is a block diagram of a coding section of an image signal progressive build-up coding and decoding device in a second embodiment of the invention; FIG. 7 is a block diagram illustrating composition of the decoding section in FIG. 6; FIG. 8 is a diagram illustrating inner product vector quantization; FIG. 9 is a diagram illustrating transmitting sequence of coded output data in this embodiment; FIG. 10 is a block diagram of a coding section of an image signal progressive build-up coding and decoding 25 device in the prior art; FIG. 11 is a block diagram illustrating composition of a decoding section in FIG. 40 4~11 I-JIIll~t j~~ FIG. 12 is a block diagram illustrating composition of a transmitting section of an interframe coding device in a third embodiment of the invention; FIG. 13 is a block diagram illustrating composition of the temporal filter in FIG. 12; FIG. 14 is a block diagram illustrating composition of the coding control section in FIG. 12; FIG. 15 is a diagram illustrating operation of coding control in this embodiment; 1'iG. 16 is a block diagram illustrating composition of a transmitting section of an interframe coding device in the prior art; FIG. 17 is a block diagram illustrating composition of the coding control section in FIG. 16; FIG. 18 is a diagram illustrating operation of coding control in the interframe coding device in FIG. 16; o a FIG. 19 is a block diagram illustrating composition of a transmitting section of an image signal progressive build-up coding device in a fourth embodiment of the invention; FIG. 20 is a diagram illustrating operation of the a s vector/subvector converter in FIG. 19; OIa FIG. 21 is a diagram illustrating operation of the subvector/vector converter in FIG. 19; FIG. 22 is a diagram illustrating an example of control means of the coding control section in FIG. 19; 41 30 FIG. 23 is a block diagram illustrating composition of a transmitting section of an image signal progressive build-up coding device in the prior art; FIG. 24 is a diagram illustrating operation principle of an inner product vector quantizer; FIG. 25 is a block diagram illustrating composition of an interframe vector quantization coding device in a fifth embodiment of the invention; FIG. 26 is a diagram illustrating relation between the first stage vector quantization and the second stage vector quantization in the interframe vector quantization coding device in FIG. FIG. 27 is a block diagram illustrating composition of the first stage vector quantization coding section of the interframe vector quantization coding device; °FIG. 28 is a block diagram illustrating composition li of an interframe vector quantization coding device in the prior art; FIG. 29 is a block diagram illustrating composition of the vector quantization coding section in FIG. 28; FIG. 30 is a block diagram illustrating composition of a coding section of a dynamic vector quantizer in a sixth embodiment of the invention; o 4 FIG. 31 is a block diagram illustrating composition of a decoding section of the dynamic vector quantizer in FIG.

^BSS

42 1 31

I

FIG. 32 is a block diagram illustrating composition of the dynamic code book in FIG. FIG. 33 is a block diagram illustrating composition of coding section of a vector quantizer in the prior art; FIG. 34 is a block diagram illustrating composition of a decoding section in FIG. 33; FIG. 35 is a block diagram of image coding transmission system according to the invention; FIG. 36 is a block diagram of image coding transmission system in the prior art; FIG. 37 is a diagram illustrating an example of characteristics of the quantization coding device; FIG. 38 is a diagram illustrating an example of characteristics of the quantization decoding device; and FIG. 39 is a diagram illustrating operation state of the transmitting buffer.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A first embodiment of the invention will be described referring to FIG. 1 FIG. 2.

20 In FIG. 1, reference numeral 20 designates a quantizer which quantizes the average value of the input block signals, numeral 23 designates a block selector which changes and outputs a block where previous frame block signals and picture elements within the block are 25 0 (hereinafter referred to as "0 block") and an average value block, and numeral 25 designates an index selector which changes and outputs motion vector index and o 0 o 0000 o a

D

000 VOO000 0 0 00 00 0 000 0 0000 0 0 0 00 0 o a 0 00o 0 4 0 0 00 0 0 60 0000~ 00 0 ea o 00 43 c 32 quantized level index. Numerals 1 18 are similar to the prior art.

The operation of the device will be described.

In FIG. 1, the interblock matching distortion operation and the comparison operation finish in serial processing with times per one input block when the number of the searched vectors is made L (L being plus integer). An example of processing steps is shown in FIG. 2.

Let the input block signals 1 be S (Sl, S 2 SK}, and let the reference block signals 24 be S' S'i 2 and the calculation algorithm ill 1i 1K of the matching distortion d. is similar to the prior art.

In the first processing, the block selector 23 outputs block. In this case, an output 17 of a distortion operator 16 is represented by following Sformula, and this value becomes the average value m of 00 the input signal blocks. However, the matching j o 20 distortion operation uses the luminance signals only.

K

m= E IS 0 oooj=1 0K z

S.

o 0 j=l 3 0 The average value m is quantized in the quantizer and the quantization average value m 22 is inputted 0 o 44 in the block selector 23. On the other hand, the quantization index 21 indicating the quantized level of the quantized average value is outputted to the index selector 25. Let the number of the quantized level be M (M being plus integer), and the quantized index from to is assigned at each level.

In the second processing, the block selector 23 outputs the average value block m having the quantized average value m as value of each picture element within the block. The output 17 of the distortion operator 16 in this case is represented by following formula, and this value is made d o

K

d o Is m l j=l 0 oo...o where 0 is given as the vector index of the average o o 15 value block.

0 In the third processing and so forth, the distortion 0 0 0 oo operation and the comparison operation are the same as 0000 noted above. That is, the block selector 23 outputs the previous frame block one after another.

Finally, the output 19 of the comparator 18 becomes 0 0 o 0 0 0 the index of the block which gives the minimum matching distortion among pieces from d o to d L of the 0 o0 a matching distortion. In this case, the vector index 0 f l corresponding to each reference block is assigned as 440 shown in FIG. 2.

o o 4 45 ii I 34 In the index selector 25, when the comparator output index 19 is 0, when the average value block m is selected, the quantized index which newly indicates the quantized level of the quantized average value m [the value being from to is outputted as the vector index 5. In other cases, the value of the comparator output index 19, as it is, is outputted as the vector index In this embodiment, although the differential absolute sum is represented as the interblock matching distortion, Euclid norm may be used in place of it, and it is possible to increase the priority of the specific reference block by giving weight to the matching distortion in each reference block.

A second embodiment of the invention will be described referring to FIG. 6 FIG. 11.

C.aoo In FIG, 6, numeral 101 designates input signal 0 vectors which block the input image signal system at 0 o 00 each sample m x n n being integers), numeral 102 o00 designates a subtractor which estimates residual signal vector between the input signal vectors and previous stage decoding vectors delayed by one frame, numeral 103 00 designates the residual signal vectors, numeral 104 0 designates a switch which controls ON/OFF operation of a 0 25 sample value coding and decoding device, an average 0' value coding and decoding device and a normalized vector i quantization coding and decoding device according to 0 6; 46 35 control signals from a coding control section, numeral 105 designates a sample value coding and decoding device which gives coding and decoding to sample value in the prescribed coding mode controlled according to control signals from the coding control section per each sample, numeral 106 designates an average value coding and decoding device which finds the average value within the block per each vector, and gives coding and decoding to the average value in the prescribed coding mode controlled according to control signals from the coding control section, numeral 107 designates a normalized vector quantization coding and decoding device which gives the inner product vector quantization in the prescribed coding mode controlled according to control signals from the coding control per each vector, numeral 108 designates coded data of the sample value, numeral 109 designates decoded value of the sample value, numeral 110 designates coded data of the average value, numeral 111 designates decoded value of the average value, numeral 112 designates coded data of the amplitude and the output vector index, numeral 113 designates output vectors subjected to amplitude reconstruction, numeral 114 designates a code assignment circuit which assigns codes to each coding data according to control signals from the coding control section, numeral 115 designates output signals of the coding device, numeral 116 designates a vector i 47 36 IC LtJ3rl*i~7 nreconstructed circuit which obtains residual signal decoded vectors in the prescribed operation according to control signals from the coding control section, numeral 117 designates residual signal decoded vectors, numeral 118 designates an adder which adds the residual signal decoding vectors and the previous stage decoding vectors delayed by one frame, numeral 119 designates decoded vectors, numeral 120 designates a frame memory which delays the decoded vector by one frame, numeral 121 designates a coding control section which generates control signals to control each coding mode of the switch, the sample value coding and decoding device, the average value coding and decoding device and the normalized vector quantization coding device corresponding to error between the input signal vector and the decoded vector and the number of coding stages, numeral 122 designates control signals from the coding control section, and numeral 123 designates coding stage indicating signals representing the number of coding with the frame unit.

In FIG. 7, numeral 124 designates a code assignment circuit which carries out the code assignment inversion according to control signals from the coding control section, numeral 125 designates a sample value decoding device which carries out the sample value decoding by the prescribed decoding mode controlled according to control signals from the coding control section pr each 0 0 000 C S 0005 00 o o 0 O 004

IS

a I I a 0 I 0 48- 37 sample, numeral 126 designates an average value decoding device which carries out the average value decoding by the prescribed decoding mode controlled according to control signals from the coding control section, and numeral 127 designates a normalized vector quantization decoding device which carries out the vector quantization decoding by the prescribed decoding mode controlled according to control signals from the coding control section.

The operation of the device will be described.

In FIG. 6, in the previous stage coding, the frame memory 120 storing the previous stage decoding results remains cleared, and the input signal vectors 111, as they are, pass through the subtractor 102 and are outputted as the residual signal vectors 113. The switch 104 renders only the average value coding and decoding device 106 to ON-state according to the control signals 122 from the coding control section. In the oc average value coding and decoding device 106, the average S 20 value within the block is calculated per each vector, and subjected to coding and decoding in the coding mode controlled according to the control signals 122, and the coded data 110 of the average value and the decoded value 111 are outputted. The coded data 110 of the average value are transformed by the code assignment circuit 114 into suitable code words, and then transmitted together Swith the control signals 122 in sequence of the first -49 38 stage transmission data shown in FIG. 9. The vector reconstruction circuit 116 outputs the residual signal decoded vectors 117 having all m x n samples as the decoded value 111 of the average value according to the control signals 122 from the coding control section.

The residual signal decoded vectors 117 pass through the adder 118, and are written as the decoded vectors 119 into the frame memory 120. At the second stage coding, in the subtractor 102, the residual signal vectors 103 by subtraction of the previous stage decoded vectors from the input signal vectors 101 are obtained. The switch 104 renders the average value coding and decoding device 106 and the normalized vector quantization coding and decoding device 107 to ON-state according to the control signals 122 from the coding control section. In the average value coding and decoding device 106, the average value within the block is calculated per each o vector, and the coded data 110 of the average value and the decoded value 111 are outputted in the coding mode 4O4~ controlled according to the control signals 122. In the normalized vector quantization coding and decoding device 107, the inner product vector quantization is performed, and the coded data 112 of the amplitude and the output vector index and the output vector 113 regenerated in terms of the amplitude are outputted.

The operation principle of the inner product vector Squantization will be described referring to FIG. 8.

II~

In the inner product vector quantization, the average value separation and normalization is given, and a set of the normalized output vector yi arranged on the unit superspherical surface of the multidimensional signal space, Y Y2' Y-N is used. That is, the normalized output vector yi satisfies the following conditions simultaneously: I Yj] 1, j Y.

j=l

I

The input signal vector x is converted through the operation process of the following formulas into the normalized output vector yi which gives the maximum inner product value to the input signal vector x, and the maximum inner product value is given as the amplitude g of the input signal vector x. a u> U Q 4 4 4 4 444 if I(x, i) I(X, Y k for all

K

i) jYij) j=l 44 It 4 a 4 4c 4 4t 4 a 4 a a 4 a 4444 i 0 1 a I U 1i g I(x, Yi) llil cosei X Cos i The amplitude g found as the scalar quantity is 20 encoded independently, and the coded result together with the index i of the normalized output vector yi are outputted as the coded data. At the same time, the 51

L

of the sample within the residual signal subvector; 39A normalized output vector yi is multiplied by the decoded value g of the amplitude g thereby the amplitude reconstructed output vector yi* is obtained.

A

-ii g yi The coded data 110, 112 are transformed by the code assignment circuit 114 into suitable code words, and are transmitted together with the control signals 122 in sequence of the second stage transmission data shown in FIG. 9. In the vector reconstruction circuit 116, the average value decoded vectors having all m x n samples as the decoded value 111 o. the average value and the amplitude reconstructed output vectors 113 are added according to the control signals 122 from the coding control section, and the residual decoded vectors 15 117 are outputted. The residual signal decoded vectors o 0 °ooo 117 are added in the adder 118 to the previous stage o decoded vectors, and the decoded vectors 119 as the o. adding result renew the frame memory 120. At the third a 4 stage coding, the residual signal vectors 103 are outputted from the subtractor 102 .n similar manner to j the second stage coding. The switch 104 renders only the sample value coding and decoding device 105 to ON-state according to the control signals 122 from the 0.0 0~ °C coding control section. In the sample value coding and 0 S 25 decoding device 105, coding and decoding of the sample value are executed per each sample within the vector in o0 52- I, 39B the coding mode controlled according to the control signals 122, .tid the coded data 108 of the sample value and the decoded value 109 are outputted. The coded data 108 of the sample value are transformed by the code assignment circuit 114 into suitable code words, and transmitted together with the control signals 122 in sequence of the third stage transmission data shown in FIG. 9. In the vector reconstruction circuit 116, according to the control signals 122 from the coding control section, the residual signal decoded vectors 117 composed of the decoded value 109 m x n pieces of the sample values are outputted. The residual signal decoded vectors 117 are added in the adder 118 to the previous stage decoded vectors, and the decoded vectors 119 as adding result renew the frame memory 120. The same coding operation as that of the third stage is repeated o gs afterwards, and the coded data 108 of the sample value at each stage are transmitted so as to renew the frame 0 0 oQ memory 120.

On the other hand, in the decoding section, when the decoding starts, the frame memory 120 storing the previous stage decoded result remains cleared, and the coded output signals 115 obtained in the coding section ao are subjected to the code assignment process in the code o 25 assignment circuit 124 and obtained as each coded data.

oEach coding data is decoded by each of the decoders 125, S126, 127 according to the prescribed mode according to -53-

_I

the control signals 122 transmitted at the same time from the coding section, and then outputted as the residual signal decoding vectors 117 from the vector reconstruction circuit 116. The residual signal decoded vectors 117 are added to the previous stage decoded results in the adder 118 so as to renew the frame memory 120.

In the coding control section 121, the average of the error between the input signal vector 101 and the decoded vector 119 in each stage is estimated in one frame period, and in accordance with the average error and the coded stage indicating signals 123, the control signals 122 for feedback control of changing of the switch 104 and changing of the average value coding mode, the normalized vector quantization coding mode and the sample value coding mode in the next stage coding are generated and outputted.

Let the input signal vector be S and the decoded

A

vector be S, then the error e may be defined, for example, by the following formula:

F

1 K 2]1/2 e E j=l In this embodiment, although the average of the error between the input signal vector 101 and the decoded vector 119 in one frame period is used in the coding control section 121 and the feedback control is executed, 54 -41 ~CI the error between the residual signal vector 103 and the residual signal decoded vector 117 may be used, and in place of the average of the error in one frame period, the arount of all coded information of one frame period may be used so as to obtain the same effect as the embodiment.

FIG. 12 is a block diagram illustrating composition of a transmitting section of an interframe coding device in a third embodiment of the invention. In FIG. 12, numeral 201 designates a digitalized motion image signal system, numeral 202 designates a temporal filter, numeral 203 designates interframe differential signals obtained in the temporal filter 202 and subjected to the non-linear weighting, numeral 204 designates a motion amount estimation section, numeral 205 designates estimated motion amount obtained in the motion amount estimation section 204, numeral 206 designates motion image signal system which is processed by the temporal filter 202 and subjected to conversion of the resolving power or the speed, numeral 207 designates a subtractor for obtaining interframe differential signals, numeral 208 designates interframe predicting signals formed from the past-time frame after finishing the coding already, numeral 209 designates interframe differential signal series, numeral 210 designates a block discrimination section which quantizes the interframe differential signal 209 being the predicting error as zero, and 55 ~tss~8a~ a I i -42 discriminates whether the coding processing at the next stage must be performed or not block by block unit, numeral 211 designates threshold value for the block discrimination, numeral 212 designates a coding control section which determines the threshold value, numeral 213 designates a coding and decoding section which encodes and decodes a block discriminated to have the significant predicting error in the block discrimination section 210, significant block, numeral 214 designates decoded predicting error signals obtained in the coding and decoding section 213, numeral 215 designates an adder which adds the predicting signals 208 and the decoded predicting error signals 214, numeral 216 designates decoded image signals, numeral 217 designates a frame memory which forms the interframe predicting signals 208 using the decoded image signals 216, numeral 218 designates coded data obtained in the coding and decoding section 213, numeral 219 designates a variable length coding section which gives the variable length coding to the coded data 218, numeral 220 designates a buffer where the data series subjected to the variable length coding in the variable length coding section 219 is transmitted at the definite transmission speed, numeral 221 designates data by counting the variable length coded data per each frame (information amount per frame), numeral 222 designates a line interface where the data ANO system smoothed in the buffer 220 is transmitted to the 56

L

0 II' 43 transmission line, and numeral 223 designates transmitting signals. FIG. 13 is a block diagram illustrating composition of the temporal filter 202 in FIG. 12.

In FIG. 13, numeral 224 designates a subtractor which finds difference between frames, numeral 225 designates image signals of the past-time frame, numeral 226 designates interframe differential signals, numeral 227 designates a non-linear weighting circuit which provides weight to the interframe differential signals 226, numeral 228 designates an adder which adds the interframe differential signals 203 weighted and the image signals 225 of the past-time frame, numeral 229 designates temporal filter output signals obtained by the adder 228, and numeral 230 designates a frame memory which performs frame delay, resolving power conversion or speed conversion.

FIG. 14 is a block diagram illustrating composition of the coding control section 212 in FIG. 12. In FIG. 14, numeral 231 designates a table ROM, numeral 232 designates a register which delays the threshold value 211 at the frame period, and numeral 233 designates threshold value delayed by the register 232.

FIG. 15 is a diagram illustrating characteristics to be written in the table ROM 231.

The operation of the device will be described. The e digitalized image signal system 201 is first inputted to 57- 0 8 0 44 the temporal filter 202. In the temporal filter 202, subtraction to the previous frame signal 225 is performed by the subtractor 224 and the output is converted into the interframe differential signal 226.

The interfrare differential signal 226 is made the weighted signal 203 by the non-linear weighting circuit 227, and added to the previous frame signal 225 by the adder 228 into signal 229 subjected to the temporal filter processing. The signal 229 is stored in the frame memory 230, and used in the filter processing of next frame. The frame memory 230 not only gives the frame delay for the temporal filter, but also has function of converting the resolving power or the speed to meet the specification of the coding section or the o 15 transmission speed and reading it as the coding input o image signals 206. When the transmission speed is low, ogcoo the coding frames are thinned out, so-called frame 0oo 0o o0 cutting is performed. Then only the frames for coding 000 o0oo are read from the frame memory 230, and other frames rem, "/ed by the frame cutting are overwritten on the memory. Consequently, the time relation between the 0 0 0 o image signal series 201 and the previous frame signal o 0 225 becomes relation of "frames which are encoded o continuously". The weighted interframe differential r 25 signal 203 is integrated by one frame in the motion amount estimation section 204, and used as the estimated o" :o motion amount 205 for determining the threshold value as 0 0 58 Od 0 45 hereinafter described. The signal 206 read from the frame memory 230 is subjected to subtraction to the interframe predicting signal 208 by the subtractor 207, and converted into the interframe differential signal 209. The interframe predicting signal 208 is formed using the reconstruction image signals of the past-time frame after finishing the coding and the local decoding in the transmitting section already, and method of the motion compensation or the like may be used in this case. Since the interframe differential signal 209 gets quite close to 0 when the subject has no variation or motion, the significant block and the insignificant block are discriminated in the block discrimination section 210 as above described, and regarding the J 15 insignificant block the data indicating it as insignificant only are transmitted thereby the "information amount can be compressed. In order to o0.

discriminate blocks, the absolute value sum of the interframe differential signal system formed in blocks is estimated, and then compared with the threshold value 211. Let the interframe differential signal series in blocks be E. (j 1, 2, and the threshold value be Tn, then the block discrimination is performed as follows: k if K E IEjl T insignificant block j= 1 n 59 446 46 k if K-1 j T significant block j=l n Regarding the block discriminated as a significant block, further the interframe differential signal 209 is encoded. In the coding and decoding section 213, the significant block is encoded and then decoded, and the decoded predicting error signal 204 and the coded data 218 are outputted. There are various sorts of the coding and decoding methods. However, since these have no direct relation to the essence of the invention, the detailed description shall be omitted here. The decoding predicting error signal 214 is added to the interframe predicting signal 208 by the adder 215 so that the decoded image signals 216 is formed. The decoding image signals 216 are stored in the frame memory 217, and used to form the interframe predicting signal in the next frame and so forth. On the other hand, the coded data 218 is assigned with code words corresponding to the frequency of each data in the variable length coding section 219. In the buffer 220, the speed is smoothed so that the coded data series subjected to the variable length coding is transmitted at the constant transmission speed, and the coded data series in variable length coding is counted per each Sframe and outputted as the information amount 221 per frame to the coding control section 212. The line 47 interface 222 transmits the variable length coded data with speed smoothed as the transmitting signals 223 to the transmission line.

In the coding control section 212, using the estimated motion amount 205, the information amount 221 and the threshold value 233 supplied with the frame delay by the register 232 and referring to the table ROM 234, the new threshold value 211 is transmitted.

Let the estimated motion amount 205 be M the past n threshold value 233 be Tnl, and the information amount 221 in the frame coded using Tn 1 be Bn-l' then the new threshold value T (211) is obtained as shown in FIG. n Between the threshold value and the information amount, there is hyperbolic relation as shown by four curves in FIG. 15. The four characteristic curves show o o an example, and vary depending on whether the motion of 0 "the subject is large or small. First, from B and n-i Tnl' one characteristic curve is selected among a plurality of curves stored in the table ROM 231. The characteristic curve indicates what degree of the motion is included in the frame which is encoded using the 04threshold value T and generates the information of C0 n-i Bn-l' Since the estimated motion amount Mn (205) o0 estimates the motion amount of the frame to be encoded oa hereafter, the motion characteristic curve is suitably Stransferred using M n If M is large, the curve is ~ntransferred to the characteristics with large motion; transferred to the characteristics with large motion; 61

'I

44 48 if M is small, the curve is transferred to that with n small motion. Subsequently the point with the information amount being B* is searched along the determined curve. In this case, B* is the information amount allowed per one frame corresponding to the transmission speed. If the point with the information amount being B* is determined on the selected curve, the threshold value on the point is read as T n That is, the characteristic curve corresponding to the motion amount is selected from relation between the threshold value Tnl of the frame after finishing the coding and the information amount Bn-l* Regarding the frame to be coded hereafter, the characteristic curve is corrected using the estimated motion amount, and control is 15 performed so that the threshold value required to attain Sthe intended information amount is obtained as the new 0 threshold value T from the curve.

n 00 0 In this embodiment, although the temporal filter oo 000 processing or the frame delay by the frame memory 230 to convert the resolving power and the speed is used as means for obtaining the interframe differential signal o D o00 203 being the reference signal to estimate the motion amount, of course, the frame memory may be prepared only for estimating the motion amount.

A fourth embodiment of the invention will be described referring to FIG. 19 FIG. 22. FIG. 19 is a block diagram illustrating composition of a transmitting 62

I

section of an image signal progressive build-up coding device in the fourth embodiment of the invention. In FIG. 19, numeral 304 designates a vector/subvector converter which reduces the dimension number of the input vector from L am x bn), b, m, n being natural number) into K m x n) and forms subvector, numeral 314 designates a subvector/vector converter which uses a sample value within the subvector of the dimension number K m x n) and forms the vector of the dimension number L am x bn) in interpolation reconstruction, numeral 305 designates residual signal subvector, numeral 313 designates residual signal decoding subvector, numeral 322 designates a coding control section which produces control signals 323 indicating parameters a, b, 15 m, n to determine the dimension number L and K of the c"°o vectors and the threshold value corresponding to coded stage number 321, and numeral 325 designate-:.

discrimination information which indicates whether the coding and decoding to the residual signal vector 303 should be executed or not. Other numerals 301 303, 306 312, 314 320, 324 are similar to those in the °o device of the prior art.

Q 0 0 The operation of the device will be described. In °o FIG. 19. at the first stage coding, the frame memory 318 o 25 remains cleared. The input signal vector 301 of the *sgs dimension number L (am x bn) is not subjected to any 9l processing in the subtractor, but outputted as it is as 63 L <i the residual signal vector 303. The residual signal vector 303 is inputted to the vector/subvector converter 304, and subjected to the conversion processing of the dimension number as hereinafter described and converted into the residual signal subvector 305 of the dimension K m x n) and then outputted. In the vector/subvector converter 304, the residual signal vector 303 and the residual signal subvector 305 are represented respectively as follows: input vector; s= [sl, s 2, s r s rE{l, 2, L) subvector U= [u l u 2 uj, I u j6{l, 2, K) The sample value u. in the subvector is given by value 3 of samples in the input vector averaged per a x b samples as shown in the following formulas: o o r 15 u E s S3 a b r °°oO0,o 0r=r 1 1 oo o a o r (j 1) x a- b 1 0i 0 a A 4 r j x a b FIG. 20 shows relation between the input vector and the subvector when a b m n 4 corresponding to Sada the image signal system of two dimensions.

The residual signal subvector 305 is inputted to a 4 a a 4a A the average value coding device 306 and the normalized vector quantization coding device 307, and subjected to the same processing as that of the prior art. As a 64 B~ 1 i a result, the average value coded data 308 and the average value decoded value 309 are outputted from the average value coding device 306, and the vector quantization coded data 310 and the amplitude constructed output vector 311 are outputted from the normalized vector quantization coding and decoding device 307, and the average value decoded value 309 and the amplitude reconstructed output vector 311 are added in the first adder 312, thereby the residual signal decoded subvector 313 is obtained. The residual signal decoded subvector 313 of K dimensions is subjected to the following processing through the subvector/vector converter 314, and converted into the residual signal decoded vector 315 of L dimensions. In the subvector/vector converter 15 314, the residual signal decoded subvector 313 and the 0 .0 residual signal decoded vector 315 are represented o respectively as follows: Ssubvector ;u [u u u u K j6(l, 2, K) output vector; s [sl, s2, s sL] rEl, 2, L The sample s in the output vector is given in that the same samples in the subvector are arranged repeatedly Sper a x b samples as shown in the following formulas: SSr= u. r6{l, 2, L} r Sj =INT (r l)/a-b 1 INT(*) represents conversion to integer by emission of pt fractions 65 i.

FIG. 21 shows the sample arrangement in two dimensions of the subvector corresponding to samples in the output vector when a b m n 4.

The residual signal decoded vector 315 is added in the second adder to the previous stage decoding vector 319 delayed by one frame in similar manner to the device in the prior art, and written as the decoding vector 317 in the frame memory 318 and used for the coding in the next stage. The average value coded data 318 and the vector quantization coded data 310 are supplied to the code assignment circuit 320.

At the second stage and so forth, to the residual signal vector 303 between the input signal vector 301 and the previous stage decoding vector 319 stored in the 15 frame memory 318, the above-mentioned coding processing is executed in sequence repeatedly under following control: The coding control section 322 produces the parameters a, b, m, n to determine the dimension number of each of the residual signal-vector 303, the residual signal subvector 305, the residual signal decoded subvector 313, the residual signal decoded vector 315 in the coding processing and the control signal 323 indicating the threshold value as hereinafter described 25 corresponding to the coded stage number 321, and supplies the control signals 323 to the vector/subvector converter 304, the subvector/vector converter 314 and the code o o 0 0 0 00 0 0 O o 0 g~o G- c ao o 9 0 00 900 0 O 0 0 0 0 0 o o3 0 00 0 0 Xr *L 1 I 1h 66 assignment circuit 320. FIG. 22 shows an example of setting method of the dimension number L am x bn) of the residual signal vector 303 at the first stage and the second stage corresponding to the image signal system of two dimensions. At the second stage coding processing and so forth, the vector/subvector converter 304 compares the average square value per sample within the residual signal vector 303 with the threshold value supplied from the coding control section 322 in magnitude.

As a result of comparison, if the average square value is larger than the threshold value, the coding and decoding processing is executed. If not, the coding and decoding processing is not performed, but all sample values within the residual signal decoded vector 315 outputted from the subvector/vector converter 314 is made 0. The discrimination information 325 indicating result of the magnitude comparison is supplied from the vector/subvector converter 304 to the code assignment circuit 320 and the subvector/vector converter 314.

In the code assignment circuit 320, the control signal 323, the discriminationinformation 325, the average value coded data 308 and the vector quantization coded data 310 are converted into suitable code words, and then transmitted as the coding output data 324.

In this embodiment, although a plurality of samples of the input vector are combined and averaged and made samples of the subvector in the operation of the vector/ 67 L. I subvector converter, samples within the input vector may be extracted according to suitable subsample pattern and made samples of the subvector, and further a smoothing filter for the band limiting may be inserted in the cou o o 0 00 o 0 0 04 input stage.

A fifth embodiment of the invention will be described referring to FIG. 24 FIG. 28. FIG. 25 is a block diagram illustrating composition of a coding section of an interframe vector quantization device.

In FIG. 25, numeral 401 designates input image signal system, numeral 402 designates a subtractor which performs subtraction to interframe predicting signals, numeral 403 designates interframe predicting signals, numeral 404 designates interframe differential signals, 15 numeral 405 designates a first stage vector quantization coding section, numeral 406 designates first stage coding data, numeral 407 designates a first stage vector quantization decoding section, numeral 408 designates first stage decoding signals, numeral 409 designates a subtractor which finds difference between the interframe differential signals 404 and the first stage decoded signals 408, numeral 410 designates first stage error signals, numeral 412 designates a second stage vector quantization coding section, numeral 412 designates 25 second stage coded data, numeral 413 designates a second stage vector quantization decoding section, numeral 414 designates second stage decoded signals, numeral 415 t a4 a It a c o 0 Q

CC)

68 I ,r designates an adder which adds the first stage decoded signals 408 and the second stage decoded signals 414, numeral 416 designates decoding interframe differential signals, numeral 417 designates an adder which adds the interframe predicting signals 403 and the interframe differential signals 416, numeral 418 designates decoded image signal system, numeral 419 designates a frame memory which supplies the decoded image signal system 418 with the frame delay and forms the interframe predicting signals 403, numeral 420 designates a variable length decoding section, numeral 421 designates a buffer for the speed smoothing, numeral 422 designates threshold value, numeral 423 designates a line interface and numeral 424 designates transmitted signals.

15 FIG. 26 is a diagram illustrating relation between the first stage vector quantization and the second stage vector quantization. FIG. 27 is a block diagram eo illustrating composition of the first stage vector quantization coding section 405 in FIG. 25. In FIG. 27, numeral 425 designates an average value and amplitude operation section, numeral 426 designates average value, a numeral 427 designates average value and amplitude, numeral 428 designates an average value separation and o normalization section, numeral 430 designates average value and amplitude, numeral 429 designates normalized vectors, numeral 431 designates a code book which stores output vectors, numeral 432 designates output vectors, 69 I- numeral 433 designates a distortion operation section which calculates distortion between the normalized vectors 429 and the output vectors 432, numeral 422 designates threshold value, numeral 434 designates a block discrimination section, numeral 436 designates distortion calculated in the distortion operation section 433, numeral 437 designates a minimum distortion detecting section which detects the minimum value of the distortion 436, numeral 435 designates block discrimination information, and numeral 438 designates index of the output vector giving the minimum distortion.

The operation of the device will be described. The input image signal system 401 is subjected subtraction of the interframe predicting signal 403 by the subtractor 402, and converted into the interframe differential signal 404. The interframe differential signal has little power in comparison to the original signal, and therefore can be encoded with little coding error. The interframe differential signal 404 is encoded in the first stage vector quantization coding section 405.

Then the threshold value 422 is used as parameter. The coded data 406 encoded in the first stage vector quantization coding section 405 is decoded in the first stage vector quantization decoding section 407 thereby the first stage decoded signal 408 is obtained. The first stage decoded signal 408 is subtracted from the interframe differential signal 404 by the subtractor 409 70

I

thereby the first stage error signal 410 is obtained.

The first stage error signal 410 has little power further in comparison to the interframe differential signal 404, and therefore can be encoded with little coding error. The first stage error signal 410 is encoded in the second stage vector quantization coding section 411. Then the threshold value 422 is used as parameter. The coded data 412 encoded in the second stage vector quantization coding section 411 is decoded in the second stage vector quantization decoding section 413 thereby the second stage decoded signal 414 is obtained. The first stage decoded signal 408 and the second stage decoded signal 414 are added in the adder 415 thereby the decoded interframe differential signal 416 is obtained. The interframe predicting signal 403 and the decoded interframe differential signal 416 are added in the adder 417 thereby the decoded image signal "series 418 is obtained. The decoded image signal series 418 is stored temporarily in the frame memory 419 and supplied with the frame delay thereby the interframe predicting signal is formed. On the other hand, the first stage coded data 406 and the second stage coded data 412 are subjected to the variable length coding in the variable length coding section 420, and stored temporarily in the buffer 421 and subjected to the speed

B

smoothing processing, and then transmitted as the Stransmitting signal 424 through the line interface (I/F) 71 423. In the buffer 421, the threshold value 422 in proportion to the storage amount of the variable length coded data is outputted, and supplied to the first stage vector quantization coding section 405 and the second stage vector quantization coding section 411 so as to control the information generation amount.

Next, referring to FIG. 26 and FIG. 27, the operation of the first stage vector quantization coding section 405 and the second stage vector quantization coding section 411 will be described. As described regarding the interframe vector quantization device in the prior art, in the vector quantization, the picture element is made a plurality of blocks and the output vector with the highest similarity (least distortion) is searched. In FIG. 26, an example of the vector quantized in the first vector coding section 405 and the vector quantized in the second stage vector quantization coding I section 411 is shown. The dimensions of the vector in any case are made 4 x 4 16. In the invention, the average value of interframe differential signals corresponding to the same position on the picture plane C as that of the vector quantized at the second stage (formed by the first stage error signal) is made one element, and vector quantized at the first stage is C 25 formed. Consequently, as shown in FIG. 26, when the Si vector quantized at the first stage and the vector quantized at the second stage are overlaid on the 72 picture plane, one piece at the first stage corresponds to 16 pieces at the second stage. This is expressed by formulas as hereinafter described. If the series comprising the interframe differential signals 404 blocked per 4 x 4 16 pieces is represented as S. [Si Si2, S i 6 and set comprising the S i i2' i16 system S. blocked further per 4 x 4 16 pieces on the picture plane is represented as [S S2, S 16 2' -16 (S.i i 1 16), FIG. 26 is expressed as follows: 16 block average value m. 1/16 E S. (i 1 16) j=l vector quantized at first stage m [ml, m2, o o o16 m and [S S2' S 16 are at the same position on the picture plane.

o 0 If the first stage decoded signals 408 obtained at the S first stage vector quantization decoding section 405 and the first stage vector quantization section 407 are represented as m' [m'll m 2 1 m6 the first I 16 S'stage error signals 410 to be subjected to.the vector quantization at the second stage are following vectors: I I

I

i r

A

S. u [Si.

-i 1 il m S. S.

u: 2 unit 16 unit vector) 1 At the second stage, the above-mentioned vectors are subjected to the average value separation and normalization, and then to the vector quantization as described 73 ii. i regarding the interframe vector quantization device in the prior art. Consequently, influence of the first stage vector quantization to the second stage vector quantization relates only to the average value being the scalar quantity, and therein no influence as vector. If there is any influence between both, efficiency of the vector quantization at the second stage is deteriorated by error of the vector quantization at the first stage.

If relation between the first stage and the second stage exists only in the scalar quantity as in the case of the invention, the first stage vector quantization does not adversely affects the second stage vector quantization.

0ooo 0 FIG. 27 is a block diagram illustrating composition 0 0 0 o0° of the first stage vector quantization coding section °o °oo 15 405. Input signal to be subjected to the vector o 00 0 ooo quantization is the interframe differential signal 404.

0000 00 The signal 404 calculates the average value and the amplitude in unit of a block of 4 x 4 16 pieces in the operation section 425 of average value and amplitude.

0000 1 20 This block has amount of a block to be subjected to the o 0 vector quantization at the second stage. The obtained o 0 0average value 426 is blocked, and the vector for the 0 0 °oo°°o first stage quantization is formed and subjected to the 00g.0 average value separation and normalization in the o 25 average value separation and normalization section 428.

This is expressed by formulas as hereinafter described.

The operation in the operation section 425 of average value and amplitude is to calculate 74 16 average value m. m. 1/16 S..

1 1 j=l 1 16 amplitude gi g 1/16 E m l j=l The processing in the average value separation and normalization section 428 is to calculate 16 average value M M 1/16 E m.

j=l 3 16 amplitude G G 1/16 E Im. M

I

jl1 average value separation and normalization: x. o 3 (m M)/G S.Distortion between the normalized vectors X [x 1 x 2 0o S 10 x 1 obtained as above described and the output o o.o 16 I 0 vectors 432 read from the code book is calculated in the distortion operation section 433. Before this processing, the average value m. and the amplitude g. (427) are 1 1.

0i compared with the threshold value 422 in the block o G 15 discrimination section 434. Let the threshold value 422 o I be Th, the block discrimination is represented as follows: 0 o Imil Th and g. Th insignificant block I mi. Th or g. Th significant block o 0 0 Regarding the insignificant block, the coding is not required at the first stage and the second stage.

75 C~r r i However, since the block discriminationuses the block in the second vector quantization coding device 411 as unit, it is only one element for the block of the first stage. Consequently, in the distortion operation section 433, the distortion of the element corresponding to the insignificant block is estimated as 0. That is, the distortion 436 is usually calculated as follows: 16 distortion d d(X, Y j Ix Y2 i j=l J However, if the block S. is insignificant block, since the corresponding element becomes S. m. x the i 1 i' distortion 436 is calculated as follows: 16 d(X, Y 2 x E -y2 j=l(j=i) x In the minimum distortion detecting section 437, among the distortion 436 between the input vector stored in the code book 431 and the input vector 429, the minimum distortion is detected and the index number 438 of the input vector giving the minimum distortion is outputted.

The coded data 406 outputted from the first stage vector quantization coding section 405 are the block discrimination information 435,'the average value M and 4 .9L. the amplitude G (430), and the index 438. However, if all blocks included in the blocks to be quantized at the first stage are insignificant blocks, since information other than the block discrimination information 435 does 76 63 1 lr 1- C I I~ 3 -1 not have any meaning and need not be transmitted, the information amount can be controlled by the threshold value 422.

Regarding the second stage vector quantization coding section 411, the operation is similar to that of the vector quantization coding sertion 439 described regarding the interframe vector quantization device in the prior art. In the embodiment, since the threshold value 422 supplied to the second vector quantization coding section 411 may be controlled and only the first stage vector quantization coding section 405 may be used for the coding, the information amount can be significantly controlled.

In this embodiment, although the control of the o 15 threshold value is feedback control corresponding to the S0 u storage amount of the buffer, it is also effective that the frame memory is installed at the front stage of the coding device and the motion amount is estimated thereby factor of feedforward is added.

Also in this embodiment, although the fixed output vector set is used in the vector quantization code book J at both the first stage and the second stage, it is also S effective that the code book for the first stage produces the output vector using frame memory content within the !25 loop and the method of vector quantization or motion compensation is used. Merit in that the average value of the block t- perform coding of the second stage is 77 64 I T. L~ 1 treated as the picture element in the first stage is not limited to the vector quantization, but, for example, use of the orthogonal transformation in coding of the second stage is also effective because higher harmonics are not generated due to error in the first stage.

A sixth embodiment of the invention will be described referring to FIG. 30 FIG. 32. In FIG. numeral 528 designates a dynamic code book RAM in which writing or reading is possible at any time, numeral 529 designates a normalization circuit which normalizes the average value separated input vector X in magnitude X of the vector, numeral 530 designates normalized 0 coefficient hereinafter referred to as and numeral °ooa" 531 designates normalized input vector hereinafter S° 15 referred to as Numeral 532 designates a dynamic code book control section which controls the update procedure of the dynamic code book RAM, numeral 533 designates write demand signals, numeral 534 designates oa, 2 normalized input vector with index, numerals 535a, 535b a 20 designate selectors, and numeral 536 designates vector data. In FIG. 31, numeral 537 designates a vector data a decoding section.

The vector quantization coding operation in an embodiment of the invention will be described referring 25 to FIG. 30. Input signal vector S designated by numeral 501 in FIG. 30 is converted by the average value separate circuit 502 into average value separated input vector X 78 65 W" so- st I---e designated by numeral 505 in FIG. 30, and then inputted to the inner product operation section 506 and the normalization circuit 529. The average value is processed and transmitted in similar manner to the prior art. The inner product P yi between the normalized output vector yi which is read from the fixed code book ROM 507 and the dynamic code book RAM 528 and designated by numeral 509 in FIG. 30 and the average value separated input vector x is calculated in the inner product operation section 506 in similar manner to the prior art, and then the normalized output vector yi giving the maximum inner product value to the average value separated "i nput vector x is detected, and the address signal 508 a 0 indicating address of the detected normalized output vector yi on the fixed code book ROM or the dynamic code book RAM is outputted as the index 519 from the index latch 516. The maximum inner product value Pmax is max outputted as the correction amplitude g designated by numeral 513 in FIG. 30 from the maximum inner product detecting section 512. In the above-mentioned process, the inner product operation section 506, the maximum inner product detecting section 512, the address counter 510 and the index latch 516 execute the same operation as that of the prior art. The dynamic code book RAM 528 as shown in FIG. 32 is constituted by a FIFO memory in first-in first-out form where writing or reading operation is performed in asynchronous state.

79 66 L- ~I

-I-

I. r I--jUi~ucU~_m Update is performed at any time according to the update procedure controlled by the dynamic code book control section 532. An example of the update procedure of the content of the dynamic code book RAM 528 will now be described based on an operation example of the dynamic code book control section 532. The average value separated input vector x is inputted to the normalization circuit 529 and processed according to the following formulas, and analyzed into the normalization coefficient o designated by numeral 530 in FIG. 30 and the normalized input vector X* designated by numeral 531 in FIG. 30, and then two parameters a and X* are supplied to the dynamic code book control section 532.

o xi E xj 1j=l "Q0~ 0oui 0 0 0 44 -4 00 0cO X /o X* 2* k 1' I x I 0 0 In the dynamic code book control section 532, using the normalized coefficient a and the correction amplitude 9 20 separated input vector x and the normalized output vector QPW g yi regenerated in amplitude at the decoded state is estimated according to the following formula, and the update procedure of the dynamic code book RAM 528 is adaptively controlled based on the magnitude of the 2 approximation d 80 -L io7 L d 2 (x gyi 2 d2 2 2 lx 2 g21i2 2g(x, y) 2 2 2g 2 [lI 2 1, y) g] 2 2 -g That is, when the approximation d 2 is larger than the 2 allowable value D 2 the write demand signal 533 is made Ill and the normalized input vector X* is written in the dynamic code book RAM 528, and at the same time the normalized input vector 534 with index to which predix is added so as to indicate the writing of the normalized input vector X* is outputted. On the other hand, when t 2 2 S""o the approximation d is the allowable value D or less, the write demand signal 538 is made I01 and simply outputted. The write control signal 533 is transmitted oa.. 15 to the first and second selectors 535c, and used to 0 0000 select the coded data transmitted corresponding to the update procedure of the dynamic code book RAM 528. That is, when the write demand signal 533 is 101, since the

S

update of the dynamic code book RAM 528 is not performed, the first selector supplies the correction amplitude g i (numeral 513) outputted from the maximum inner product detecting section 512 to the amplitude coding device 515 Sin similar manner to the prior art, and the second selector 535b transmits the index 519 outputted from the index latch 516 as the vector data 541 to .the coding data multiplexing section 520. When the write demand 81 1 68 I L I -e I -I _1 signal 533 is Ill, the update of the dynamic code RAM is pe;formed also at the receiving side, and at the same time the normalized output vector yi at the decoded state is replaced by the normalized input vector X* (numeral 531), and in order to transmit the normalized coefficient o (numeral 530) obtained in the normalization processing, the first selector 535a supplies the normalized coefficient a to the amplitude coding device 515 and the second selector 535b supplies the normalized input vector 534 with index as the vector data 536 to the coding data multiplexing section 520. The amplitude coding device 515 performs similar operation to the o o prior art.

Through the above-mentioned processing, the average -0 15 value coded data 517, the amplitude coded data 518 and 00 S 00 0 o4 the vector data 536 are multiplied in the coded data 0 multiplexing section 520 according to the prescribed format, and then outputted as the decoded output data 521.

An operation example of the dynamic code book RAM 528 will be described referring to FIG. 32. The read control section 528d reads data on the address assigned by the address pointer, the normalized output vector and repeats the operation in sequence.

When the write demand signal 535 is Ill, the write control section 528b writes the write data, the normalized input vector X* onto the address assigned by 82- 69 *M*IWMI 49 the write address pointer. The address counter 528a counts up the address by 1 at the write finishing point and resets the address to 0 when it becomes over the maximum value, and repeats the operation. When the above-mentioned operation is executed, the newest normalized input vector X* of the definite number determined by the memory capacity can be used as the normalized output vector yi in the vector quantization.

The vector quantization decoding operation in this embodiment will be described referring to FIG. 31. The coded output data 521 are separated in the coding data demultiplexing section 522 according to the prescribed °o 0 format into the average value coded data 517, the amplitude coded data 518 and the vector data 536.

0 15 The average value coded data 517 and the amplitude 0o o coded data 518 are decoded in similar manner to the pric 0 0000 or 4 1 art, and converted into the average value decoded value i (numeral 529 in FIG. 31) and the amplitude decoded value g (numeral 530 in FIG. 31). In the vector data decoding section, it is discriminated whether the separated vector data 541 is coincident with the prefix added to the normalization input vector or not. If coincident, the write demand signal 533 is made ili, and the write demand signal 533 and the normalized input :25 vector X* (numeral 531 in FIG. 31) received subsequent to the prefix are outputted. If not coincident, the write demand signal 533 is made |01 and the vector data 4 I 4 (4 83 536 is outputted as the index 519. The fixed code book ROM, 507 and the dynamic code book RAM 533 supply the normalized output vector (numeral 509 in FIG. 31) corresponding to the index 519 to the third selector 535c. Further when the write demand signal 533 is III, the normalized input vector X* (numeral 531 in FIG. 31) is written in the dynamic code book RAM 529, and the update of the dynamic code book RAM 528 similar to the coding operation is executed. In the third selector 535c, when the write demand signal 533 is 101 the normalized output vector y. (numeral 509 in FIG. 31) is outputted, and when the write demand signal 533 is IlI 0 the normalized input vector x (numeral 525 in FIG. 31) 0'00 is outputted. The vector outputted from the third 000 00 o 15 selector 535c is multiplied by the amplitude decoded 00 0 C.0. value 526, and then the average value decoded value 525 0000

C

0000is added, thereby the decoded vector s(numeral 527 in FIG. 31) is obtained.

In this embodiment, although the average value 0 00 20 separation and normalization vector quantization device is shown where the average value of the input vector is 00 04 separated and the output vector is separated in the average value and normalized, similar effect can be obtained when the input vector is subjected to vector 25 quantization directly, and the dynamic code book RAM is updated based on the vector quantization error.

8 4 71 El- ~-I ?u A seventh embodiment of the invention will be described referring to FIG. FIG. 35 is a block constitution diagram of an image coding transmission system according to the invention.

In FIG. 35, the side indicates the transmitting side, and the side indicates the receiving side.

In FIG. 35, numeral 601 designates an input buffer which inputs the digitized image signals and outputs them suitably to the coding section at the next stage, numeral 603 designates a frame memory which stores the image signals after coding and decoding before the present image signals by one frame, numeral 602 designates a subtractor which carries out the subtraction between the output of the input buffer 601 and the output of the frame memory 603, numeral 604 00 designates a quantization coding device which gives the too* 0 0. quantization and coding to the output of the frame memory 603, numeral 605 designates a quantization decoding device which decodes the signals after the quantization coding, numeral 606 designates an interframe adder which adds the quantization decoded output and the output of the frame memory 603, and writes the result to the frame memory 603, numeral 607 designates a variable length coding device which assigns the variable length code to the quantization coded output corresponding to the frequency of each code, numeral 608 designates a transmitting buffer which stores the variable length -72- II-l ~d I L i; coding output, numeral 609 designates a transmitting buffer control section which monitors the control of writing and reading in the transmitting buffer 608 and the storage amount of the transmitting buffer and then transmits the monitoring result to the input buffer 601, numeral 610 designates a dummy data adding section which adds the dummy data to the output of the transmitting buffer, numeral 616 designates a local decoding capability information generation section which generates information indicating time capability of decoding processing at the local receiving side, numeral 617 designates a multiplexing section which multiplies o00 the output of the dummy adding section by the local ¢ooo i decoding capability information generated in the section 15 616, and numeral 611 designates a line interface section.

oo Numeral 612 designates a line interface section on uthe receiving side, numeral 619 designates a separate section which separates remote decoding capability information from the receiving data, numeral 618 o0.20 designates a transmitting operation control section which determines the local transmitting operation from oa 0 0 the remote decoding capability information and transmits 0 0 it to the transmitting si.de, numeral 613 designates a Sdunmmy separate section which deletes the added dummy o 25 data, numeral 614 designates a variable length decoding section which decodes the variable length code, numeral 615 designates a receiving buffer which stores the 86 I, i 1 73 I -r C signals after the variable length decoding, numeral 605' designates a quantization decoding section which gives the quantization decoding to the output of' the receiving buffer 615, numeral 603' designates a frame memory which stores the decoded image signals before the present image signals by one frame, and numeral 606' designates an interframe adder which adds the output of the quantization decoding section 605' and the output of the frame memory 603' and then writes the result to the frame memory 603'.

The operation of the device will be described.

The inputted image signals 701 are written to the input buffer 601. The input buffer performs writing and reading by the unit of the image frame, but it has the composition of double buffer because reading may be performed during writing.

C C The coded and decoded image signals 702 before the present image signals by one frame are outputted from the frame memory 603. In the interframe subtractor 602, the interframe differentialsignals 703 are obtained by subtracting between the present image signals 701' read from the image buffer and the image signals 702. The interframe differential signals 703 are encoded by the quantization coding device 604, and become the quantizaticn coding signals 704. FIG. 37 shows an example of characteristics of the quantization coding device. The quantization coded signals 704 are inputted 87 1.

74 in the variable length coding device 607, and transmitted into the variable length code 706 corresponding to the frequency of each coding signal.

At the same time, the quantization coded signals 704 are inputted in the quantization decoding device 605, and then are outputted as the coded and decoded differential signals 705. FIG. 38 shows an example of characteristics of the quantization decoding device.

The coded and decoded differential signals 705 are inputted together with the image signals 702 into the interframe adder 606, and become the coded and decoded image signals 702' and are written to the frame memory 603 for the coding to the next frame.

C o On the other hand, the variable length codes 706 So 00O 0 15 are inputted in the transmitting buffer 608. The 0 f oooo transmitting buffer outputs the data in accordance with the requirement from the transmission line side after storing the variable length codes over the definite 2o o amount, and has the composition of double buffer (buffer So 20 f1, buffer 112) because writing and reading must be performed at the same time. The transmitting buffer to control section 609 controls -writing and reading of the transmitting buffer. For example, when the buffer #1 is '"oo at writing operation and the buffer #2 is at reading operation, the transmitting buffer control section 609 monitors the storage amount of the buffer and if the storage amount becomes more than the prescribed set 88 75 I j value, the transmitting buffer control section 609 demands ceasing of output of the data to the input buffer 601.

Receiving the demands, the input buffer 601 ceases the output of the data to the rear stage. The transmitting buffer control section 609 detects the pause of the input data to the transmitting buffer 608, and ceases writing to the buffer #1 and makes the situation of waiting for reading. The buffer #2 during reading ceases reading if the residual amount becomes less than the prescribed set value, and it waits for the buffer #1 to be in the situation of waiting 'for reading.

When the buffer #1 is in the situation of waiting for o r reading, the buffer #2 and the buffer #1 are read out continuously. The buffer #2 is in the situation of o waiting for writing when the residual amount becomes oze zero.

0 00 S0 o o 02 a- 0o 0r 0 .4 o 2 When the buffer #2 is in the situation of waiting for writing, the transmitting buffer control section 609 demands to start the output of the data to the input buffer 608.

In this process, before the buffer #1 gets in the situation of waiting for reading, there becomes the situation that the transmitting buffer 608 cannot output any data.

The dummy data adding section 610 outputs the data with the dummy data added thereto so as to continue the 89 76 e "i transmission of the data to the transmission line without break while the transmitting buffer 608 cannot output the data.

In the local decoding capability information generation section, the information 707 indicating time capability of decoding processing at local receiving side, for example, information indicating time TD' required for processing one image frame is generated.

.This information is multiplied in the multiplexing section 617 into that combined with the image dummy data.

The signal after multiplexing is converted in the line interface section 611 so that the electric level is matched to characteristics of the transmission line, and then outputted to the transmission line.

15 At the receiving side, signal inputted through the transmission line is subjected to reverse conversion of the electric level in the line interface section 612, and information 707' indicating time capability of the remote decoding processing is separated from the signal 20 in the separate section 619 and transmitted to the transmitting operation control section 618, and other data are transmitted to the dummy separate section 613.

In the dummy separate section 613, the dummy data added in the dummy adding section 610 are cleared thereby only 25 the data about the image are outputted.

000 00 0 030* ooo oo 000 00 0 0O 0

D

o oo 0000 0 3 03-0 0 0 0 (3 ii o oo 0 0~ o c| L 1 O ai i a 00 0 oooo Do o i The output is processed in the variable length decoding section 614 by the reverse treatment with 90 I I respect to that in the variable length coding section 607, and then inputted in the form of the quantization coded signals 704 into the receiving buffer 615.

The receiving buffer has the composition of double buffer, because writing and reading are performed at the same time. In the receiving bufler, the stored data are variable in amount so as to take matching with respect to time between the signal speed inputted from the transmission line side and the speed of the image decoding section at the rear stage.

For example, 'f the processing speed of the image decoding section at the next stage is low, the stored amount of the receiving buffer is increased. On the contrary, if the processing speed is high, the receiving buffer acts at the small stored amount. The quantization coded signals 704' are decoded by the quantization 0 decoding device 605' and outputted as the coded and decoded differential signals 705' in similar manner to the transmitting side. The coded and decoded image signals 702' before the present decoding image by one O 0frame are outputted from the frame memory 603', and are o(o o added to the coded and decoded differential signals 705' o 00 S in the interframe adder 606', and the resulted signals are written as the coded and decoded image signals to 0 25 the frame memory 603' and also outputted to outside.

S oo On the other hand, at the transmitting operation control section 618, based on the information 707', 91 i L. c ~L r~-rs discrimination is performed regarding what degree of the coding capability at the local transmitting side enables the decoding processing without overflowing of the receiving buffer at the remote station.

For example, if time TD is required to decode one frame as the information 707', command is issued so that the interval to transmit the code corresponding to the lead of each image frame from the transmitting buffer is always made T

D

or more.

Operation of the transmitting buffer control section 609 receiving the code will now be described in detail.

FIG. 39 shows state of the transmitting buffer control section typically when the buffer #1 is at 0'15 reading state and the buffer #2 finishes the writing and .0is waiting for reading. In usual, if the transmitting ooe buffer stores data more than the prescribed set value e o c i 0 (Th2 in FIG. 39) during writing, stoppage of data output is demanded to the input buffer 601. In FIG. 39, 20 the buffer #2 stops the writing at the storage amount M.

i On the other hand, reading from the transmitting buffer is performed at a burst in the N data unit, and when the residual amount of the buffer during reading becomes less than N, reading is performed only the S25 jbuffer at reverse side is at waiting for reading, and reading is stopped at other cases.

reading is stopped at other cases.

92- 1 c. When command is issued from the transmitting operation control section 618 that transmitting interval of the code corresponding to the lead of the image frame is made T D or more, output of data corresponding to the lead of the image frame from the transmitting buffer is checked. Once the corresponding data is outputted, the timer is set to the time TD and supervision is performed so that next corresponding data is not outputted before the timer becomes time out.

If it is recognized that the corresponding data exists in the N data to be subsequently transmitted before the time out, next reading is inhibited.

The longer the read inhibiting time, the longer the time of output stop command for data to the input buffer o 15 601. Consequently, the image frame number which can be encoded per unit time is decreased.

Since the dummy data are transmitted to the transmission line during read inhibiting of the transmitting buffer, data of only image after the dummy 20 data separation at the receiving side is intermittent in 0o time, thereby longer time can be used for the decoding processing at the receiving side.

Consequently, even at the image coding device having the receiving side of large TD since transmission at the remote transmitting side is performed in matching with the local capability (limiting the capability at the transmitting side), although the image frame number -93 80 is small and quality as the motion picture image is deteriorated, the device at the receiving side is made small size and low cost.

In this embodiment, in order that the transmission image frame number at the transmitting side is drawn to the limit of the capability at the receiving side, output of the data corresponding to the lead of the image from the transmitting buffer is limited. However, if the operation is allowed at considerably lower level than the capability at the receiving side, above-mentioned effect can be obtained when the image frame number outputted from the input buffer 601 per unit time is varied.

Also in this embodiment, although the information 4 0 707 indicating the time capability of the decoding processing and the image data are multiplied on one transmission line and transmitted, similar effect can be obtained when the information 707 is transmitted through other transmission line.

According to the embodimentas above described, in the motion compensation circuit, the average value of the input block signals is adopted in matching between blocks, thereby even at large motion amount or at scene change, the frequency error signal is suppressed without increasing the hardware scale or the prooessing time.

As a result, the generated information amount is reduced or the picture quality is improved.

94 Also according to an embodiment of the invention, since the ON/OFF operation of each coding and decoding device is adaptively selected and changed, the generating amount of the coding information and the reconstructed image quality can be adaptively controlled per frame unit in wide range.

Further according to an embodiment of the invention, since the motion amount of the frame to be encoded hereafter is estimated and the coding control is performed, if the subject is suddenly moved or stands still on the contrary, the interframe coding device without delayed control is obtained.

Further according to an embodiment of the invention, the dimension number of the vectors to be encoded is reduced and the vector quantization is performed in stages. Still further, since the threshold processing is performed at the encoding process of 0o' the second stage or later, the block size can be varied without increasing the operation scale of the inner product quantization o 0 t°o device, and control of the coding information amount in each stage can be performed at wide range.

Further according to an embodiment of the invention, since the vector quantization device is constituted in multiple stages, vector quantization at the first stage is performed using the average value of blocks being encoding unit at the next stage as S constitution element, control range of the information amount is wide, and the picture quality is not extremely deteriorated by the control, and the vector quantization error at the first stage does not adversely affect the coding at the second stage.

Further according to an embodiment of the invention, since the code book of the vector quantization device is composed of 82

II'I

a dynamic code book where writing or reading is possible at any time and a fixed code book in the conventional manner, and based on approximation between the input vector and the decoding vector, while content of the dynamic code book is adaptively updated, the vector quantization coding and decoding is executed, thereby deterioration of the approximation of the decoding vector can be suppressed with respect of special input vector being different in property from the output vector group stored in the fixed code book.

Still further according to an embodiment of the invention, since the time capability of the decoding processing at the receiving side is transmitted together with the image data to the remote station, and the time interval of data transmission at the transmitting side is controlled based on the information o' at the receiving side, normal image communication can be realized even using the device of low cost and small size having low S decoding processing capability at the receiving side 0 o Si

Claims (9)

1. An image signal progressive build-up encoder/decoder comprising: a substractor which estimates residual signal vector showing a residual between one of input signal vectors made from a series of input image signal by means of dividing into lattice- shaped plural samples m x n n: positive integer) and an input signal vector of the previous frame; an average value encoder/decoder which calculates average value within block of residual signal vector, and performs redundancy reduction coding of the average value; a normalized vector quantization encoder/decoder which utilizes the residual signal vector as input vector and subtracts the average value from each element of the input vector and obtains the normalized output vector having the maximum inner product value to the input vector among a set of normalized output vectors with average value 0, amplitude 1 generated so o that total of distortion is minimized based on the distribution of normalized input vectors of which amplitude becomes 1, and obtains index to indicate the normalized output vector, and also o performs redundancy reduction coding and decoding of the S amplitude gain of the input vector given by the maximum inner S product value, and the decoded amplitude gain is multiplied by the detected normalized output vector thereby the amplitude reconstructed output vector can be obtained; a sample value encoder/decoder which performs redundancy reduction coding and decoding of m x n samples in the residual signal vector sample by sample; a switch which adaptively controls ON/OFF operation of the average value encoder/decoder, the normalized vector quantization encoder/decoder and the sample value encoder/decoder based on the control signal frame by frame; a vector reconstructor which selects adaptively the S decoded average value, the decoded residual signal vector by adding the decoded average value to the amplitude reconstructed output vector, and the decoded sample value based on the control 85 signal frame by frame control signal, and then outputs them as the decoded vector; and, a coding controller which generates the control signal and enables the adaptive control operation of the switch, each encoder/decoder and the vector reconstructor corresponding to the number of coded samples each frame.

2. An image signal progressive build-up encoder/decoder as set forth in claim i, wherein in the coding controller, at the first coding stage, only the average value encoder/decoder are turned on, and rough image is reconstructed by the decoded vector which all m x n samples are substituted by the decoded average value, and at the second coding stage, the average value encoder/decoder and the normalized vector quantization encoder/decoder are turned on, and the decoded vector substituted by the decoded residual signal vector is obtained, and the image of which quality is better than that of the first stage can be built up, and at the third coding stage or later, only the sample o oaa value encoder/decoder is turned on, the decoding vector comprising the decoding value of m x n pixels of sample value is S obtained, and the image of which quality is better than that of o the second stage can be built up. 0 o 0

3. An image signal progressive build-up encoder/decoder as set forth in claim 1 or claim 2, wherein in the average value encoder/decoder, the normalized vector quantization 004l: encoder/decoder and the sample value encoder/decoder, a set of different coding and decoding control modes corresponding to S various encoded information generation rate of each coding stage :0 are prepared, and based on the total encoded information generation rate of one frame by frame coding stage and the number S of the stage, the coding and decoding control mode, operation of the switch and the vector reconstructor are adaptively selected and controlled frame by frame at the subsequent coding stage.

4. An image signal progressive build-up encoder/decoder as set forth in any one of claims i, 2 or 3, wherein square-root 86 of the mean square error of each sample between the residual signal vector and the decoded vector outputted from the vector reconstructor is calculated as the error amplitude value, and based on the average of the error amplitude value during one frame period and the number of coding stage, the coding and decoding control mode and operation of the switch and the vector reconstructor are adaptively selected and controlled frame by frame at the subsequent coding stage.

An image signal progressive build-up encoder wherein to same one input image frame, the input signals are performed redundancy reduction coding and decoding and reconstructed image signals are delayed by one frame period, and the residual signals between the input image signals and the delayed signals are performed redundancy reduction coding and decoding frame by frame respectively and operation is repeatedly performed thereby high quality and resolution image is built up progressively as time progresses, said encoder comprising: a vector/subvector transformer which forms lattice- shaped am sample x bn line b, m, n: natural number, and am a x m, and bn b x n) residual signals into an L-dimensional (L am x bn) vector, and forms lattice-shaped m x n average values calculated within the blocks of a sample x b line residual signals respectively into a K-dimensional (K m x n) subvector; an average value encoder and decoder which performs redundancy reduction coding and decoding of the arithmetic means of the sample within the residual signal subvector; K-dimension normalized vector quantization encoder and decoder which treats the residual signal subvector as K-dimension input vector, and performs vector quantization of the input vector through the inner product operation of K dimensions into K-dimension normalized output vector of average value 0 and B, amplitude i, and performs redundancy reduction coding and decoding of the amplitude gain of the residual signal subvector given by the inner product value between normalized output vector and the input vector; a subvector/vector de-transformer which arranges 87 II samples within the decoded K-dimension residual signal subvector obtained by multiplying the normalized output vector and the decoded amplitude gain, and each element of the K-dimension amplitude reconstruction output vector corresponding to lattice- shaped m sample x n line subvector is added to the decoded average value, thereby performs interpolation of the decoded residual signal vector having the L dimensions; and performs decrease size of the lattice-shaped block of the residual signals step by step and to execute the coding and decoding operation repeatedly.

6. An image signal progressive build-up encoder as set forth in claim 5, wherein at the first coding stage, the input image signals are combined by lattice-shaped m sample x n line and average value within the block is treated as one sample, and the samples are further combined in lattice-shaped m x n samples into K-dimension input vector and the K-dimension mean separated and normalized vector quantization is performed for the K- dimension input vector, and at the subsequent coding stage, the K-dimension mean separated and normalized vector quantization is S performed again respectively by combination of the lattice-shaped o m sample x n line the residual signals thereby hierarchical S coding and decoding for each block can be performed.

7. An image signal progressive build-up encoder as set forth in claim 5 or claim 6, wherein at the subsequent coding stage, the square mean of the sample value within the block by combination of the lattice-shaped m sample x n line residual signals is compared with the threshold value, and block by block conditional replenishment is executed for coding and decoding of only the block having the square mean value larger than the threshold value, and binary informations indicating the result of the threshold comparison is performed redundancy reduction coding and decoding.

8. An image signal progressive build-up encoder/decoder according to claim 1 substantially as herein described with 100 88 II~ reference to and as illustrated in the accompanying drawings.

9. An image signal progressive build-up encoder according to claim 5 substantially as herein described with reference to and as illustrated in the accompanying drawings. Dated this 19th day of December, 1989 MITSUBISHI DENKI KABUSHIKI KAISHA By Its Patent Attorneys: GRIFFITH HACK CO. Fellows Institute of Patent Attorneys of Australia G 0 101