AU606397B2 - Telephone subset circuit arrangement - Google Patents

Description

Declarant To: The Commissioner of Patents i .ii .i L' i i I- AU-AI-13449/88 PCT WORLD INTELLECTUAL PROPERTY ORGANIZAN" N N Internat l Bu| f INTERNATIONAL APPLICATION PUBLISHED UBER'HEWTECO TPERATION TREATY (PCT) (51) International Patent Classification4 (11) International Publication Number: WO 88/ 08234 H04M 19/08 A l (43) Iniernational Publication Date: 20 October 1988 (20.10.88) (21) International Application Number: PCT/AU88/00046 (74) Agent: O'CONNOR, Patent Department, Standard Telephones and Cables Pty. Limited, 252-280 (22) International Filing Date: 22 February 1988 (22.02.88) Botany Road, Alexandria, NSW 2015 (AU).

(31) Priority Application Number: PI 1339 (81) Designated States: AU, BE (European patent), DE (European patent), DK, FR (European patent), IT (Euro- (32) Priority Date: 9 April 1987 (09.04,87) pean patent), JP, US.

(33) Priority Country: AU Published With international search report.

(71) Applicant (for A U only): STANDARD TELEPHONES AND CABLES PTY. LIMITED [AU/AU]; 252-280 Botany Road, Alexandria, NSW 2015 (AU).

(71) Applicant (for all designated States except A U US): AL- CATEL N.V. [NL/NL]; Strawinskylaan 537, NL-1077 A. P 8 DEC 1988 XX Amsterdam (NL).

(72) Inventor; and Inventor/Applicant (for US only) CALLIGARO, Paul, AUSTRALIAN Leonard [AU/AU]; 54 Barker Street, Kingsford, NSW 2032 -4 NOV 988 PATENT OFFICE This do;ument ciins Ihe (54) Title: TELEPHONE SUBSET CIRCUIT ARRANGEMENT imnc;i': t I .J e Lu l Li j ice idL correct for 2 /J I t ^L4M ~a4.w (57) Abstract A telephone subset circit arrangement which includes a capacitor (CI) that provides a current source for the circuits' dialler chip Initially, with the capacitor discharged, upon connexion of the line terminals (LI and L2) to an exchange line, current flows via the line terminal (LI) and a bleed resistor (RI) to cause a first transistor (TRI) to switch on th'ereby rendering the circuits' line switch conducting, The capacitor is charged via the operated line switch by line current and when the voltage level across the capacitor reaches the minimum operating Voltage of the dialler chip, a circuit comprising a second transistor (TR2) switches the first transistor off which in turn switches off the line switch. The dialler chip now has sufficient power available to it to operatt the line switch whenever the hook-switch (HS) is operated.

WO 88/08234 PCT/AU88/00046 -1- Telephone Subset Circuit Arrangement Technical Field This invention relates to telephone subsets and in particular to telephone subsets incorporating an electronic line switch, sometimes known as a line interface circuit.

Background Art The electrical line switch fulfils a number of functions including the hook-switch function, that is, the line switch acts as a hook-switch 'Wnen a hook-switch control signal is selectively applied to the line switch, a hook-switch control signal being generated when the user brings the subset into the off-hook mode. This control signal may, for example, be provided by a ten number repetory tone/pulse dialler chip or a microprocessor. In a subset provided with a conventional mechanical hook-switch and dialler chip, the dialler chip is provided with its operating power from current derived from the exchange battery and drawn over the exchange line through the hook-switch. As soon as the subset is brought into the offhook mode the hook-switch contacts operate and adequate operating voltage is extended to the dialler chip which can then function.

In the case of a subset provided wit an electronic line ,witch, however, when such a subset is initially connected to the exchange line, or reconnected after subsequently being un-plugged, the dialler chip is Without power because its power source is cut off by the line switch which it controls. Consequently the dialler chip cannot function, and the line switch cannot be signalled.

An obvious means by which operating power could be provided to the dialler chip under the initial conditions referred to above is to provide a small dry cell. An undesirable feature of this solution, however, would be the necessity to regularly replace the cell when its capacity falls. Another solution would be to provide a bleed cirouit around the line switch, to bleed sufficient current from the exchange line during the on-hook mode.

2 Some CMOS dialler chips, however, initally draw a peak current of about 300uA prior to attaining their normal operating state, and therefore any bleed circuit would have to provide at least 300uA. This introduces a problem in that a bleed current of this magnitude exceeds the allowable onhook current allowed by the telecommnnication authority.' Typically, the on-hook current must not exceed It is, therefore, an object of the present invention to provide a circuit arrangement which will provide the dialler chip with sufficient operating current upon initial connection, and re-connection after subsequent 0 un-plugging of the subset, without the need to draw excessive on-hook bleed current. Hereinafter such a circuit will be referred to as A Dialler Chip Energizing Circuit.

Sunrmary of Invention According to the present invention there is provided a telephone subset circuit arrangement comprising a first and second line terminal means for respectively connecting to conductors of an exchange line, a transmission circuit means connected between said first and second line terminal means, a line switch means whose switching element is formed by a conductive path of a controllable semiconductor switch means having a con-

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trol element coupled to an output of a control means associated with said transmission circuit means, said switching element being serially connected in the subset circuits' loop current circuit, said control means having a first input means coupled to hook-switch means for applying hook-switch mode signals to said output of the control means for switching said switching element accordingly, said control means deriving a power supply from current drawn from exchange battery via the first line terminal means and the conductive path of said line switch means to power terminal means associated with said control means, wherein said circuit arrangement further comprises a bleed circuit for bleeding a current of a predetermined magni- Stude from said exchange line, a first controllable semiconductor switch -3means whose control element is coupled to said bleed cIrcuit a'nd a controlled 1 element of which is coupled to the control element of siaid line switch means, whereby upon connection of said first and second line terminal means to the exchange line the bleed current renders said first controllable semiconduc~or switch means conducting whereby'the switching element of said line switch means is rendered conducting connecting current to the said power terminal means to enable said control means, said power terminal means being coupled to storage capacitor means arranged such that af ter a predetermined period the magnitude of the voltage across the said capacitor means reaches a level which causes said f irst semiconductor switch means to render the line switch means non-conducting.

Preferably, the circuit arrangement further includes a voltage regulatiorn means which regulates the voltage across the power terminals of the control means during off -hook operation.

Brief Description of Drawings 00 0 0e0O S. OS S S

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In order that the invention may be readily carried into effect, it will, now be described in detail by way of exa~ile with reference to the accompwnying drawings in which: I is a schematic circuit of part of a subset circuit arrangement showing the invention in its simplest form.

Fig. 2 is a circuit dlagram. of a, telephone subset incorporating an emabodiment of the present invention.

Fig. 3 is a circuit diagram of'1,'he embodiment of Fig. 2 with the addition of a regulation circuit.

Best Mode Of. Carrying Out The Invention Referring to Fig. 1, the ir'cuit shown con~rises a ten number repetory tone/pulse dialler chip 1, having a dial pulse output A, a power terminal C a cormon voltage rail terminal D and hook-switch (HS) input X and Y; a line switun 2 having its switchx~g circuit (not shown) coupled across outputs J and K and its control circuit (not shown) coupled to input L. &As '4 WO 88/08234 PCT/AU88/00046 coupled to input L is the emmitter electrode of an NPN transistor TR1 whose base element is connected to the junction of resistor R2 and the collector of the NPN transistor TR2. A bleed resistor R1 couples L1 terminal (not shown) to the junction of resistor R2 and the collector of transistor TR1 as well as to power terminal C via diode Dl. Diode Dl may preferably comprise three serially connected diodes. A storage capacitor Cl is connected across power terminal C and the common voltage rail D. Power terminal C is also coupled to the base element of transistor TR2 via zener diode D2.

Coupled to the base element of transistor TR2 is a delay network comprising resistor R3 and capacitor C2. The common voltage rail terminal D is coupled to line terminal L2 (not shown).

In operation, when the circuit arrangement shown in Fig. 1 is coupled to an exchange line via line terminals L1 and L2 (not shown) with capacitor Cl discharged and the subset on hook, line current flows via bleed resistor Rl, resistor R2, base element of transistor TR1 and to the common voltage rail D via line switch circuitry (not shown). Due to the voltage-current characteristic of diode Dl, very little current flows through the diode.

Transistor TR1 is switched on, thereby rendering the switching circuit of line switch 2 conducting and connecting LI terminal to terminal C of dialler 1. The voltage across capacitor C1 begins to rise. When the voltage across capacitor Cl reaches the minimum operating voltage of the dialler chip required to control the line switch, typically 1.8v, because of the characteristics of zener diode D2, a relatively significant current Sbegins to flow into the network comprising resistor R3 and capacitor 02.

The values of resistor R3 and capacitor 02 are such that only after the voltage across C1 reaches approximately 3v, well above the minimum line switch operating voltage, will the voltage across capacitor 02 have risen to a magnitude sufficient to cause transistor TR2 to saturate. Upon saturation, transistor TR1 Ls turned off and line switch 2 is rendered nonconducting. Charged storage capacitor 01 now providing adequate operating 9 i i i i u r WO 88/08234 PCT/AU88/00046 voltage at terminal C of the dialler chip so that when the subset is brought into the off-hook mode and hook-switch TS operates, the dialler chip produces the required signal at terminal A which is applied to input L of the line switch 2 to render the line switch conducting and allow the subset to operate normally.

If the subset is subsequently disconnected from the exchange line and the charge on storage capacitor C1 decays to below the minimum voltage (1.8v) necessary for the dialler chip to operate the line switch, when the set is re-connected to the exchange line insufficient current will be flowing through zener diode D2 to raise the voltage on capacitor C2 to cause saturation of transistor TR2. Consequently transistor TR1 is on and operating voltage is provided at terminal C via the conducting line switch 2-- Referring to Fig. 2, the subset circuit arrangement comprises line terminals L1 and L2 connected across the AC points of a polarity guard device in the form of a diode bridge PG. A tone ringer (not shown) is also connected across the line terminals. Across the DC points of bridge PG is a telephone transmission circuit TX. Dialler chip 1 is also connected across the DC points of bridge PG and in parallel with transmission circuit TX. The dialler chip may be, for example, a 0OKI MSM6052 chip, and ina dial pulse output A, a mute signal output B, a power terminal C, common voltage rail terminal D, dual-tone multifrequency (DTMF) output E, an earth recall output F, a DC characteristic adjustment signal output G, a plurality of inputs 1-28 from a key pad (riot shown) associated with the subset, and inputs X and Y from an associated hook-switch HS. Serially connected between the DC positive r-zint of polarity guard PG and the transmission circuit TX is the main swit c ng path of the line switch circuit comprising a main switch in the form of a complementary configuration of transistors TR4 and TR5, and a control transistor TR3 whose base element is coupled to output A of dialler chip 1 and to the emitter of transistor TR1 3 0 0f the Dialler Chip Energizing Circuit comprising transistors TR1 and TR2, 1 WO 88/08234 PCT/AU88/00046 -6bleed resistor RI, diodes Dl and D2, resistor R2, storage capacitor Cl, and delay elements ,eansisting of resistor R3 and capacitor C2.

The operation of the Dialler Chip Energizing Circuit part of the circuit shown in Fig. 2 is identical to that of Fig. 1. The operation or the line switch shown in Fig. 2, assuming normal operating voltage at terminal C, is as follows: When brought into the off-hook mode, the operation of the hook-switch contacts H-S is sensed by dialler chip I whereupon a mute signa~l is applied to output B which mutes the transmission circuit TX; a signal is applied to output G which turns on a shunt circuit (not shown).

A signal is applied to output A which turns on the control transistor TR3 of the line switch which in turn switches on transistor TR t I and TR5. Upon operation of transistor TR5 a current loop is provided via line terminal Li, positive point of polarity guard PG, resistor R4, collector /emit ter junction of transistor TR5, shunt circuit in parallel with transmission circuit TX, negative point of polarity guard PG to L2. After about 4100 rn/s the shunt circuit and the mute signal are removed leaving the transmission circuit TX in the current loop.

Referring to Fig. 3, the subset arrangement shown is substantially identical to that shown in Fig. 2 except for the addition of the regulation circuit elements which comprise transistors TR6 and M 7, resistor R6 and diode D6 and a decoupling element C3. The emitter/collector path of TR7 is serially connected between the line switch switching path and terminal C of dialler chip ,L and its base element is connected to the ornllector element of transistor TRG whose base element is coupled to the base element of transistor Th In operation, when the subset Is in the offC-hook~ mode and the voltage across capacitor CI begins to rise to say L.P-N, current flowing. throughi zener diode D2 and resistor R7 increases causinr the voltage at the cathode of the zener diode to Increase. Consequently transistor TR6 drawo increased current through resistor H6. Kn increase in current through resis4- WO 88/08234 PCT/AU88/00046 7 tor R6 lowers the voltage at the base element of transistor TR7 thereby regulating the voltage at terminal C. The value of resistor R7 determines the reference voltage.

Diode D6 is included in the base/emitter circuit of transistor TR6 in order to ensure that the Dialler Chip Energizing Circuit is not misoperated by the regulation circuit. The forward characteristics of diode D6 are such that during the operation of the Dialler Chip Energizing Circuit, no significant current flows through transistor TR6. To change the conductance of transistor TR6 during regulation, however when the voltage at terminal C rises to regulation reference level, with a corresponding increase in the voltage at the cathode of zener diode, significant current flows via base/emitter of TR6 to operate the regulation circuit.

While the present invention has been described with regard to many particulars it is understood that equivalents may be readily substituted without departing from the scope of the invention.

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Claims (8)

1. A telephone subset circuit arrangement comprising a first and sec- ond line terminal means for respectively connecting to conductors of an ex- change line, a transmission circuit means connected between 5aid first and second line terminal means, a line switch means iwl-se switching element is fc. led by a conductive path of a controllable semiconductor switch means having a control element coupled to an output of a control means associated with said transmission circuit means, said switching element being serially connected in the subset circuits' loop current circuit, said control means having a first input means coupled to hook-switch means for applying hook- switch mode signals to said output of the control means for switching said switching element accordingly, said control means deriving a power supply from current drawn from exchange battery via the first line terminal means and the conductive path of miad line switch means to power terminal means associated with said control means, wherein said circuit arrangement fur- ther comprises a bleed circuit for bleeding a current of a predetermined magnitude from said exchange line, a first controllable semiconductor switch means whose control element is coupled to said bleed circuit and a controlled element of which is coupled to the control element of said line s, witch means, whereby upon connection of said first and second line tenni- nal means to the exchange line the bleed current renders said first con- trollable semiconductor switch means conducting whereby the switching element of said line switch means is rendered conducting connecting current to the said power terminal means to enable said control means, said power terminal means being coupled to storage capacitor means arranged such that after a predetermined period the magnitude re the voltage across the said capacitor means reaches a level whiuh causes said first semiconductor switch means to render the line switch means non-conducting.

2. An arrangement as claimed in claim 1, further including a second A controllable semiconductor switch means a control element of which is cou- L,~u ,i I .i 1 WO 88/08234 PCT/AU88/00046 -9- pled to the said storage capacitor means via a delay circuit which includes a zener diode means, and a conductive path of which is coupled to the con- trol element of said first controllable semiconductor switch means, the characteristics of said zener diode means being such that when the voltage across said storage capacitor reaches a first predetermined magnitude the zener diode means begins to conduct a relatively large current whereby said second controllable semiconductor switch means is rendered conducting, thereby switching the first controllable ,witch means off.

3. An arrangement as claimed in claim 2, wherein said delay circuit further includes an R/C network the characteristics of which are such that the rendering of the second semiconductor switch means conducting is de- layed until the voltage across said storage capacitor means rises to a sec- ond predetermined magnitude higher than said first predetermined magnitude.

4. An arrangement as claimed in any one of the preceding claims, in- cluding a voltage regulating means for regulating the voltage at the power terminta means of the control means, said voltage regulating means compris- ing a third semiconductor switch means a conductive path of which is seri- ally connected between said first line terminal means and said power terminal means, and a control element of which is coupled to a voltage sensing circuit means arranged such that when the magnitude of the voltage at the power terminal means rises to a third predetermined magnitude the conductance of the conductive path of the third semiconduetor switch means is increased thereby regulating the voltage at said power terminal means about a reference value set by said voltage sensing circuit.

An arrangement as claimed in claim 4, wherein said voltage sensing circuit comprises a fourth semiconductor switch means a control element of which is coupled to a reference circuit comprising said zener diode means and a voltage reference resistor means of predetermined value, and a conductive path of which is coupled via a serially connected cv.rent sens- ing resistor means to said line terminal means and to the control s.ement WO 88/08234 PCT/AU88/00046 10 of said third semiconductor switch means, whereby when the voltage at the said power terminal means rises to said third predetermined magnitude, in- creased current through said reference circuit causes the current sensing resistor to increase, thereby decreasing the conductance of the third semi- conductor switch means.

6. An arrangement as claimed in any one of the preceding claims, wherein said control means associated with said transmission circuit mean. is a ten number repetory tone/pulse dialler chip.

7. An arrangement as claimed in any one of claims 1 to 5, wherein said control means associated with said transmission circuit means is a micro- processor.

8. A telephone subset circuit arrangement substantially as herein de- scribed with reference to Figs. 1, 2 and 3 of the accompanying drawings