AU602058B2 - A packet switching network - Google Patents

A packet switching network Download PDF

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Publication number
AU602058B2
AU602058B2 AU12630/88A AU1263088A AU602058B2 AU 602058 B2 AU602058 B2 AU 602058B2 AU 12630/88 A AU12630/88 A AU 12630/88A AU 1263088 A AU1263088 A AU 1263088A AU 602058 B2 AU602058 B2 AU 602058B2
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AU
Australia
Prior art keywords
node
communication network
data
circuits
receiver
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Ceased
Application number
AU12630/88A
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AU1263088A (en
Inventor
Jan Gaston Bauwens
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Alcatel Lucent NV
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Alcatel NV
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Publication date
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Anticipated expiration legal-status Critical
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Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00Data switching networks
    • H04L12/28Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
    • H04L12/42Loop networks
    • H04L12/437Ring fault isolation or reconfiguration

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  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)
  • Small-Scale Networks (AREA)
  • Time-Division Multiplex Systems (AREA)

Description

-n Iendl-nents maeunder [7TI n,'t 0 Lg. o tan tl COMYMONWEALTH OF AUSTRALIA PATENTS ACT 1952-1969 COMPLE&TE SPECIFICATION FOR THE TNVENTION ENTITLED "A PACKET SWITCHING NETWORK" The following statement ip a full description of this invention, including the best method of performing it known to us:- S1 This invention relates to a communication network to transmit packets of data, each containing routing information, between terminal stations connected to said network via nodes, each of said notes including at least a first receiver circuit and a first transmitter circuit to respectively receive and transmit packets from and to said network, at least a second receiver circuit and a second transmitter circuit to respectively receive and transmit packets from and to the terminal station connected to said node, and control means to route packets received by said first receiver circuit either to said first or to said second transmitter circuit in functioi of said routing information contained in said packets and to transfer packets received by said second receiver circuit to said first transmitter circuit.
Such a network is already known in the art, e.g. from Australian Patent Application No. 21957/83. In this known network, the control means include a queue and temporarily store the packets of data intended for the first transmitter circuit in this queue and afterwards transfer either the thus stored packets, or those stored in the second receiver circuit to this first transmitter circuit in moction of the priority allocated to either the queue or the second receiver circuit.
Hence, these known control means are relatively complex because they contain a queue and their operation makes it necessary to establish a predetermined priority between this queue and the second receiver circuit.
An object of the present invention is to provide a network of the above type, but wherein the control means do not necessitate either the use of a queue or the establishment of a processing priority.
According to the invention, this object is achieved in an arrangement in which control means comprise a multiplexer/demultiplexer circuit controlled by said routing information and adapted to cyclically read out said first and said second receiver circuits and to route packets stored in the I, 2 receiver circuit thus read out to the transmitter circuit selected by means of said routing information contained in these packets.
Because the multiplexer/demultiplexer circuit cyclically reads out the two receiver circuits, no queue is required, thus reducing the volume of the control means. This is a serious advantage especially when these control means have to be integrated on a chip. Also no priority whatsoever has to be established a priori.
The above mentioned and other objects and features of the invention will become more apparent and the invention itself will be best understood by referring to the following description of an embodiment taken in conjunction with the accompanying drawings wherein: Fig. 1 shows a communication network according to the invention; Fig. 2 represents node N1 and terminal station Ul of the communication network of Fig. I in more detail; and Fig. 3 also represents node !lI, but provided with a node failure protection circuit.
The communication network shown in Fig. 1 is a Local Distribution Network of the type Broadband Integrated Services Data Network (ISDN) including several terminal stations Ul to U5 respectively connected to identical nodes Ni to N5 which are constituted by switching systems (SW1) described below and interconnected so as to form a ring network topology. A terminal station U1/U5 may for instance be a telephone subset, a video-phone set, a television set, a personal computer, a radio, a telecommunication exchange or another ring network, In the ring network shown, signals such as voice, computer data and video are transmitted between these terminal stations Ul to U5 under the form of data packets and in the single direction indicated by the arrow A. Each packet circulating in the ring network includes a header containing routing information indicating to the node N1/N5 to which it is supplied whether this packet has to be routed further in the ring network or is destined to the terminal station U1/U5 connected to this node I, 3 The bit-rate of transmission of the signals may be different for each ring segment, i.e. between two nodes N1-N5, of the ring network with a maximum value of, e.g. 560 Mega-bits/second.
Each switching system (SW1) constituting a node N1/N5 is for instance of the type disclosed in\) a..opra.ticn. s.a.n
E
7 and uses switching techniques called Fast Packet Switching (FPS) or by Asynchrone Time Division (ATD). Node NI, to which terminal station Ul is connected, is represented in more detail in Pig. 2. The node N1 or more particularly its switching system (SW1) includes control means constituted by a central Time Division Multiplex (TDM' switching bus SB whose operation is controlled by a timing circuit SEC and which is able to transmit packets of data from any of 8 receiver circuits to any of 8 transmitter circuits.
However, since in the present case the packets circulate in the ring only in a single direction and that only one terminal station Ul i! connected to the node N1, only 2 receiver circuits RCO and RC1 and 2 transmitter circuits TCO and TC1 are required and represented in Fig. 2. This node N1 has a first input terminal RO and a first output terminal TO connected ring segments of the network to the first receiver circuit RCO and to the first transmitter circuit TCO respectively. N1 also has a second input terminal Rl and a second output terminal TI connecting the terminal station II1 to the second receiver circuit RC1 and to the second transmitter circuit TC1 respectively. Both the receiver circuits RCO and RC1 are connected to the switching bus SB which is itself further connected to both the transmitter circuits TCO and TC1.
It is to be noted that although in the present case the switching capacity of the disclosed node is not fully exploited, i.e. that only 2 of the 8 receiver and transmitter circuits are used, its use is economic because, due to its wide use in telecommunication switching networks, it has been possible to reduce its production cost. The switching capacity of this switching system is for instance fully exploited in a broadband ISDN 4 Q 0
*^S
switching network such as the one disclosed in\?aeteRt C cp tin Tra r Anumber :\3B-1 9 2 to exchange packets of data between terminal stations which generally are subscriber stations.
A packet travelling on the ring network is supplied to the receiver circuit RCO of the node N1 via its input terminal RO and has its header analyzed by this receiver circuit RCO. Depending on the routing information contained in this header, the packet is then routed to the transmitter circuit TCO or TC1 via the switching bus SB. In practice, if the routing information is recognized by the receiver circuit RCO as indicated the relative address of the transmitter circuit TC1, for instance the number 1, or of the terminal station Ul connected thereto, the packet is routed to this terminal station Ul via the transmitter circuit TC1 and the output terminal T1. In the other case, i.e. when the routing information is not recognized by the receiver circuit RCO, the packet is transferred to the transmitter circuit TCO and so further on the ring network via the output terminal TO.
Since packets may be simultaneously present in the receiver circuits RCO and RC1 and can be destined to a same transmitter circuit, e.g. TCO, the transmitter circuits TCO and TC1 are each provided with a buffer queue QO and Ql respectively so that the peak transmission rate of these transmitter circuits TCO and TC1 is not exceeded. The length of this buffer queue QO/Q1 is so calculated that the risk of overflow is lower than a predefined probability for an assumed maximum traffic load at the input terminals RO and Ri. In each receiver circuit RCO and RC1 a respective buffer BO and Bl having the length of one packet of data is provided to ensure that an incoming packet is delayed over a maximum of one TDM switching bus SB cycle. In order to be able to transfer all incoming packets sufficiently fast, the minimum TDM speed or bit-rate of the switching bus SB is at least equal to the sum of the bit-rates of the data signals arriving to the different receiver circuits RCO and RC1. In other words, the maximum N 0o i TDM cycle duration of the switching bus SB is equal to less than the time needed to receive one packet at any receiver communication RCO/RC1.
It is to be noted that a node is in fact a statistical multiplexer/demultiplexer. Indeed, all the incoming packets from different receiver circuits RCO and RC1 may be routed to one single transmitter circuit TCO/TC1 (multiplexing) or be distributed to different transmitter circuits TCOO and TC1 (demultiplexing).
Each node is provided with a signal regenerator (not shown) to reshape the data signals before transmitting them to the ring network. Moreover, to prevent the ring from becoming inoperative by a failure of a node each node is bypassed by a protection circuit allowing the transmission of the packets of data.
When optical fibres are used as ring segments, such a bypass circuit is constituted by an optical fibre path presenting a certain attenuation for the signals flowing through it. In this way, when all the nodes N1 to operate normally, the signals regenerated in each node N1/N5 are strong enough to over-ride those passing through and attenuated by the bypass circuit. In case of failure of a node N1/N5, the signals only pass through the bypass circuit of that faulty node N1/N5 and are so supplied to the receiver circuit RCO of the next node whose signal regenerator compensates the loss of amplitude caused by the preceding bypass attenuator circuit.
It is to be noted that in this case of optical transmission, all the receiver circuits RCO connected to the ring network are provided with an optical receiver and all the transmitter circuits TCO connected to this ring network are provided with an optical transmitter.
When electrical connections are used as ring segments, e.g. coaxial cables, each bypass circuit is constituted by a diode Dl and each node is provided with an additional equipment such as shown in Fig. 3 for the node N1. The bypass diode Dl is connected between terminals R'O and T'O of the ring segments and the node N1 is also connected to the ring net-
_ITXLII*-~-~I-UIY-~I
I
work via these terminals R'O and T'0. Terminal R'0 is connected to input terminal RO of the switching system SW1 by a capacitor CR, whilst output terminal RO of this switching system SW1 is connected to terminal T'0 via a capacitor CT identical to CR. R'O is further connected to a reference voltage VR (ground) via a current sink IR sinking a constant DC current I, whilst this same reference voltage VR is connected to T'0 via a current source IT generating a sane constant DC current I. The capacitors CR and CT prevent the DC current I to flow through the switching system SW1 but allow the packets of data to flow thrcugh it. When this node N1 is operative, the current source IT coupled to SW1 generates a DC current I which flows to the next node, i.e. N2 (Fig. additionally to the signals already present in the ring network. Tis DC current I is sunk in the current sink IR of the node N2. The same is true for a DC current I generated by the current source IT of the node preceding Nl, e.g. N5, and which will be sunk in the current sink IR of the node N1. As a consequence, when all the nodes N1 to N5 are active constant DC currents I flow from current sources IT to current sinks IR and no current flows through the diodes Dl which remain thus blocked. However, when a node, e.g. N1, is inactive, faulty or when it is removed from the ring network, the DC current I generated by the current source IT of the preceding node N5 can only be sunk by the current sink IR of the node N2 normally following N1. So, the diode Dl present at the location of the node Nl becomes conductive because of this DC current I. As a result, all the packets of data circulating on the ring i network between N5 and N2 are flowing through the diode Dl of the node N1 and the operation of the ring network is not affected.
The ring network may be folded so as to form a bus topology with two wires or coaxial cables, one for each transmission direction. Other network top topologies such as a star or an hybrid structure are also possible. However, the above unid:.rectional ring network is preferred because of its point-to-point transmission between nodes which avoids reflections 7 problems and because only one receiver circuit RCO and one transmitter circuit TOO are connected to this network. A ring network may also easily be extended by making an opening, generally at the location of a node and by inserting there a new ring segment.
While the principles of the invention have been described above in connection with specific apparatus, it is to be clearly understood that this description is made only by way of example and not as a limitation on the scope of the invention.
I.

Claims (10)

  1. 2. A communication network as claimed in claim i, wherein said trans- mitter circuits each include a buffer queue for storing packets of data provided by said control means prior to transmitting them on said network. 4 3. A communication network as claimed in claim 1, wherein said re- ceiver circuits each include a buffer for storing at least one of said packets of data before it will be read out by said control means.
  2. 4. A communication network as claimed in any one of claims 1 to 3, wherein the bit-rates at which the data are received by at least two of said first receiver circuits are different. L -1 1- 1 1- A communication network as claimed in any one of claims 1 to 4 wherein at least one node the bit rates at which data are received by the first and the second receiver circuits are different.
  3. 6. A communication network as claimed in claim 4 or claim 5, wherein said control means transfer said data read out in a receiver circuit to a transmitter circuit at a bit-rate which is at least equal to the sum of the bit-rates at which data are received by said first and second receiver cir- cuits.
  4. 7. A communication network as claimed in any one of claims 1 to 6, wherein the bit-rates at which the data are transmitted by at least two of said first transmitter circuits are different.
  5. 8. A communication network as claimed in any one of claims 1 to 7 wherein in at least one node, the bit rates at which data are transmitted by the first and the second transmitter circuits are different.
  6. 9. A communication network as claimed in any one of claims 1 to 8, wherein said ring segments are optical fibres, and wherein each oi' said first receiver circuits is provided with an optical receiver, whil 3t each of said first transmitter circuits is provided with an optical transmitter. A communication network as claimed in claim 9, including at least one node failure protection circuit constituted by an optical fibre circuit able to attenuate signals flowing through it and bypassing said node.
  7. 11. A communication network as claimed in any one of claims 1 to 8, in- cluding protection means against node failure comprising at each node lo- cation a diode which bypasses said node and, associated to each node, a current sink coupled to the anode of said diode, a first capacitor coupled between said anode and the first receiver circuit of said node, a current source coupled to the cathode of said diode and a second capacitor coupled between the first transmitter circuit of said node and said cathode.
  8. 12. A communication network as claimed in any one of claims 1 to 11, (herein it constitutes a broadband integrated services data network to transfer signals such as voice, computer data and video between said termi- nal stations.
  9. 13. A communication network substantially as herein described with ref- erence to Figs. 1 to 3 of the accompanying drawings. DATED THIS NINTH DAY OF JULY, 1990 ALCATEL N.V.
  10. 41.LI*I~L\ ,zo r r i, L i"
AU12630/88A 1987-03-18 1988-03-04 A packet switching network Ceased AU602058B2 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
BE8700281A BE1000395A4 (en) 1987-03-18 1987-03-18 Communication network.
BE8700281 1987-03-18

Publications (2)

Publication Number Publication Date
AU1263088A AU1263088A (en) 1988-09-22
AU602058B2 true AU602058B2 (en) 1990-09-27

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AU12630/88A Ceased AU602058B2 (en) 1987-03-18 1988-03-04 A packet switching network

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AU (1) AU602058B2 (en)
BE (1) BE1000395A4 (en)
ES (1) ES2006596A6 (en)
WO (1) WO1988007295A1 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FI85319C (en) * 1990-06-21 1992-03-25 Valtion Teknillinen The coupling element.

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3652867A (en) * 1970-05-28 1972-03-28 Milton Bocin Device for connecting a substitute current path in case of line break
GB2133952A (en) * 1982-12-22 1984-08-01 Int Standard Electric Corp Multiple-ring communication system
WO1987004579A1 (en) * 1986-01-24 1987-07-30 Alcatel N.V. Switching system

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2363954A1 (en) * 1976-09-03 1978-03-31 Lannionnais Electronique Priority switching system for centralised exchanges - consists of solid state circuitry and is based on inhibit circuit operating at given threshold level

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3652867A (en) * 1970-05-28 1972-03-28 Milton Bocin Device for connecting a substitute current path in case of line break
GB2133952A (en) * 1982-12-22 1984-08-01 Int Standard Electric Corp Multiple-ring communication system
WO1987004579A1 (en) * 1986-01-24 1987-07-30 Alcatel N.V. Switching system

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Publication number Publication date
WO1988007295A1 (en) 1988-09-22
AU1263088A (en) 1988-09-22
BE1000395A4 (en) 1988-11-22
ES2006596A6 (en) 1989-05-01

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