AU598720B2 - An automatic vehicle identification system consisting of a numberplate with a luminous strip and of a remote optical decoder - Google Patents

Description

PATENTS ACT 1952 P/00/011I Form COMPLETE SPECIFICATION

(ORIGINAL)

F43R OFFICE USE Short Title: Int. Cl: Application Number: EsZ 0 Lodged: /79/L 'Complete Specification-Lodged: Accepted: Lapsed: Published: P~riority: This document contains the amendments made under section 49 and is correct for printin g.J S0 10O53 1 Related Art: 04 10 /:9 TO BE COMPLETED BY APPLICANT Name of Applicant: R 5E\_ P f -A Fp, Address of Applicant: P S~IY-CY 91 Actual Inventor: .~.\11NE.

N-9 \Aj Glc Address for Service: A' 'V$'If 1 Complete Specification for the invention entitled: PhrN No MJEI\U 1AE'tV The Wow~ing statement is a full description of this invention, including the best method of performing it known to me:-* Note: The description is to be typed in double spacing, pica type face, in an area not exceeding 250 mm in depth and 160 mm in width, on tough white paper of good quality and it is to be inserted inside this form.

14599/78-L 1459/7-LPrinted by C. THOMPSON, Commionwealth Government Printer, Canbi.rra Page 1 AN AUTOMATIC VEHICLE IDENTIFICATION SYSTEM CONSISTING OF A NUMBERPLATE WITH A LUMINOUS STRIP AND OF A REMOTE OPTICAL DECODER 1. Introduction.

A. General Description.

This system makes possible the automatic identification of vehicles. It consists of a vehicle numberplate incorporating a luminous strip and of a remote optical decoder. The system in effect amounts to a high-tech extension of the concept of numberplates which have identified vehicles since the earliest days of motorised transport. The vehicle numberplate, while conventionally displaying the vehicle registration identification in legible characters (letters and digits), also incorporates a rectangular strip which emits visible light when the ignition is started. To the unaided eye, the light appears steady, but in actual fact it is pulsed on and off at a rapid rate by an electronic circuit fixed to the back of i the numberplate and powered by the vehicle battery. The sequence of pulses is encoded with the characters identifying the vehicle registration, together with a State identifier character and a redundancy-check character. The State identifier (for example, the prefix for New South Wales registered vehicles), is necessary because of the fact that '2 i a vehicle registration from one State miqht otherwise coincide with that from another. The redundancy-check character is an extra character determined by the preceding characters and serves as a check of the correctness of any subsequent decoding process by an optical decoder. Such an optical decoder at a distance, for instance mounted by the roadside and aimed at the passing traffic, decodes the pulse sequence emitted from each vehicle and thereby identifies its registration.

B. Possible uses and advantages.

The uses of this automatic vehicle identification system are envisaged to be as follows: Automatic collection of road tolls, as for example bridge tolls. If vehicles were fitted with the lightencoded numberplates and optical decoders were provided at toll points, tolls could be collectea without the need for toll-collectors (for example, by storage of vehicle registrations in computer memory for regular billing of the registered owners), and without requiring vehicles to slow down at toll points.

I i l I i I -rl -i i I ii~ Page 2 (ii) Detection of stolen vehicles. Optical decoders by the roadside could be programmed remotely, by radio link or telephone lines, to respond to stolen-vehicle numberplates. Optical decoders could also be carried in private vehicles and appropriately programmed by drivers who had volunteered to help search for stolen vehicles. The fact that numberplates emitted visible light (and not, say, invisible infra-red) would thwart any casual tampering by a vehicle thief, and careful design of the numberplate and of its connections to the vehicle battery would make even expert tampering a risky procedure. Thus light-encoded numberplates would form the basis of a system of greatly increased deterrence against vehicle theft.

(iii) Simultaneous measurement of traffic speeds and identification of traffic.

An optical decoder with two photosensitive areas at a small horizontal separation from each other could measure the speed of a passing vehicle through the measurement of the small time-interval between successive responses from the two areas. Since the light impinging on these areas also carries the registration identification, the optical decoder would simultane ously measure speed and identify the vehicle. This double function contrasts Sfavourably with police radar, which has only the single function of measuring speed and so leaves the identification of the vehicle in question as a separate, and contentious, issue. It is also worth noting that, as a novel means of enhancing road safety, fixed roadside 3C decoders, simultaneously measuring speed and identifying the vehicles, could be used not only for collecting fines from speeding drivers, but also for rewarding those who complied with speed limits.

4 2. Distinction between essential features and preferred embodiments of the invention.

The essential features are: an area on the surface of an otherwise conventional numberplate emits visible light when the ignition is started; this light appears steady to the eye, but is modulated so as to transmit information regarding the vehicle registration identification; (3) the information is unambiguous and permits checking for internal consistency through the use of redundancy.

1:% Page 3 That the light should be visible is an essential feature to thwart tampering, as mentioned in 1 B(ii) above. That it should appear steady to the eye is also ar essential feature, since any perceptible flicker would be annoying and distracting to other road users. The modulation of the light as described below is therefore a very fast modulation that the eye cannot follow, whether in direct or peripheral vision, so that it sees a steady light.

Preferred embodiments comprise frequency-shift keying as the preferred form of modulation of the light, the use of an "overall-start" frequency, the mutual ratios of the frequencies, and an extra (State) identifier to remove ambiguity in the registration identification.

Some of the attributes to be described are neither essential features nor even necessarily preferred embodiments, but result from convenience or availability of parts; thus for instance the use of ASCII (American Standard Code for Information Interchange), the method of formation of the essential redundancy-check character, the red colour of the light, F0 the use of eight light-emitting diode chips, the type of ROM, the components of the decoder circuitry and the alphanumeric display.

S3. Constructional and electronic details.

A. Physical appearance, encoding logic and circuitry of the numberplate.

Physical appearance and construction.

The numberplate, ABCD in Figure i, conforms overall to the standard shape and size in New South Wales, Australia: it is rectangular with a length of 375 mm along the longer (horizontal) dimension AB or DC and 138 mm along the shorter (vertical) dimension BC or AD. A rectangular slit EFGH 80 mm long and 20 mm wide is cut with its upper edge EF 20 mm from the top edge AB of the numberplate, and its centre coinciding with the central vertical axis of the numberplate, as shown in Figure i. The conventional legible registration identification characters (not shown in Figure and any required logos, emblems, slogans or the like, are positioned in the rectangular area approximately denoted by IJKL in Figure i, that is, occupying almost the entire horizontal extent of the numberplate and that part of its vertical extent below the slit.

in the slit are positioned eight rectangular light-emitting diode (LED) chips, each 20 mm long and 10 mm wide, these eight being in two rows of four and closely packed, as indicated by the lines in the slit EFGH in Figure 1. Each chip contains 8 individual LEDs, so that 64 LEDs are used altogether. The rectangular slit packed with the rectangular I: chips then Page 4 forms the "strip" referred to in the title. The LEDs forn part of a circuit accommodated in a small thin box attached to the back of the numberplate.

These LED chips are a commercially available item, constructed as rectangular blocks 20 mm long and 10 mm wide as stated above, and about 5 mm deep. Inside each chip are 8 LEDs, disposed so that they illuminate the chip front surface which consists of an approximately 19 mm by 9 mm sheet of strongly diffusing (scattering) white plastic. To the rear of each chip are attached 16 pins each 5 mm long for electrical connections. In the present scheme, the front surfaces of all 8 chips are mounted flush with each other and about 2 mm shy of the front surface of the numberplate.

When power from the battery is connected to the circuit, the LEDs light up and their light is visible from in front of the numberplate. The type of LED used in the present scheme produces a red light, but yellow and green LEDs of the same physical structure are also available, and one can envisage a fully implemented scheme where the front numberplate emits 29 yellow light and the back numberplate red light. The present combined intensity of the 64 LEDs and the existing decoder i sensitivity permit decoding at a distance of about 9 metres.

The light appears steady to the unaided eye, but is in actual Sfact modulated at a rapid rate. All the 64 LEDs, each with a ballast resistor in series, are driven in parallel and modulated in synchronism with one another. The reason for the use of eight LED chips, instead a single LED, is the higher intensity of light emitted, and the eight LED chips could be replaced with a single large LED should such a larger and more powerful LED eventually become available. Each LED in the present scheme is driven at 20 mA peak (mean current of 10 mA), and the total current consumption of the numberplate circuitry is 660 mA. By bright daylight the strip appears pinkish-red and can be easily discerned by eye at 20 to 30 metres.

By night the strip appears a brighter and deeper red, but duller than the normal dipped headlights on either side of the .numberplate.

(ii) Timing and use of frequency-shift keying.

Each character (letter or digit) is represented by a string of six binary digits each of which represents either a zero or a one. The light modulation is of the type known as frequency-shift keying (FSK). This type of modulation confers on the decoding process a high degree of immunity against extraneous interference, including adverse daylight or weather conditions. One particular frequency denotes a "zero", while another particular frequency denotes a "one". The time for each bit to be Page transmitted is 32 microseconds (32 millionths of a second), corresponding to a baud (bit per second) rate of 31.25 kilohertz (kHz). In this time of 32 microseconds, if the light is pulsed on and off five times (that is, off-on-off-on-off-on-off-on f -on-off-on-on), corresponding to a frequency of 5 x 31.25 kHz 156.25 kHz, the bit is a "one". If the light is pulsed on and off seven times, corresponding to a frequency of 7 x 31.25 kHz 218.75 kHz, the bit is a "zero". For all of the three frequencies used, namely 93.75 kHz (see below), 156.25 kHz and 218.75 kHz, the light off-time is always equal to the light on-time, that is, the duty cycle is For decoding purposes each character string of six bits (with the exception of the first character, see below) is preceded by a zero and followed by a one, denoting respectively the start and stop signals for that character.

Thus each character consumes a total of 8 x 32 microseconds 256 microseconds and effectively comprises eight bits.

The complete numberplate sequence consists of the conventional 20 six legible characters, together with a State identifier ib character at the beginning and a redundancy-check character at the end. Thus there are eight characters altogether, therefore consuming a total transmission i time of 8 x 256 microseconds 2048 microseconds or 2.048 milliseconds (thousandths of a second). The start bit for the entire string of 64 bits is given a unique frequency of its own, namely 3 x 31.25 kHz 93.75 klz i As soon as the 64 bits have been transmitted, the cycle starts again. The purpose of the "overall-start" bit, with its unique frequency, is to ensure that if the optical decoder starts to receive light part way through the 64-bit sequence, the rest of that cycle will be ignored, and decoding will commence only upon reception of the overall-start frequency. Thus if the decoder just misses the overall-start S bit, the decoding time will be about 4.096 milliseconds or approximately 1/250 of a second, and the time needed to decode a numberplate sequence will always lie between this upper limit and the lower limit of 2.048 milliseconds.

Since the total time for which the light is on, during the transmission of a bit, is the same whether the bit is a zero or a one, namely 16 microseconds, the average intensity of the emitted light, and therefore the intensity of the light seen by the unaided eye, will not depend on the details of the character string making up the registration identification.

Because the frequencies 93.75 kHz, 156.25 kHz and 218.75 kHz are all multiples of the baud rate of 31.25 kHz, the three frequencies can be generated by the 31.25 kHz clock without discontinuities in phase of the frequency-modulated signal.

Because the three frequencies are in the ratio 3:5:7 and none of these numbers is an integer multiple of either of the other two, crosstalk interference through harmonics is unlikely.

t Page 6 (iii) Use of ASCII coding and formation of redundancycheck character.

The sequence of six bits specifying each character conforms to the 7-bit per character ASCII standard (American Standard Code for Information Interchange). The first ("most significant") bit of the seven bits is always the complement of the second bit (for digits and upper-case letters), and so there is no need to transmit both; hence the choice of six bits transmitted per character in the present scheme.

For convenience in decoding, the six bits of each character are transmitted in reverse order, and the eight characters transmitted are also in reverse order, with the redundancycheck character first and the State identifier last. (For numberplates with less than 6 conventional characters, any convenient non-alphanumeric ASCII character could be used as a filler).

o A simple way of forming a redundancy-check character is as follows. The seven original characters are written in their S (6-bit) ASCII format in seven rows, one for each character.

A parity bit (one or zero) is now placed at the bottom of each of the six columns. This parity bit can be selected S by the following rule: if the number of ones in a column is even, then the parity bit for that column is zero; if the S number of ones in a column is odd, the parity bit for that column is one. The resulting row of six parity bits makes up the (6-bit) ASCII redundancy-check character. The process is illustrated in Table 1 below, where the six conventionally displayed registration identification characters are "MHC469" with a New South Wales electronically coded State identifier prefix making a seven-character string "2MHC469". These seven characters determine the redundancy-check character (the letter), so that the complete emitted string is "2MHC4690".

Table 1. Formation of redundancy-check character.

Character 6-bit

ASCII

2 110010 M 0 0 1 1 0 1 H 001000 C 0 0 0 0 1 1 4 110100 6 110110 9 111001 Parity: 0 0 1 1 1 1 6-bit ASCII 3 i Il Page 7 If p is the (small) probability that a bit is detected incorrectly (a zero for a one or with equal probability a one for a zero), then the probability that a consistent 2 eight-character string is nevertheless formed is 168p If no redundancy-check character were used, the probability that a consistent seven-character string was formed would of course be 1 (certainty). (This argument of course ignores the fact that errors could be detected through the apparent reception of an ASCII string corresponding to a non-alphanumeric character). Thus if p 0.001, the use of a single redundancy-check character gives a probability of only 1 in 6000 that the wrong vehicle could be "identified" through a consistent character string. Thus redundancy-checking serves as a "fail-safe" identification technique.

o (iv) Circuit schematic and realisation, and ROM programming.

000 0000 o0 0 Figure 2 shows the schematic of the numberplate circuitry.

0o_ The 1 MHz frequency of a crystal-co itrolled clock is oD divided by 32 to produce the basic 11.25 kHz baud rate of the bit transmission. This 31.25 kHz frequency is passed through x3, x5 and x7 phase-locked loop (PLL) multipliers oo ~to provide the three frequencies used in the FSK modulation.

The 31.25 kHz frequency is also used to strobe the address lines of a ROM (read-only memory) in which the characters of the numberplate are stored. The output of the ROM is connected to the control inputs of the programmable switch, o, which passes one of the three frequencies every strobe 0o interval (1/31.25 kHz or 32 microseconds) to the LED driver.

0 o0 Figure 3 shows in detail the realisation of this schematic, using CMOS (complementary metal-oxide semiconductor) °310. logic chips. A regulator (not shown in Figure 3) providing S about +9 V powered by the vehicle battery supplies power 00o to the circuit. The total power consumption for one S numberplate is about 9 W. The voltage supply for the ROM is 5 V, whence the use of the 4050 and 7407 buffer chips as level shifters.

00ooo00 The frequency multiplication is performed by the 4046 PLLs with outputs connected back to the inputs through the 4526 programmable binary dividers.

The ROM used here is a 27C64 with 13 address lines and 8 data output lines. Only the least two significant of these data output lines are needed: 00 (pin 11) and 01 (pin 12).

When both these outputs are at logic zero, the frequency passed by the 4051 switch to the LED driver is 218.75 kHz.

When pin 11 is at logic one and pin 12 at logic zero, the frequency passed is 156.25 kHz. When pin 11 is at logic zero and pin 12 at logic one, the frequency pazsed is 93.75 kHz (overall start). Of the 13 address lines, only the 6 lines AO (pin 10) to A5 (pin 5) are needed, and the remaining seven are permanently grounded. These six lines strobed in A. IIiL L 7 1 Page 8 binary sequence (26 64) by the 4520 synchronous divide-bysixteen counter evoke the overall-start bit (output pin 11 at logic zero, output pin 12 at logic one), and then the remaining 63 bits (all with output pin 12 at zero, and output pin 11 variable at zero or one). The 4520 is a dual counter with pin 10 the enabling pin of the second counter.

This pin is set high by the four-input 4082 AND gate when the 16 counts of the first counter have been completed.

Table 2 below shows the complete ROM programming for the numberplate sequence 2MHC4690. The unneeded data output lines 02 to 07 inclusive are permanently at zero.

4 o 44t 4 $44'( Table 2. ROM programming for 2MHC4690.

(note reverse ordering) Address Output lines 01 00 overall start "0" 1 stop 0 start 44$ 4d 4 01 0 0 4 4 "1191 0 1 0 1 stop start "6" 0 1 1 stop (continued) I Page 9 Table 2 (continued) Address Output lines 01 00 24 0 0 start 0 0 26 0 0 27 0 1 "4" 28 0 0 29 0 1 0 1 31 0 1 stop 32 0 0 start 33 0 1 34 0 1 0 0 "C" 36 0 0 37 0 0 38 0 0 39 0 1 stop 0 0 start 41 0 0 42 0 0 43 0 0 "H" 44 0 1 0 0 46 0 0 47 0 1 stop 48 0 0 start 49 0 1 0 0 51 0 1 "M" 52 0 1 53 0 0 54 0 0 0 1 stop 56 0 0 start 57 0 0 58 0 1 59 0 0 "2" 0 0 61 0 1 62 0 1 63 0 1 stop Page B. Circuitry of the optical decoder.

The light signal can of course be decoded using many different techniques; the following scheme using hardwired logic was found to operate satisfactorily.

Figure 4 shows the schematic of the optical decoder. The incident light generates current through the photodiode which then produces a signal at the output of the amplifier. If this signal is at the overall-start frequency of 93.75 kHz, the lower phase-locked loop demodulator, tuned to this frequency, will open the gate to pass the subsequent demodulated signals from the upper demodulator, tuned to a central frequency of 187.50 kHz. These demodulated signals are "one" for 156.25 kHz and "zero" for 218.75 kHz, the mean of these frequencies being the 187.50 kHz central frequency, and are passed to the UART (universal asynchronous receivertransmitter). The UART operates here only in its receiver mode and converts the serial signals for each group of eight bits to parallel format for simultaneous delivery as an alphanumeric character an upper case A to Z or a digit from 0 to 9) to an eight-window 16-segment LED 0 alphanumeric display.

oo.. The UART is driven by a 500 kHz clock, so that 16 cycles S of this clock comprise one bit and every 128 cycles a complete character is received, including its start and °oo stop bits. When this happens the data ready (DR) output S pulse of the UART controls a programmable switch and advances a synchronous counter to enable writing to the appropriate sections of the alphanumeric display. This display then shows the eight characters of the numberplate.

S 30 When there is no optical signal the phase-locked loop of the upper demodulator will be out of lock. This condition Swill appear as a low level on the lock-detect output of the o upper demodulator. The low level applied to the NAND o o, gate will disable any further writing to the alphanumeric 0 oo display. Figures Sa to 5d show the realisation of this Sschematic.

S Figure 5a shows the BPW34 photodiode with 12 V reverse .o.ns bias connected to the high slew-rate LF351 operational amplifier. The photodiode is positioned at the focus of a circular converging lens of 65 mm diameter and 130 mm focal length. Both photodiode and amplifier are mounted inside a grounded metal box with matt-black-painted inner and outor surfaces, the only means of entry for light into the bo b in.g through the lens which accurately fills a cirt1ular holoe ut; ,lin ono side. No optical filters were used. 'i'hi box j mounoted on a tripod for conrenient aiming.

Page 11 The output of the amplifier is connected by coaxial cable to the rest of the circuit (Figures 5b, c and d) in another grounded metal box. When the separation between numberplate and the illuminated photodiode is about 9 metres, the peak-to-peak signal at the output of the amplifier is about 100 mV.

The output of the LF351 is connected to the inputs of two I XR2211 demodulators, the upper one configured so as to produce at pin 7 a high logic level for 156.25 kHz and a low logic level for 218.75 kHz. The logic level at pin 6 of the upper XR2211 is high when its phase-locked loop is in lock, that is when a sufficiently strong optical signal is present at either 156.25 kHz or 218.75 kHz. The level at pin 6 is low when the optical signal is absent or too weak, and will then disable any further writing to the 4 alphanumeric display in Figure 5d and will reset the UART, the 4013 D flip-flop 3 and the 4520 synchronous counter in Figure 5c. This disabling and resetting are done using the Smultiple-input 4023 NAND gate and the two-input 4093 NAND S 29,q gate 7 in Figure Figure 5b shows the circuitry of the 500 kHz clock used to 4 '2 drive the D flip-flops and the 6402-1 UART in Figure I The reference is a 1 MHz crystal (without any temperature control) in the feedback loop of a 4001 NOR chip. A divide- S by-2 counter (the 4040) produces 500 kHz with accurate duty cycle.

The level at pin 6 of the lower XR2211 is high when the overall-start frequency of 93.75 kHz is present. In Figure this level and that from pin 7 of the upper XR2211 are connected to two pairs of Schmitt-tr.igger 4093 NAND circuits (1 to 4) for pulse squaring, and then to the D inputs of flip-flops 1 and 2. If the overall-start frequency of 93.75 kHz has not yet arrived, output Q of 4 flip-flop 2 is low, output Q of flip-flop 3 is therefore also low and so the output of the 4093 NAND gate 6 is high.

i The RRI (receiver register input, pin 20) of the UART is I therefore high and the UART cannot accept data. (The small triangles in Figure 5c denote the buffer chips 4050 and its f complement 4049, used for shifting high logic levels from the normal +12 V level to the +5 V level appropriate to the S, UART and to the alphanumeric display in Figure 5d. For restoring the logic level to +12 V, or for complementing 0, +5 V logic levels, the TTL 7406 chip is used and is also shown as a small triangle in Figures 5c and 4 Page 12 When the overall-start frequency arrives, the input to the 4093 NAND gate 3 goes high, the Q output of flip-flop 2 goes high and sends the Q output of flip-flop 3 also high.

Flip-flop 3 is not clocked by the 500 kHz clock, but instead by the Q output of flip-flop 2, and flip-flop 3 therefore functions as a latch. The high level of the Q output of flip-flop 3 is also the level of the lower input of 4093 NAND gate 6. Regardless of the input to the 4093 NAND gate 1, the RRI input of the UART is now sent low, signifying a start bit for the UART, because the complement output Q of flip-flop 2 has now gone low and has therefore sent the output of 4093 NAND gate 5, and therefore the upper input of NAND gate 6, high; in consequence (since 4093 NAND gate 6 is now enabled by a high on its lower input) the output of 4093 NAND gate 6 is now low. This low output is also the input to the RRI pin of the UART.

The output Q of flip-flop 3 will stay high (until its reset input is sent high), even after the 93.75 kHz signal has ceased and the remaining 63 bits are due to follow. When the 93.75 kHz has ceased, the Q output of flip-flop 2 will a 0go low (but without affecting the output of flip-flop 3), and therefore the complement output Q of flip-flop 2 will go high. The 4093 NAND gate 5 is therefore enabled and will Spass the complement of the string of 63 bits. Since the S 4093 NAND gate 6 is also enabled (because the Q output of S flip-flop 3 is still high), it will pass the uncomplemented string of 63 bits to the RRI input of the UART, which will accept them since it has already received a start (low) pu.se.

3d The 64-02-1 UART organisation of input data is set at 6 data bits with 1 stop bit and no parity checking. The pins CLSl, CLS2, PI, EPE and SBS are set accordingly to the appropriate prescribed logic levels. After the start bit, 6 data bits &A6 stop bit for each character have been received, the DR (data received) output on pin 19 goes high and the data on the six RBR (receiver buffer register) lines are valid.

After a delay through 4013 flip-flop 4 the DR line will reset itself through the negative-going pulse to the data register ii reset (DR-R) pin 18. As the DR line goes low again, it advances the synchronous 4520 counter by one binary step. The least two significant output bits at pin 4 and at pin 3) of this counter are connected to the address inputs Al and AO respectively of the two 1414 alphanumeric display chips. The four binary combinations of Al and AO route the 4_ V 1- lil L o Page 13 data on the six RBR lines to the respective four display windows; thus the combination Al 0 and AO 0 addresses the rightmost display window, which will now display the character sent over the RBR lines. The 1414 alphanumeric display accepts 7-bit ASCII characters, but as mentioned previously, for digits and upper-case letters the first and second most significant bits are mutual complements, whence the purpose of the 7406 inverter in Figure 5d. Which of the two 1414 chips displays the character is determined by the next most significant bit at pin 5) of the 4520 counter. This output is connected to the active control line of the 4052 programmable switch. When the bit is low, that is S for the first four characters, the high DR signal will be ro'2ted to X0 and will therefore enable writing (by a low level to WR) to the right-hand 1414 chip. When the bit is high, that is for the last four characters, the high S DR signal will be routed to Xl and will therefore enable writing to the left-hand 1414 chip. After all eight characters have been received and displayed, the "8" bit (pin 6) of the 4520 counter will reset the circuitry through 4013 flip-flop P a (Pages 14 and 15, to follow, define the Claims) ]i