AU581279B2 - Systolic architectures for sonar processing - Google Patents

Description

SYSTOLIC ARCHITECTURES FOR SONAR PROCESSING

INTRODUCTION

Current sonar systems employ both time and space diversity to achieve a high level of oper- 5. ational performance. This, together with the complex geometry and relatively slow speed of sound propagation in the ocean, has imposed many constraints on the concomitant signal processing system. For example, low sonar operating frequencies and the use of

10. wide-band processing force the use of broad-band beamforming. Further, ever-increasing numbers of hydrophone elements are being used for high spectral resolution and the signal processing system must be capable of forming in parallel large numbers

15. ■ of independent beams in order to attain an .adequate angular cover as well as giving the spectral -resolution. In addition, for towed systems in particular, the geometry of the array may fluctuate. The general effect of these three observations is to impose

20. an enormous computing load on the signal processing system. Some agencies have developed satellite- to-shore systems which can call on the number crunching power of super-computers like the Cray. In the general environment this is not possible and hence

25. there is the necessity to look at parallel computers based on VSLI technology. If such systems are realisable then there is the added advantage that the system can be carried on small platforms such ^• as helicopters and diesel-electric submarines.

30. This invention indicates one possible arch¬

I itecture for implementing a limited class of passive broad-band beamformers . It is found that computing loads approaching hundreds of mega-flops can be achieved conceptually with a minimum of silicon area. It is also found that the systems can be made highly reliable by incorporating a limited 5. form of self repair.

A paper by Speiser, J.M., hitehouse, H.J. and Bromley, K. (1980). 'Signal Processing Applications for Systolic Arrays', Record of the 14th Asimolar Conference on Circuits, Systems and Computers, 10. Pacific Grove, California, IEEE 80CH1625-3 addresses the general question but does not give a clear indication of the power of systolic arrays for particular tasks. In contrast, this paper is concerned with a specific design and implementation.

15. Reference may be had to the specification of Patent Application No. WO 84/04225, published under the provision of the Patent Cooperation Treaty, in which a self repair large scale integrated circuit is described, this application is assigned to the

20. Commonwealth of Australia, having the same inventors as this application namely Marwood, W. and Clarke, A.P.

SYSTOLIC ARCHITECTURES

The invention deals generally with a form 25. of distributed signal processing called a systolic array. The systolic array is a one, two or higher dimensional array of identical processors. In each processor both the hardware and the executed program is identical. Each processor is connected 30. to nearest neighbours, computes data, and then passes data on to its neighbours at all times in synchronism with a master clock. In physiology, the word 'systole' is used for the heart contraction pumping blood. In the systolic array the system 5. clock is the analogue of the heart.

In most sonar signal processing requirements the basic operations can be written in a matrix form. When this is realised it can be seen that each processor can consist of a cascaded sequence

10. of processing blocks where each block is a systolic array executing a matrix operation. Hence the total implementation will consist almost entirely of systolic processing elements. Reference may be had to the papers of Whitehouse, H.J. and Speiser,

15. J.M., 'Sonar Applications of Systolic Array Technology', presented at IEEE Eascon, Washington, D.C., Nov. 17-19, 1981, and Speiser, J.M. and Whitehouse, H.J., 'Parallel Processing Algorithms and Architectures for Real-Time Signal Processing', SPEE Vol. 298,

20. Real-Time Signal Processing IV (1981) paper 298-03.

BEAMFORMING

In conventional beamforming the observation of some propagating, coherent wave in the ambient noise background of the ocean is enhanced by summing 25. time-delayed and weighted hydrophone data. The weights are designed to achieve some specified side-lobe level from a particular array.

The output in a given direction θ is given by k ^bθ^{(t) = ∑ W}n^Xn ^C - ⁸^ ⁽³-D where x (t) is output from hydrophone n w is a weight factor and r (θ) is a time delay to be applied to the n hydrophone to steer in the direction Θ .

5. In digital systems the x are sampled (usually at frequencies 5-10 times Nyquist) and samples from each hydrophone taken as near to the steered direction θ as possible.

In order however that the invention will be 10. better understood, an embodiment of the invention will be described with reference to the accompanying drawings .

FIG. 1 shows a structural schematic of the beamformer. It consists of a linear concatenation 15. of identical modules. Sensor data is input at the left boundary module and weighting coefficients ^•are input to the front boundary of each module. Beam data are output from the bottom face of each module.

20. FIG. 2 shows a functional schematic of two modules and details their interconnection.

FIG. 3 is a functional schematic of a systolic processing element which when connected in a three, dimensional structure of the form of Fig. 2 implements 25. the FIR filter and register stacks of each module.

FIG. 4 shows the logical interconnection of a two dimensional array of the systolic elements of Fig. 3 to implement one module. FIG. 5 shows the modified matrix product required for the formation of a beam sample.

FIG. 6 indicates the data shift operation required at each array sample time,

5. FIG. 7 shows by way of explanation the block diagram of a finite impulse response filter implemental with the systolic elements of Fig. 3.

FIG. 8 shows for explanatory purposes, details of a third order finite impulse response (FIR) filter 10. or convolution implementation, showing the cyclic completion behaviour of the systolic processing elements .

Fig. 1 shows a structural schematic of the object of this invention which is an' interpolation

15. or adaptive beamformer. The figure shows that construction is achieved by concatenating a series of identical modules 1. Sensor data are input at the leftmost module and weighting coefficients are input to the front boundary of each module.

20. Beam outputs are driven out from the bottom face of each module, one beam per module.

A block schematic of the beamformer is shown in Fig. 2 for the case of two beams. It is constructed by replicating modules defined by 2, 3, 4 and 5.

25. The number of replications of the module determines the number of beams the beamformer can process . Module interconnection is demonstrated by the figure. Operation of the beamformer is described in terms of one module only. The FIR filter bank 2 is con-

30. structed from k linear systolic arrays of multiply/ accumulate elements. Each systolic array implements an FIR filter. Each filter is associated with one particular sensor.

The number of FIR filters is determined by the number of sensors, and each sensor broadcasts 5. its data to one systolic array per module. Weighting coefficients are entered serially into the boundary elements of each filter and recirculated. Filter outputs occur cyclically from each element in turn and are input to adjacent linear arrays of registers.

10. These registers are interconnected orthogonally to form a pipelining register stack 3. Data is clocked through the structure synchronously, and the cyclic completion times of the k filters are in phase. This causes the outputs from the ith

15. element of each of the k filters to be loaded syn¬ chronously into one column of the register stack 3 at each successive time period. These ouput samples are clocked through the register stack 3 to the accum¬ ulator bank 4 where the accumulated result is output

20.- after k clock periods. The skewing of the data- present in the columns due to the cyclic behaviour of the filters cause the accumulator element outputs to be cyclic also. These outputs are input to a demultiplexer 5 to recover the correct beam time

25. series.

The inputs are designated X_, , X«, X-.....X, and these go to the FIR filter banks 2. The weights are indicated by r. → _s τ→ -••••r.. , , ^ n • • • -^r _{? k} ^etc-

Fig. 3 shows a functional schematic of a systolic 30. procesing element which when connected in a three dimensional structure of the form of Fig. 2 implements the FIR filters 2 and register stacks 3 of the modules of Figs. 1 and 2. It consists of a pipelining delay element 6 for the r coefficients and a storage delay element 7 for the x coefficients. These co-

5. efficients are multiplied in a multiplier element 8 and the result summed in an accumulator 9. At the completion of the formation of an inner product x.r in the accumulator it is loaded into a register stack element 10.

10. Fig. 4 shows the logical interconnection of a two dimensional array 11 of the systolic elements of figure 3 with an accumulator array 12 and demulti- plexer 13 to implement one module of figures 1 and 2.

15. THE BEAMFORMING TAS^'K ^•

This can be represented in matrix form

tr{ X.S(Θ)} = b_β(t)

where X is the data buffer at time t and S (θ) is a matrix that extracts data from X for

20. Errors are possible due to sampling. Pridham, R.G., and Mucci, R.A. , 'A Novel Approach to Digital Beamforming' I. Acoust, Soc . Am., Feb. 1978 pp 625-434 suggest interpolation as a means of reducing this error. For steering over p angles it is then

25. possible to write a matrix equation

where ^r ₁> ^r2''"'^rk ^{are t}' ^e ^ columns of S which are now occupied by interpolation coefficients, x , x , ... ,x, are the k rows of X

and is an operation giving as the 'inner product' the sum over n of the scalar product ^r _n-^x _n

5. The formation of a single beam is considered

^bl^(θl^{) = Σ r}i^(θl⁾ i=l

,k

= ΣΣ Σ r. . θ.) x. . i=l j=l

where s is the length of the data vector.

A modification to this architecture which removes the necessity to broadcast the input data involves the placement of delay elements in both 10. SPE interconnection paths and also the input data path.

Fig. 5 shows a schematic of the formation of an interpolation beam sample from a data matrix. The beam sample is the trace of the product of 15. the data matrix and a weight matrix. As is shown in the figure, the computation performed by the proposed architecture does not include off-diagonal elements. The computation efficiency is improved over a conventional matrix multiplication by a factor of (k-1), as only k elements are formed,

2 compared to k in the conventional product. The

5. formation of the actual beam sample requires the addition of the k main diagonal elements. This involves k-1 additions.

To obtain the next beam sample, it is necessary to perform the data shift operation detailed in 10. Fig. 6 before performing the modified matrix product. However, the structure of the systolic arrays which perform the convolutions make this data shift naturally. The architecture readily accepts adaptive processes such as the Frost algorithm.

15. In the case of an adaptive algorithm imple¬ mentation, the coefficients are updated as often as is required. Computation of the new coefficients is performed externally to the systolic array.

Figures 7 and 8 show respectively how a finite 20. impulse response filter 15 is implemented with the systolic element of Fig. 3, and how the cyclic completion behaviour of the systolic elements in arrived at. The cyclic completion of the SPE's is not resolved by a demultiplexer as would be 25. necessary in a complete filter implementation. Instead advantage is taken of the spare clock periods between the completion phase of each SPE to clock the data in the pipeline register stack to the accumulator where it is summed.

Claims (1)

1. THE CLAIMS DEFINING THE INVENTION ARE AS FOLLOWS:

   1. A three-dimensional systolic architecture for beamforming according to this invention arranged to accept broadcasted data samples from an array and to convolve them with sets of weighting co-

   5. efficients characterised by a one dimensional array of similar modules (1) having finite impulse response FIR filter elements (2) arranged to have their outputs directed into pipelining register stacks (3) and propagated to the stack boundaries, and summed at the 10. stack boundaries in accumulator arrays (4) and passed through demultiplexers (5) to the beamformer output ports.

   2. A three-dimensional systolic architecture ^• according to claim 1 wherein each FIR filter (2) connects to one sensor (x) whereby each sensor (x) broadcasts its data to one systolic array per 5. module.

   3. A three-dimensional systolic architecture according to claim 1 or 2 wherein each module (1) comprises a two dimensional array of both FIR filter elements (2) and pipelining stacks (3), said FIR filter

   5. element (2) comprising a pipelining delay element (6) for the weighting coefficients (r) and a storage delay element (7) for the x coefficients, said filter element (2) including a multiplier element (8) and an accumulator (9), the said pipelining delay element (6) 10. and the storage delay element (7) being arranged to output to the multiplier element (8) which in turn is arranged to output the product to the accumulator (9) from where the x.r product is loaded into a register stack (10) . 4. A three-dimensional systolic architecture according to claim 1 or 3 arranged to recirculate the weighting coefficients to allow the beam former to accept sensor inputs (X) and compute beam outputs

   5. without continuous entry of weighting information.

   5. A three dimensional systolic architecture according to claims 2, 3 or 4 wherein the said circuitry is so arranged that the FIR filter elements 2 are incompletely implemented whereby accumulation of

   5. the result is made possible in the spare clock periods.

   6. A three dimensional systolic architecture according to claim 1 characterised in that replicated modules (1) used equal the number of beamformers required and the FIR filter bank (2) is constructed

   5. from linear systolic arrays of multiply/accumulator elements (4) and each systolic array implements one said FIR filter of the filter bank (2) and each filter is associated with one particular sensor, further characterised in that each sensor broadcasts its data

   10. ' to one systolic array per module (1) and weighting coefficients are entered serially into the boundary elements of each filter of the bank (2) and re¬ circulated, the outputs of the said filter banks (2) being arranged to occur cyclically from each element in

   15. turn and are directed to input to adjacent linear arrays of registers which are interconnected orthog¬ onally to form a pipelining stack (3).

   7. A three dimensional systolic architecture according to claim 6 further characterised in that the circuitry is arranged so that data is clocked through the structure synchronously and cyclic completion times 5. of the elements of the filter banks (2) are in phase whereby the completed convolution sums are loaded synchronously into one column of the register stack (3) at each successive period of time and the outputs are input to the said demultiplexer (5) to recover the 10. correct beam time series.

   8. The method of data collection using a three-dimensional systolic architecture which consists in

   (a) collecting information on transducers such as 15* hydrophones and passing the signal of each transducer to an array of similar modules (1),

   (b) passing the signal input to each module to a linked FIR filter bank (2),

   (c) passing the output from the filter bank (2) 20. to a pipelining register stack (3), and

   (d) accumulating and demultiplexing in an accumulator (4) and a demultiplexer (5) to form a beam (b) whereby a series of beams are produced.

   9. The method of data collection according to claim 6 wherein the said FIR filter banks are in¬ completely implemented.