AU560782B2 - Delayed serial digital data sequence transmission - Google Patents

Delayed serial digital data sequence transmission

Info

Publication number
AU560782B2
AU560782B2 AU54182/86A AU5418286A AU560782B2 AU 560782 B2 AU560782 B2 AU 560782B2 AU 54182/86 A AU54182/86 A AU 54182/86A AU 5418286 A AU5418286 A AU 5418286A AU 560782 B2 AU560782 B2 AU 560782B2
Authority
AU
Australia
Prior art keywords
digital data
data sequence
serial digital
sequence transmission
delayed serial
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
AU54182/86A
Other versions
AU5418286A (en
Inventor
Peter-Grauer Jensen
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Siemens AG
Original Assignee
Siemens AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens AG filed Critical Siemens AG
Publication of AU5418286A publication Critical patent/AU5418286A/en
Application granted granted Critical
Publication of AU560782B2 publication Critical patent/AU560782B2/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F5/00—Methods or arrangements for data conversion without changing the order or content of the data handled
    • G06F5/06—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor
    • G06F5/10—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor having a sequence of storage locations each being individually accessible for both enqueue and dequeue operations, e.g. using random access memory
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/04—Arrangements for selecting an address in a digital store using a sequential addressing device, e.g. shift register, counter
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H17/00—Networks using digital techniques
    • H03H17/0009—Time-delay networks
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2205/00—Indexing scheme relating to group G06F5/00; Methods or arrangements for data conversion without changing the order or content of the data handled
    • G06F2205/10—Indexing scheme relating to groups G06F5/10 - G06F5/14
    • G06F2205/104—Delay lines

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Use Of Switch Circuits For Exchanges And Methods Of Control Of Multiplex Exchanges (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Communication Control (AREA)
AU54182/86A 1985-03-01 1986-02-28 Delayed serial digital data sequence transmission Ceased AU560782B2 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE3507326 1985-03-01
DE19853507326 DE3507326A1 (en) 1985-03-01 1985-03-01 ARRANGEMENT FOR THE DELAYED FORWARDING OF SERIAL APPLICABLE DIGITAL DATA SEQUENCES

Publications (2)

Publication Number Publication Date
AU5418286A AU5418286A (en) 1986-09-04
AU560782B2 true AU560782B2 (en) 1987-04-16

Family

ID=6263957

Family Applications (1)

Application Number Title Priority Date Filing Date
AU54182/86A Ceased AU560782B2 (en) 1985-03-01 1986-02-28 Delayed serial digital data sequence transmission

Country Status (3)

Country Link
EP (1) EP0193765A3 (en)
AU (1) AU560782B2 (en)
DE (1) DE3507326A1 (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2647988A1 (en) * 1989-05-30 1990-12-07 Trt Telecom Radio Electr DEVICE FOR DELAYING A PROGRAMMABLE DIGITAL SIGNAL AND APPLICATION TO AN ERROR-CORRECTING DEVICE
KR0152396B1 (en) * 1995-10-31 1998-11-02 정선종 Pcm data delay circuit

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
SE328918B (en) * 1969-02-18 1970-09-28 Ericsson Telefon Ab L M
US4271483A (en) * 1977-08-04 1981-06-02 Independent Broadcasting Authority Delay circuits
JPS5733409A (en) * 1980-08-06 1982-02-23 Sony Corp Reproducer of coded signal
JPS5963812A (en) * 1982-10-04 1984-04-11 Hitachi Ltd Variable length delay circuit

Also Published As

Publication number Publication date
EP0193765A3 (en) 1990-01-31
EP0193765A2 (en) 1986-09-10
DE3507326C2 (en) 1993-04-01
DE3507326A1 (en) 1986-09-04
AU5418286A (en) 1986-09-04

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