AU5447396A - Method and structure for polishing a wafer during manufacture of integrated circuits - Google Patents

Method and structure for polishing a wafer during manufacture of integrated circuits

Info

Publication number
AU5447396A
AU5447396A AU54473/96A AU5447396A AU5447396A AU 5447396 A AU5447396 A AU 5447396A AU 54473/96 A AU54473/96 A AU 54473/96A AU 5447396 A AU5447396 A AU 5447396A AU 5447396 A AU5447396 A AU 5447396A
Authority
AU
Australia
Prior art keywords
polishing
integrated circuits
during manufacture
wafer during
wafer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
AU54473/96A
Inventor
Michael A. Leach
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
MICHAEL A LEACH
Original Assignee
MICHAEL A LEACH
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by MICHAEL A LEACH filed Critical MICHAEL A LEACH
Publication of AU5447396A publication Critical patent/AU5447396A/en
Abandoned legal-status Critical Current

Links

Classifications

    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B24—GRINDING; POLISHING
    • B24B—MACHINES, DEVICES, OR PROCESSES FOR GRINDING OR POLISHING; DRESSING OR CONDITIONING OF ABRADING SURFACES; FEEDING OF GRINDING, POLISHING, OR LAPPING AGENTS
    • B24B37/00—Lapping machines or devices; Accessories
    • B24B37/11—Lapping tools
    • B24B37/12—Lapping plates for working plane surfaces
    • B24B37/16—Lapping plates for working plane surfaces characterised by the shape of the lapping plate surface, e.g. grooved

Landscapes

  • Engineering & Computer Science (AREA)
  • Mechanical Engineering (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)
AU54473/96A 1996-04-08 1996-04-08 Method and structure for polishing a wafer during manufacture of integrated circuits Abandoned AU5447396A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/US1996/004864 WO1997037813A1 (en) 1996-04-08 1996-04-08 Method and structure for polishing a wafer during manufacture of integrated circuits

Publications (1)

Publication Number Publication Date
AU5447396A true AU5447396A (en) 1997-10-29

Family

ID=22254936

Family Applications (1)

Application Number Title Priority Date Filing Date
AU54473/96A Abandoned AU5447396A (en) 1996-04-08 1996-04-08 Method and structure for polishing a wafer during manufacture of integrated circuits

Country Status (2)

Country Link
AU (1) AU5447396A (en)
WO (1) WO1997037813A1 (en)

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3430499C2 (en) * 1984-08-18 1986-08-14 Fa. Carl Zeiss, 7920 Heidenheim Method and device for lapping or polishing optical workpieces
JPH0757465B2 (en) * 1988-05-31 1995-06-21 住友金属鉱山株式会社 Method and apparatus for polishing thin film
JPH03196966A (en) * 1989-12-25 1991-08-28 Nec Corp Magnetic disk substrate working abrasive tool

Also Published As

Publication number Publication date
WO1997037813A1 (en) 1997-10-16

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