AU5394490A - Improved scheme for insuring data consistency between a plurality of cache memories and the main memory in a multi-processor computer system - Google Patents

Improved scheme for insuring data consistency between a plurality of cache memories and the main memory in a multi-processor computer system

Info

Publication number
AU5394490A
AU5394490A AU53944/90A AU5394490A AU5394490A AU 5394490 A AU5394490 A AU 5394490A AU 53944/90 A AU53944/90 A AU 53944/90A AU 5394490 A AU5394490 A AU 5394490A AU 5394490 A AU5394490 A AU 5394490A
Authority
AU
Australia
Prior art keywords
computer system
main memory
cache memories
data consistency
processor computer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
AU53944/90A
Other versions
AU631631B2 (en
Inventor
Scott Arnold
Stephen G. Delahunt
Michael E. Flynn
Tryggve Fossum
Ricky C. Hetherington
David A. Webb
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Digital Equipment Corp
Original Assignee
Digital Equipment Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Digital Equipment Corp filed Critical Digital Equipment Corp
Priority to AU53944/90A priority Critical patent/AU631631B2/en
Publication of AU5394490A publication Critical patent/AU5394490A/en
Application granted granted Critical
Publication of AU631631B2 publication Critical patent/AU631631B2/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0815—Cache consistency protocols
    • G06F12/0817—Cache consistency protocols using directory methods
    • G06F12/0822—Copy directories

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
AU53944/90A 1990-04-27 1990-04-27 Improved scheme for insuring data consistency between a plurality of cache memories and the main memory in a multi-processor computer system Ceased AU631631B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
AU53944/90A AU631631B2 (en) 1990-04-27 1990-04-27 Improved scheme for insuring data consistency between a plurality of cache memories and the main memory in a multi-processor computer system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
AU53944/90A AU631631B2 (en) 1990-04-27 1990-04-27 Improved scheme for insuring data consistency between a plurality of cache memories and the main memory in a multi-processor computer system

Publications (2)

Publication Number Publication Date
AU5394490A true AU5394490A (en) 1991-12-19
AU631631B2 AU631631B2 (en) 1992-12-03

Family

ID=3739930

Family Applications (1)

Application Number Title Priority Date Filing Date
AU53944/90A Ceased AU631631B2 (en) 1990-04-27 1990-04-27 Improved scheme for insuring data consistency between a plurality of cache memories and the main memory in a multi-processor computer system

Country Status (1)

Country Link
AU (1) AU631631B2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5727151A (en) * 1990-09-28 1998-03-10 Fujitsu Limited Message control system specifying message storage buffer for data communication system with general purpose and arbitrary form buffers

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4755930A (en) * 1985-06-27 1988-07-05 Encore Computer Corporation Hierarchical cache memory system and method
EP0349123B1 (en) * 1988-06-27 1995-09-20 Digital Equipment Corporation Multi-processor computer systems having shared memory and private cache memories

Also Published As

Publication number Publication date
AU631631B2 (en) 1992-12-03

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