AU5382994A - Cell buffer memory management - Google Patents

Cell buffer memory management

Info

Publication number
AU5382994A
AU5382994A AU53829/94A AU5382994A AU5382994A AU 5382994 A AU5382994 A AU 5382994A AU 53829/94 A AU53829/94 A AU 53829/94A AU 5382994 A AU5382994 A AU 5382994A AU 5382994 A AU5382994 A AU 5382994A
Authority
AU
Australia
Prior art keywords
cell
stream
buffer memory
loss
recorded
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
AU53829/94A
Other versions
AU672066B2 (en
Inventor
Michel Henrion
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Alcatel Lucent NV
Original Assignee
Alcatel NV
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Alcatel NV filed Critical Alcatel NV
Publication of AU5382994A publication Critical patent/AU5382994A/en
Application granted granted Critical
Publication of AU672066B2 publication Critical patent/AU672066B2/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/50—Overload detection or protection within a single switching element
    • H04L49/505—Corrective measures
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/20—Support for services
    • H04L49/205—Quality of Service based
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/50—Overload detection or protection within a single switching element
    • H04L49/501—Overload detection
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/54—Store-and-forward switching systems 
    • H04L12/56—Packet switching systems
    • H04L12/5601—Transfer mode dependent, e.g. ATM
    • H04L2012/5638—Services, e.g. multimedia, GOS, QOS
    • H04L2012/5646—Cell characteristics, e.g. loss, delay, jitter, sequence integrity
    • H04L2012/5647—Cell loss
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/54—Store-and-forward switching systems 
    • H04L12/56—Packet switching systems
    • H04L12/5601—Transfer mode dependent, e.g. ATM
    • H04L2012/5638—Services, e.g. multimedia, GOS, QOS
    • H04L2012/5646—Cell characteristics, e.g. loss, delay, jitter, sequence integrity
    • H04L2012/5651—Priority, marking, classes
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/54—Store-and-forward switching systems 
    • H04L12/56—Packet switching systems
    • H04L12/5601—Transfer mode dependent, e.g. ATM
    • H04L2012/5678—Traffic aspects, e.g. arbitration, load balancing, smoothing, buffer management
    • H04L2012/5681—Buffer or queue management

Abstract

This device receives several cell streams characterised by different cell loss rate performances and comprises means for recognising that a cell loss is inevitable when the buffer memory is full, as well as means for deciding that an incoming cell should be recorded in the buffer memory instead of another cell which will be lost. It furthermore comprises means (CF1..., CFi..., CFn) for associating with each cell stream (FC1..., FCi..., FCn) a dynamic indication of cell loss balance (CLF1..., CLFi..., CLFn), which is a function of a cell loss performance (Ni) allotted to this stream and cell losses (RTi) actually noted for this cell stream, and means (SCDA) for selecting a cell stream, especially by comparing the said dynamic indications of cell loss, and for causing as a consequence the incoming cell to be recorded in the buffer memory instead of a cell of the selected cell stream. <IMAGE>
AU53829/94A 1993-01-27 1994-01-18 Cell buffer memory management Ceased AU672066B2 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR9300799 1993-01-27
FR9300799A FR2700865B1 (en) 1993-01-27 1993-01-27 Cell buffer management device.

Publications (2)

Publication Number Publication Date
AU5382994A true AU5382994A (en) 1994-08-04
AU672066B2 AU672066B2 (en) 1996-09-19

Family

ID=9443401

Family Applications (1)

Application Number Title Priority Date Filing Date
AU53829/94A Ceased AU672066B2 (en) 1993-01-27 1994-01-18 Cell buffer memory management

Country Status (5)

Country Link
EP (1) EP0609128B1 (en)
AT (1) ATE265709T1 (en)
AU (1) AU672066B2 (en)
DE (1) DE69433733T2 (en)
FR (1) FR2700865B1 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6330222B1 (en) 1997-04-17 2001-12-11 Fujitsu Limited Traffic control apparatus and traffic control method used in exchange

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5946318A (en) * 1997-03-21 1999-08-31 International Business Machines Corporation Method and apparatus for processing and packetizing data from a data stream
US6021440A (en) * 1997-05-08 2000-02-01 International Business Machines Corporation Method and apparatus for coalescing and packetizing data

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2947956B2 (en) * 1991-03-05 1999-09-13 株式会社日立製作所 Switching system
US5365519A (en) * 1991-03-05 1994-11-15 Hitachi, Ltd. ATM switch1ng system connectable to I/O links having different transmission rates
CA2012868C (en) * 1989-03-23 1994-03-22 Shin-Ichiro Hayano Call control with transmission priority in a packet communication network of an atm type
CA1320257C (en) * 1989-04-20 1993-07-13 Ernst August Munter Method and apparatus for input-buffered asynchronous transfer mode switching
EP0533900B1 (en) * 1991-04-10 1997-08-06 Koninklijke Philips Electronics N.V. Low delay or low loss cell switch for atm

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6330222B1 (en) 1997-04-17 2001-12-11 Fujitsu Limited Traffic control apparatus and traffic control method used in exchange

Also Published As

Publication number Publication date
EP0609128A1 (en) 1994-08-03
EP0609128B1 (en) 2004-04-28
FR2700865A1 (en) 1994-07-29
DE69433733D1 (en) 2004-06-03
FR2700865B1 (en) 1995-02-24
ATE265709T1 (en) 2004-05-15
DE69433733T2 (en) 2005-04-28
AU672066B2 (en) 1996-09-19

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