AU5294193A - Method and apparatus for memory interleave reduction - Google Patents
Method and apparatus for memory interleave reductionInfo
- Publication number
- AU5294193A AU5294193A AU52941/93A AU5294193A AU5294193A AU 5294193 A AU5294193 A AU 5294193A AU 52941/93 A AU52941/93 A AU 52941/93A AU 5294193 A AU5294193 A AU 5294193A AU 5294193 A AU5294193 A AU 5294193A
- Authority
- AU
- Australia
- Prior art keywords
- reduction
- memory interleave
- interleave
- memory
- interleave reduction
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
- G06F13/1647—Handling requests for interconnection or transfer for access to memory bus based on arbitration with interleaved bank access
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/06—Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication
- G06F12/0607—Interleaved addressing
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Multi Processors (AREA)
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US95527692A | 1992-10-01 | 1992-10-01 | |
US955276 | 1992-10-01 | ||
PCT/US1993/009275 WO1994008295A1 (en) | 1992-10-01 | 1993-09-29 | Method and apparatus for memory interleave reduction |
Publications (1)
Publication Number | Publication Date |
---|---|
AU5294193A true AU5294193A (en) | 1994-04-26 |
Family
ID=25496599
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
AU52941/93A Abandoned AU5294193A (en) | 1992-10-01 | 1993-09-29 | Method and apparatus for memory interleave reduction |
Country Status (2)
Country | Link |
---|---|
AU (1) | AU5294193A (en) |
WO (1) | WO1994008295A1 (en) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2000315173A (en) * | 1999-04-30 | 2000-11-14 | Matsushita Electric Ind Co Ltd | Memory control device |
KR102464801B1 (en) | 2015-04-14 | 2022-11-07 | 삼성전자주식회사 | Method for operating semiconductor device and semiconductor system |
Family Cites Families (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO1982003931A1 (en) * | 1981-04-27 | 1982-11-11 | Kris Bryan | Multi-master processor bus |
US4783736A (en) * | 1985-07-22 | 1988-11-08 | Alliant Computer Systems Corporation | Digital computer with multisection cache |
US4875206A (en) * | 1988-03-31 | 1989-10-17 | American Telephone And Telegraph Comopany, At&T Bell Laboratories | High bandwidth interleaved buffer memory and control |
US5136717A (en) * | 1988-11-23 | 1992-08-04 | Flavors Technology Inc. | Realtime systolic, multiple-instruction, single-data parallel computer system |
-
1993
- 1993-09-29 WO PCT/US1993/009275 patent/WO1994008295A1/en active Application Filing
- 1993-09-29 AU AU52941/93A patent/AU5294193A/en not_active Abandoned
Also Published As
Publication number | Publication date |
---|---|
WO1994008295A1 (en) | 1994-04-14 |
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