AU470948B2 - Circuit arrangement for increasing the signal noise ratio in receivers of code multiplex transmission installations - Google Patents
Circuit arrangement for increasing the signal noise ratio in receivers of code multiplex transmission installationsInfo
- Publication number
- AU470948B2 AU470948B2 AU55153/73A AU5515373A AU470948B2 AU 470948 B2 AU470948 B2 AU 470948B2 AU 55153/73 A AU55153/73 A AU 55153/73A AU 5515373 A AU5515373 A AU 5515373A AU 470948 B2 AU470948 B2 AU 470948B2
- Authority
- AU
- Australia
- Prior art keywords
- receivers
- increasing
- noise ratio
- circuit arrangement
- signal noise
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
- H04B1/69—Spread spectrum techniques
- H04B1/707—Spread spectrum techniques using direct sequence modulation
- H04B1/7097—Interference-related aspects
- H04B1/7103—Interference-related aspects the interference being multiple access interference
- H04B1/7107—Subtractive interference cancellation
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B7/00—Radio transmission systems, i.e. using radiation field
- H04B7/14—Relay systems
- H04B7/15—Active relay systems
- H04B7/204—Multiple access
- H04B7/216—Code division or spread-spectrum multiple access [CDMA, SSMA]
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Noise Elimination (AREA)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DEDE82221 | 1972-04-29 | ||
DE19722221524 DE2221524C3 (en) | 1972-05-03 | 1972-05-03 | Circuit arrangement for extending the signal-to-noise ratio at the receiving end in communication systems |
Publications (2)
Publication Number | Publication Date |
---|---|
AU5515373A AU5515373A (en) | 1974-11-07 |
AU470948B2 true AU470948B2 (en) | 1976-04-01 |
Family
ID=5843882
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
AU55153/73A Expired AU470948B2 (en) | 1972-05-03 | 1973-05-02 | Circuit arrangement for increasing the signal noise ratio in receivers of code multiplex transmission installations |
Country Status (2)
Country | Link |
---|---|
AU (1) | AU470948B2 (en) |
DE (1) | DE2221524C3 (en) |
Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6035856B2 (en) * | 1978-10-28 | 1985-08-16 | ヤマハ株式会社 | Receiving machine |
DE2906969C2 (en) * | 1979-02-22 | 1982-09-30 | Siemens AG, 1000 Berlin und 8000 München | Circuit arrangement for clock recovery in regenerators for digital signals |
US4495475A (en) * | 1982-01-08 | 1985-01-22 | Litton Systems, Inc. | Residual mode phase locked loop |
US4408350A (en) * | 1982-02-19 | 1983-10-04 | Erwin Donath | Enhanced selectivity signal receiver |
-
1972
- 1972-05-03 DE DE19722221524 patent/DE2221524C3/en not_active Expired
-
1973
- 1973-05-02 AU AU55153/73A patent/AU470948B2/en not_active Expired
Also Published As
Publication number | Publication date |
---|---|
AU5515373A (en) | 1974-11-07 |
DE2221524A1 (en) | 1973-11-15 |
DE2221524B2 (en) | 1979-01-11 |
DE2221524C3 (en) | 1979-09-06 |
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