AU464581B2 - Random access memory system utilizing an inverting cell concept - Google Patents

Random access memory system utilizing an inverting cell concept

Info

Publication number
AU464581B2
AU464581B2 AU49689/72A AU4968972A AU464581B2 AU 464581 B2 AU464581 B2 AU 464581B2 AU 49689/72 A AU49689/72 A AU 49689/72A AU 4968972 A AU4968972 A AU 4968972A AU 464581 B2 AU464581 B2 AU 464581B2
Authority
AU
Australia
Prior art keywords
random access
access memory
memory system
system utilizing
cell concept
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
AU49689/72A
Other languages
English (en)
Other versions
AU4968972A (en
Inventor
F. CROXTON and LAURENCE F. ABBOTT BRIAN
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Bull HN Information Systems Inc
Original Assignee
Honeywell Information Systems Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Honeywell Information Systems Inc filed Critical Honeywell Information Systems Inc
Publication of AU4968972A publication Critical patent/AU4968972A/en
Application granted granted Critical
Publication of AU464581B2 publication Critical patent/AU464581B2/en
Expired legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C11/00Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/4078Safety or protection circuits, e.g. for preventing inadvertent or unauthorised reading or writing; Status cells; Test cells
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C11/00Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/403Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh
    • G11C11/405Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh with three charge-transfer gates, e.g. MOS transistors, per cell
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C11/00Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406Management or control of the refreshing or charge-regeneration cycles

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Computer Security & Cryptography (AREA)
  • Dram (AREA)
  • Read Only Memory (AREA)
AU49689/72A 1972-01-03 1972-12-06 Random access memory system utilizing an inverting cell concept Expired AU464581B2 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US21597672A 1972-01-03 1972-01-03
USUS215,976 1972-01-03

Publications (2)

Publication Number Publication Date
AU4968972A AU4968972A (en) 1974-06-06
AU464581B2 true AU464581B2 (en) 1975-08-28

Family

ID=22805155

Family Applications (1)

Application Number Title Priority Date Filing Date
AU49689/72A Expired AU464581B2 (en) 1972-01-03 1972-12-06 Random access memory system utilizing an inverting cell concept

Country Status (9)

Country Link
US (1) US3786437A (US07902200-20110308-C00004.png)
JP (1) JPS5733631B2 (US07902200-20110308-C00004.png)
AU (1) AU464581B2 (US07902200-20110308-C00004.png)
CA (1) CA996260A (US07902200-20110308-C00004.png)
DE (1) DE2300165C2 (US07902200-20110308-C00004.png)
FR (1) FR2167600B1 (US07902200-20110308-C00004.png)
GB (1) GB1406117A (US07902200-20110308-C00004.png)
IT (1) IT971424B (US07902200-20110308-C00004.png)
NL (1) NL182354C (US07902200-20110308-C00004.png)

Families Citing this family (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2247835C3 (de) * 1972-09-29 1978-10-05 Siemens Ag, 1000 Berlin Und 8000 Muenchen Verfahren zum Regenerieren der Speicherinhalte von MOS-Speichern und MOS-Speicher zur Durchführung dieses Verfahrens
US3858185A (en) * 1973-07-18 1974-12-31 Intel Corp An mos dynamic memory array & refreshing system
US3934233A (en) * 1973-09-24 1976-01-20 Texas Instruments Incorporated Read-only-memory for electronic calculator
US3895360A (en) * 1974-01-29 1975-07-15 Westinghouse Electric Corp Block oriented random access memory
US4041330A (en) * 1974-04-01 1977-08-09 Rockwell International Corporation Selectable eight or twelve digit integrated circuit calculator and conditional gate output signal modification circuit therefor
US3942160A (en) * 1974-06-03 1976-03-02 Motorola, Inc. Bit sense line speed-up circuit for MOS RAM
US3942162A (en) * 1974-07-01 1976-03-02 Motorola, Inc. Pre-conditioning circuits for MOS integrated circuits
US3976892A (en) * 1974-07-01 1976-08-24 Motorola, Inc. Pre-conditioning circuits for MOS integrated circuits
JPS526044A (en) * 1975-07-04 1977-01-18 Toko Inc Dynamic decoder circuit
IT1041882B (it) * 1975-08-20 1980-01-10 Honeywell Inf Systems Memoria dinamica a semiconduttori e relativo sistema di recarica
JPS52106640A (en) * 1976-03-05 1977-09-07 Hitachi Ltd Memory peripheral circuit
US4044330A (en) * 1976-03-30 1977-08-23 Honeywell Information Systems, Inc. Power strobing to achieve a tri state
US4060794A (en) * 1976-03-31 1977-11-29 Honeywell Information Systems Inc. Apparatus and method for generating timing signals for latched type memories
JPS5645120Y2 (US07902200-20110308-C00004.png) * 1976-08-19 1981-10-21
JPS5725440Y2 (US07902200-20110308-C00004.png) * 1976-08-31 1982-06-02
JPS55150189A (en) * 1979-05-10 1980-11-21 Nec Corp Memory circuit
GB2346462B (en) 1999-02-05 2003-11-26 Gec Marconi Comm Ltd Memories
WO2000051133A1 (de) * 1999-02-22 2000-08-31 Infineon Technologies Ag Verfahren zum betrieb einer speicherzellenanordnung mit selbstverstärkenden dynamischen speicherzellen
US6580650B2 (en) 2001-03-16 2003-06-17 International Business Machines Corporation DRAM word line voltage control to insure full cell writeback level
US7916544B2 (en) 2008-01-25 2011-03-29 Micron Technology, Inc. Random telegraph signal noise reduction scheme for semiconductor memories

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB1106689A (en) * 1964-11-16 1968-03-20 Standard Telephones Cables Ltd Data processing equipment
GB1296067A (US07902200-20110308-C00004.png) * 1969-03-21 1972-11-15
US3684897A (en) * 1970-08-19 1972-08-15 Cogar Corp Dynamic mos memory array timing system
US3681764A (en) * 1971-03-15 1972-08-01 Litton Systems Inc Low power memory system

Also Published As

Publication number Publication date
JPS4879941A (US07902200-20110308-C00004.png) 1973-10-26
IT971424B (it) 1974-04-30
FR2167600B1 (US07902200-20110308-C00004.png) 1977-07-29
FR2167600A1 (US07902200-20110308-C00004.png) 1973-08-24
DE2300165C2 (de) 1983-02-24
DE2300165A1 (de) 1973-07-19
JPS5733631B2 (US07902200-20110308-C00004.png) 1982-07-17
NL7217648A (US07902200-20110308-C00004.png) 1973-07-05
GB1406117A (en) 1975-09-17
AU4968972A (en) 1974-06-06
US3786437A (en) 1974-01-15
NL182354C (nl) 1988-02-16
NL182354B (nl) 1987-09-16
CA996260A (en) 1976-08-31

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