AU463566B2 - A frame synchronization system - Google Patents

Description

28,561 p,

This invention relates to time division multiplex (TD d)binary data communication systems and more particularly to a frame sybchronization system therefor. There are certain TDM communication systems which employ a long and complex binary data format comprising a multiframe including N frames with each

of the frames including M channels, with at least one of these channel signals in each of the frames including

a different one of N subchannel signals. Such a format is found in communication systems wherein the

subchannel signals are control signals used in the receiver to control the demultiplexing of the frame

signals in the multiframe format. Another type of communication system in which such a complex format

would be employed is a system for handling multiple rate data wherein the higher speed data is transmitted

as the channel signals of the frames and lower speed

data is transmitted as the subchannels of the frames

of a multiframe. It had been the practice in the past where

the multiframe format is present in a communication

system, particularly those employed with the dual rate

data, to employ a single synchronization signal to

achieve desired frame synchronization. The timing

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speed data channels signals for the rapid and slower a master clock signal are synchronized by synchronlizing digital frequency to the bit rate and then employing therewith to generate dividers and decoders associated demultiplexing the the necessary timing signals for complex TDM format. to provide a An object of this invention is long and complex frame synchronization system for therein two frame binary data formats which includes of one. synchronizationl codes instead there is According to the present invention system for a time provided a frzme synchronization signal having a division multiplex binary data each of said N frames multifrale including N frames, a first sync signal, including M channel signals and signals including in each at least one of said channel of subchannfel sigraJs of said N frames a different one IMand N equal integers and a second sync signal, where greater th~an one, comprisinig: a first source of said data signal; signals including first mieans to produce timing said first sync a first predetrminled timing signal for timing signal for signal and a second predetermined said second sync signal; source second means coupled to said first

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and said first means responsive to saia data signal. and said first and second predetermined timing signals to produce a first control signal indicative of the phase relationship between said first predetermined timing signal and said first sync signal and a second control signal indicative of the phase relationship between said second predetermined timing signal and said second sync signal; and third means coupled to said second means and said first means responsive to said first and second control signals to control the phase of said timing signals with respect to said data signal to establish and.maintain synchronization. Embodiments of the invention will now be described with reference to the accompanying drawings, in which: Figs. 1A-lC are diagrams useful in explaining the format of the data signals upon which the frame synchronization system of the present invention operates; Fig. 2 is a block diagram of one embodiment of the frame synchronization system in accordance with the principles of this invention; Fig. 3 is a block diagram of another embodiment of the frame synchronization system in accordance with -4- 4635,66

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the principles of the present invention; Fig. 4 is a block diagram of one form of and the single decision circuit employed in Fig. 3; one Fig. 5 is a block diagram illustrating Pig. 2; form of the dual decision circuit employed in Fig. 6 is a block diagram illustrating one employed form of sync signal detector which may be for detector 7' of Figs. 2 and 3. Figs. lA-lB illustrate long and complex digital data formats employing two frame synchronization of codes upon which the frame synchronization system a typical this invention operates. As mentioned above, situation employing such a format is a digital demultiplexer where received data is demultiplexed channels or separated into channels, and one or more are subdemultiplexed into subchannels. The data is as typically arranged by frames within multiframes shown in Fig. 1A. The first sync code 1 is repeated sync once per frame as illustrated in Fig. lB. This code and the associated framing circuit will enable the demultiplexer to locate each channel within the as frame, but will not allow one frame to be recognized distinct from another frame. Assume that there. is a channel special control channel, such as channel M or Then a SC in 2ig. 1B, which is submultiplexed.

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typical submultiplexing format is shown in Fig. 1C

which shows only the SO channels within one multiframe.

A second sync code within this submultiplexed channel

format and an associated framing circuit will allow

the demultiplexer to locate each subchannel within

the multiframe. The second framing circuit can be

synchronized more quickly by sampling only the SC

bits, because the bits of the second sync code are SC

bits. The second framing circuit cannot be synchronized,

however, until the first framing circuit is synchronized,

thus correctly locating the SC bits. The formats shown in Figs. 1A, 1B, and 1C are only typical samples. The only real assumption made here is that there is a

first sync code repeated once every iHdLat bit, which is called a frame herein, and a second sync code

repeated once every N frames 4(ij ait), which is called a multiframe herein.

For purposes of explanation only, it will

be assumed that sync code 1 is a pattern continually repeated in the N frames of the multiframe.

Synchronization to this code synchronizes the frame

channels and locates odd and even bits of the SC channel

which may include control channels and sync code 2.

It is assumed -hat sync code 2 is a 00001111 word

continually repeated every multiframe.

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Referring to Fig-. 2, there is illustrated thereiA in block diagram form one embodiment of the frame synchronization system in accordance .with the principles of this invention.' Clock 3 provides a clock signal CLK. at the bit rate of the multiframe with this clock signal being synchronous vith the received data signal from source 4. This synchronization

between clock signal CLK 1 and the received data can be obtained by any well known bit synchronization arrangement such as, for instance, a phase locked loop type circuit. The output from source 3

triggers a divide by MA counter in digital counter and timing signal decoder-generator 5 except when inhibited by halt signal Hi applied to AINID gate 6 through NOT gate 10. Counter-generator 5 generate frame timing signals, including a frame rate clock CLK 2, which locates the SC bits of each frame. Other timing signals generated are similar to those disclosed in our Australian Applications Noe. 64650 and 64651, both filed December 3rd. 1969, and identified

therein as sync time signal ST, halt time signal HT, triggering signal SHC and tri~lGeriflg signal MT. The IAT signal is produced by A!!D gating the bit rate clock CLK 1 with the sync time signal ST. The SHOC

signal is produced by OR gating the halt signal HI 7 4635.66

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with the sync time signal ST end AIID gating the output

of the OR gate with the bit rate clock signal CLK in Application No. 64651. On the other hand the SHC signal in Application No. 64650 is produced by OR

gating the ST signal with shift register timing

signal SH and AND gating the output of the OR with

the bit rate clock signal CLK1.

Counter-generator 5 also produces as one of its timing signals a reference signal REP 1 for the first sync code contained in the data from source

4. As disclosed in the above mentioned applications

the signal REF1 is a square wave having a repetition

frequency equal to one-half the frame repetition frequency when employing as the first sync code the

pattern in adjacent frames.

Sync code 1 detector 7 compares the data signal and REF signal and generates a signal TOi which indicates mismatches between the data signal

and the references signal REFl. A mismatch is a binary and a match produces a binary With the first sync code and RJF1 signal as assumed above, detector 7 could be in the form of an EXCLUSIVE OR

gate. The output signal 1lIFl from detector 7 is coupled to sampling logic 8 which may be in the form

of two flip flops, such as flip flops 8 and 19 of

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Application No. 64651 or flip flops 8 and BN of the Application No. 64650. Logic 8 samples the mismatch signal WMl at regular intervals a4"lis applied to dual decision circuit 9. The halt signal HI is produced haviug a high value only when halt timing signal HTI, mismatch sample signal ISl, search level signal SL

and search mode signal SMi all have a high value to enable AITD gate 11. Typically, signal MS1 is identical to Mi. However, when either of the techniques described in the above mentioned applications are used, signal includes samples in addition to those of signal 1Sl Mi.

The SL signal indicates when the rate of mismatches has exceeded a certain level, thus permitting searching, that is, halting of the counters of counter-generator to adjust their phase. With the dual decision circuit 9 being used, signal SMl is also generated, indicating when the decision circuit is in a state called "search mode" which also permits searching. It should be noted that the left and right sides of Fig. 2 are similar. Each has a framing circuit, that just described being for frame timing.

Digital counter and timing signal decoder-generator

includes a divideby N counter to count the frame

rate clock signal CLK 2 except when inhibited by the

operation of AAD gate 6' in the presence of a halt 4635,66

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signal H2. The circuitry.in counter-generator

produces multiframe timing signals and the circuitry

associated thererith synchronizes the multiframe timing

in a manner similar to the frame timing just described.

The timing signals HT2, SHC2 and MT2 are produced as

described above with reference to counter-generator

but with the clock pulse in this situation being clock

CLK2. Generator 5' in addition to the above timing signals also produces two timing signals to control

the operation of sync code 2 detector These two

timing signals are the odd bit timing signal OBT and

the even bit timing signal EBT. These two timing

signals are produced by AND gating reference signal

REF1, the bit rate clock CLK1 and the bit timing

signal for the SC channels. Detector 7' is more

complex than detector 7 due to the type of sync code

employed for the second sync signal. One embodiment

for this detector is disclosed in Fig. 6 described

below.

Detector 7' includes, due to its internal

wiring, circuitry that will detect the entire code,

allowing up to some number of bit mismatches per code,

according to the 'detector threshold. Detector 7' is

coupled to source 4 and produces a mismatch output

signal i.E1F'2 which is coupled to sampling circuit 8' 10 4635,6(

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having the same arrangement for producing signals

MS2 and IM2as described with reference to sampling

logic 8. The output from sampling logic 8' is

coupled to dual decision circuit 9' producing the SM2 search level signal SL2 and search mode signal

for application to AND gate 11' whose output is coupled

to NOT gate Detectors 7 and as is apparent from Detector above, are two different types of circuits, signal that 7 compares the input data with a reference describes the sync code, that is, the sequence of

bit values. However, with detector 7' the description

of the sync code is built into the sync code detector,

and no reference signal is required. Detector 7

indicates a match for each bit of the code, but detector up 7' indicates a match for the entire code, allowing to to some number of bit mismatches per code according

the detector threshold. For detector 7, the phase of

the reference signal is corrected by the searching

action. For detector however, there is no external

reference signal and the timing signals used in the

example (EBT and OBT) are not changed by the framing

circuit coupled to oenerator 5' but are synchronized Timing by the framing circuit coupled to generator 5. channels, signals E3T end OBT specify the timing of the SC 11 4635,66

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of which sync code 2 is only a part.

The description of the two detectors 7 and

7' detecting sync code 1 and sync code 2, respectively,

are only by way of example. It should be understood

that the techniques of this invention are equally

applicable to use of any type of code for sync codes 1

and 2, and to use of either type of detector for sync

codes 1 and 2, these choices being determined primarily

by system requirements.

Fig. 3 is identical to Fig. 2 in all respects and operates exactly like Fig. 2 with the exception

that the La output signals from sampling logics 8 and

8' are coupled to "single" decision circuits 12 and 12'.

In addition, timing signal MT is not coupled to

decision circuits 12 and 12' and there is no search

mode output SM from decision circuits 12 and 12'.

Rather, the SL2 output of circuit 12' is coupled to

AND gate 11 as well as AND gate 11'.

It should be noted that in the description

of Figs. 2 and 3 AND gates 11 and NOT gates 10 have been described as separate units. It will be obvious that the AHD and NOT gates perform the same function

as a NAND gate and, thus, a iiAiTD gate could be

substituted for these two gate elements.

From a statistical point of view, the 12 4635,66

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MM1 average rate of mismatches per sample for signals

or i2 has an expected value higher than some rate

referred to herein as the "threshold probability" the when the counters are not synchronized, and than average mismatch rate .s expected to be less are this "threshold probability" when the counters The decision circuits 9, 12 and synchronized. judge 12' of Pigs. 2 and 3 use the above principles to

whether or not the associated counters are synchronized; present frame or, in other words, whether or not the phase is correct.

Fig. 4 shows a single decision circuit, may be which is an integrator or betting circuit, that 3 which employed for circuits 12 and 12' of Fig. This accomplished the above-mentioned function. the circuit is called a "betting" circuit because point of operation of the circuit from a statistical view is exactly analogous to a type of.betting

situation. Amplifiers 13 and 14 are high gain

differential amplifiers. Amplifier 13, capacitor C1 integrator and resistor Rl together form a Miller type

with a time constant equal to R 1 01. Vhen signal

MM4 is a indicating a mismatch, the voltage When signal fM is E 1 goes down at a certain rate. for a match, voltage E 1 goes up at another rate.

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The fixed bias voltage V 1 determines the ratio

of the up and down rates, and thereby also determines

the threshold probability of the circuit. When the

mismatch rate exceeds the threshold probability,

voltage E 1 goes down more than up; and when the

mismatch rate is less than the threshold probability,

the voltage E1 goes up more than down.

The above statements, however, ignore

limitations on the voltage E 1 No amplifier can

either increase or decrease its output voltage without

limit. At some point, the voltage can change no further.

Thus voltage E 1 is limited to some range by the

amplifier itself. The value of the lower limit is

important to the relationship of the integrator to

amplifier 14, and if the lower limit due to amplifier

13 is not stable with regard to circuit tolerances,

a more stable limit may be defined by providing clamp

circuit 15 as illustrated. Clamp circuit 15 provides

negative feedback when the limiting voltage is reached.

Amplifier 14 is used as a voltage comparator.

Its output SL is high (logical when voltage E 1 is lower than the bias voltage V2 and output SL is

low (logical when voltage E 1 is higher than bias voltage V 2 Bias voltage V 2 is a fixed voltage

between the upper and lower limits of voltage E 1 14 463 566

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but closer to the lower limit. The framing circuit works in two modes. In the sense mode, it is assumed that the phase of the counters has been corrected, and the betting circuit must detect whether the frame phase is now incorrect (loss of synchronization). In the search mode, it

is assumed that the frame phase has been incorrect. Adjustment of the phase is made, and the betting circuit must decide whether the frame phase is now correct. Both modes must be considered in the design of the betting circuit. For the sense mode, it is often required that the response of the betting circuit must be slow. This guards against signal fading, such as encountered in tropospheric scatter radio communications. Fading of the received signal commonly causes the mismatch rate to exceed the threshold probability. This causes the betting circuit to decide that the frame phase is incorrect, when indeed it is correct. This allows the framing logic to search, that is, adjust the phase, and the first adjustment will make the phase incorrect. If, .however, the response of the betting circuit is slow compared to the duration of a fade, the fade will.cease before an erroneous decision can be made. For the search mode, it is typically 4635.66 required that the response of the betting circuit must be fast. This is an importance factor in reducing the average search time (time to acquire synchronization), since the betting circuit makes many decisions during a search.

The conflicting (but not contradicting) requirements that the response of the betting circuit

must be slow for the sense mode and fast for the

search mode means that it must take a long time for

voltage E 1 to decrease from its upper limit to

voltage V 2 and a short time for voltage E 1 to increase

from its lower limit to voltage V 2 To satisfy both requirements, voltage V 2 must be much closer to the

lower limit voltage than the upper limit voltage, and

voltage V 1 must be set as high as possible, making the

threshold probability as close as possible to the lowest

mismatch rate expected for an incorrect phase. However, consideration of component variations and power supply

voltage that might cause the voltages V 1 V 2 or the clamp voltage to change with time or temperature place a limit

on how accurately V 1 and V 2 may be set without making a

functional failure probable. The result is that in some

cases a simple betting circuit cannot satisfy both of

the stated requirements.

Fig. 5 illustrates a dual decision circuit which is a dual integratorcr betting circuit, avoiding the above -16 4635.66

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problem. The input W1 operates two integrator circuits. The integrator composed of high gain differential amplifier 16, resistor R2and capacitor C2 is in the sense circuit 17 and the integrator composed of high gain differential amplifier 18, resistorR and capacitor C3 is in the search circuit 19. -The time

constant R2 C2 is made large to increase the sense mode response', and the time constant R3 03 is made small to decrease the search mode-response.* High gain differential amplifier 20 provides a voltage comparator for sense circuit 17 and high gain differe ntial amplifier 21 provides a voltage comparator for search circuit 19. Amplifiers 20 and 21 are arranged as shown to set and reset mode flip flop 22 as follows. When synchronisation is lost, the average mismatch rate exceeds -ihe threshold probability set by bias voltage V3 Pvoltage E2 goes down more than up, and eventually voltag;e E2 becomes less than bias voltage VV causing voltage E3to become high and- setting mode flip flop 22 to provide a 1"1 at the 1"1

output thereof. The output signal SM is equal to 1"1, -representing the search mode, and enables searching to begin. Since search circuit 19 has a smaller time constant, voltage E4 will go dovmn faster and sooner than E2and the SL output from high gain differential amplifier 23 will become 1111, before 17 4635.66

28,56117

signal SM becomes Since both output signals SL and SM are required to enable searching (note AND gates 11 and 11' of Fig. 2) the slower circuit, namely, sense circuit 17, determines the sense time) or the time for response to a loss of synchronization. Duaring the. search for the correct phase, search circuit 19 and the voltage comparator provided by differential amplifier 23 operate in a manner similar to the simple betting circuit of Fig. 4. Wlhen the frame phase is correct, the average misrmatch rate is less than the threshold probability set by bias voltage V5E4goes up more than down, and eventually E4 becomes higher than voltage V 6 1 causing voltage E5 to become high and to reset mode flip flop 22 to 110", which represents the sense mode. Since the sense circuit is slovier, voltage E2 cannot go up as fast as voltage .EV and there is a possibility that soon after acquiring synchronization, when voltage E2 is low and not yet up to the upper' limit voltage, that a short fade can make the framing circuit lose synchronization, because voltage E2 being low' will make the response time of the senase circuit 17 shorter than normal. To avoid this problem, the output of flip flop 22 is coupled back to the negative or inverting input of amplifier 16.through diode 24. -18 4635.66

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During sense mode, the 101" output of flip flop 22 is high, reverse biasing diode 24, and having no effect on sense circuit 17. During search mode, when sense circuit 17 is not being used, the "101 output of flip flop 22 is low, forward biasing diode 24, and drawing current from the inverting input of amplifier 16. The low source impedance of this signal enables voltage E2 to be rapidly set to its upper limit voltage. By clocking flip flop 22 with the frame timing signal MT, flip flop 22 will change state synchronously with the counters. However, the timing signal MT is necessary only if the type of flip flop used requires a clock pulse. It has been found that two simple betting circuits can be used in a frame synchronization system as illustrated in Fig. 3, instead of two dual betting circuit as shown in Fig. 2, and yet retain the advantage of the dual betting circuit, provided the two framing circuits are interlocked as shown in Fig. 3 by coupling the SL2 output of circuit 12' to AND gate 11 as well as gate 111. This results in a saving of six differential amplifiers, two flip flops and otlher asscciated components. Betting circuit 12' receives samples at a slower rate than betting circuit 12, because 19 4635.66

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clock CLK 2 is slower and the sync code is distributed

over a longer period of time (a multiframe)'. Thus,

it is easier for betting circuit 12' to have a long

sense time, that is, a slow response in the sense

mode. The first framing circuit can be protected by this same slow response by connecting signals SL2 as well as SLI to AND gate 11. Thus when the mismatch

rates are higher than threshold, the first framing circuit will not halt even when betting circuit 12 responds quickly and SLI soon becomes Halting begins only after SL2 becomes

With regard to Figs. 2 and 3 detector 7

has been indicated to be merely an EXCLUSIVE OR gate.

The reference signal REF1 is a timing signal which has the same binary value as the first sync signal when the phase of counter-generator 5 is correct. The

EXCLUSIVE OR gate compares all multiframe data bits

with this reference value. Detector 7' required to

detect the second sync code, which has been assumed to be eight bits long with a predetermined sequence of

binary and binary 1 0"1 1 s, is more complicated.

This detector is illustrated in detail in Fig. 6.

The data from source 4 is coupled to delay flip flop

which might also be called a one bit shift

register. Flip flop 25 in addition to the first

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flip flop of shift register 26 sample the data signal.

The timing signal OBT coinciding with the odd SC bits

and timing signal and EBT coinciding with the even SO

bits are produced in counter-generator 5' as described

above. Delay flip flop 25 samples only the odd SC

bits because it receives the odd timing "signal. Its

output is transferred to the four bit shift register

26 by the even timing signal. As a result the odd

SC bits passing through delay flip flop 25 encounters

a delay of one SC bit period and are brought into step

with the even SC bits. The odd SC bits are shifted down

shift register 26 and the even bits are shifted down

the four bit shift register 27. The shifting rate is

one shift per two SC bits. Thus, all of the SC bits

pass through the two shift registers, which serve to

hold the data for inspection.

When the eight bit synchronization code word

fully occupies the two shift registers, and there are

no bits in error (due to noise), the detector indicates

a match. To accomplish this, there is one flip flop

in shift registers 26 and 27 associated with each bit

of sync code 2. If the sync bit is the "1"

output of the associated flip flop of the shift registers

is wired to summing circuit 28. For-a sync bit,

the output of the associated flip flop of the shift -21 463566

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registers is wired to summing circuit 28 to get a "1"

level when the code bit resets the associated

flip.flop. This is the wiring that describes the

sync code internal to the sync code detector. Summing

circuit 28 receives eight when the shift registers

hold the exact sync word. If n bits are in error due

to noise, or because the bits are not part of the

second sync code, or because the sync bits are not

in their proper positions in the shift registers,

summing circuit 28 will receive n and (8-n)

Summing circuit 28 generates a voltage

proportional to the number of "zeroes" or bit errors.

It may also be inverting. Bias source 29 generates

a voltage which, by the same proportional scale, is

equivalent to (y 0.5) bit errors, where y is the

code mismatch threshold. Voltage comparator

indicates a code mismatch when the number of bit

errors exceeds (y

VWhile I have described above the principles

of my invention in connection with specific apparatus,

it is to be clearly understood that this description is

cade ony by way of example.

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Claims (2)

28,561/71 The claims defining the invention are as follows:-

1. A frame synchronization system for a time

division multiplex binary data signal aaving multi-

frames each of which includes IIframes, in which each of

the N frames of a said multi frame includes id channel

signals and a first sync sig-ial, and in which at least

one of the channel signals in each of the frames includes

a different one of sub-channel signals and a

second sync signal, id and N being integers greater than

unity, wherein:

tiing signal generating lieans is provided which

generates a first predetermined local timing signal for

the first sync signal and a second predetermined local

timing signal for the second sync signal;

there is a first sync signal detector which is responsive

to the first sync signal in a received data signal and the

first local timing signal to provide a first control

signal indicative of the phase relation between said two

signals;

there is a second sync signal detector which is

responsive to the second sync signal in a received data

signal and the second local timing signal to provide a

second control signal indicative of Lhe pna-e relation

between tne seco_-d s.nc signal and tne second local timing

signal;

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Cdl first and second sampling circuits are adapted to sample

first and second control signals respectively, the outputs ol

the first and second sampling circuits being applied respect: to first and second decision circuits whose outputs indicate the average rate of mismatch between the local timing signal and and the received sync signals exceed a threshold level; ar the outputs of the first and second decision circuits the applied to the timing signal generating means to control ther timing of the first and second timing signals generated the to ensure synchronisation between the timing signals and ceived data signal.

2. A system according to claim 1, and wherein said ti signal generating means includes: a source of bit-rate clock signals synchronous with the of the data signal; a first divider and signal generator to provide at least first local timing signal and a frame rate clock; first logic circuitry coupled between said source of bit signals and said first divider and generator and responsive the outputs of said first decision circuit to control the cc of the bit rate signals to said first divider and generator control the phase of said first local timing signal and sai( rate clock; a second divider and timing signal generator to provide least said second local timing signal; and

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second logic circuitry coupled between said first

divider aid generator'and said second divider and generator

and responsive to the output of said second decision

circuit to control the coupling of the frame rate clock to

said second divider and generator to control the phase

of said second local timing signal.

3. A system according to claim 2, wherein:

said first logic circuitry includes a first NAID

gate coupled to said first decision circuit and a first

AND gate coupled to the first NANiD gate and between the

bit-rate source and said first divider and generator; and

said second logic circuitry includes a second ANMD

gate coupled to the second decision circuit and a second

AND gate coupled to said lAiAD gate and between said first

divider and generator and said second divider and generator.

4. A system according to claim 1, 2 or 5, wherein;

said first sync signal includes binary and binary

in alternate ones of said N frames and said first

local timing sig.na iu a square wave wnose repetition

frequency is one half the repetition frequency of said

,i frames; said second sync signal inciudes x consecutive bits

having a predetermined sequence of binary "i's and

being an integer 6 reater than unity;

said second local timin -signal includes a third

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timing signal having a timing signal corresponding to the

odd bits of said x bits and a fourta timin signal corres-

.onding to the even bits of said x bits; said first sync signal detector includes an

,6CLUSIV.E-OR gate to w.ich are aplied the data signal

and the first control signal; and

said second sync signal dtector includes a delay

flip-flop to which are applied the data signal and said

third timing signal, a first x/2 stage shift register

coupled to the delay flip-flop and to which said fourth

timing signal is applied, a second x/2 stage shift regist(

to which tae data signal and the fourth timing signal are

a;plied, a sumning circuit coupled to each.stage of each

of said snift registers, and voltage comparison means

coupled to the output of said suruming circuit to produce

said second control signal.

A system according to claim 1, 2, 3 or 4, wherein said first decision circuit includes a first dual integration circuit which derives from the output of

said first saupling circait third and fourth output

signals which are applied to the timing sigral generating

means to.effect said control of the phase of tie first timing signal, and wherein said second decision- circuit

includes a second dual integration circuit w.ich derives

from tie output of said second sa:,pling circu-it fifth

26 4635,66

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and sixti output signals whici are applied to the timing

signal -eneratiig i.ea:s to effect said control of the phase

of the second timing signal.

6. A system as claimed in claim 1, 2, 3 or 4,

wnerein said first decision circuit is a first

integration circuit which derives from the output of said

first sampling circuit a third output signal waich is

applied to the timing signal generating means to effect

said control of the phase of the first timin signal,

and wherein said second decision circuit is a second

integration circuit which derives from the output of said

second sampling circuit a fourth output signal wnich is

applied to the timing signal jenerating means to

effect said control tne piase of the second timing signal.

7. A frame synchronisation system for a time division multiplex data signal substantially as described

with reference to Figs. 2, 5 and 6, or to Figs. 3, 4 and 6 of the accompanying drawings.

DATED THIS FIRST DAY OF MAY, 1975.

STANDARD TELEPHONES AND CABLES PTY. LIMITED.

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