AU4575500A - Portable integrated circuit device with a reduced format chip card in comparison with standard chip cards and method for the production thereof - Google Patents
Portable integrated circuit device with a reduced format chip card in comparison with standard chip cards and method for the production thereofInfo
- Publication number
- AU4575500A AU4575500A AU45755/00A AU4575500A AU4575500A AU 4575500 A AU4575500 A AU 4575500A AU 45755/00 A AU45755/00 A AU 45755/00A AU 4575500 A AU4575500 A AU 4575500A AU 4575500 A AU4575500 A AU 4575500A
- Authority
- AU
- Australia
- Prior art keywords
- comparison
- production
- integrated circuit
- circuit device
- portable integrated
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
- G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings
- G06K19/06—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
- G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
- G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
- G06K19/077—Constructional details, e.g. mounting of circuits in the carrier
- G06K19/07737—Constructional details, e.g. mounting of circuits in the carrier the record carrier consisting of two or more mechanically separable parts
- G06K19/07739—Constructional details, e.g. mounting of circuits in the carrier the record carrier consisting of two or more mechanically separable parts comprising a first part capable of functioning as a record carrier on its own and a second part being only functional as a form factor changing part, e.g. SIM cards type ID 0001, removably attached to a regular smart card form factor
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
- G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings
- G06K19/06—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
- G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
- G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
- G06K19/077—Constructional details, e.g. mounting of circuits in the carrier
- G06K19/07743—External electrical contacts
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
- H01L2224/48228—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item the bond pad being disposed in a recess of the surface of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Power Engineering (AREA)
- Credit Cards Or The Like (AREA)
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR9906730A FR2794267B1 (fr) | 1999-05-27 | 1999-05-27 | Dispositif portable a circuit integre, de type carte a puce de format reduit par rapport au format standard des cartes a puces et procede de fabrication |
FR99/06730 | 1999-05-27 | ||
PCT/FR2000/001270 WO2000073987A1 (fr) | 1999-05-27 | 2000-05-11 | Dispositif portable a circuit integre, de type carte a puce de format reduit par rapport au format standard des cartes a puces et procede de fabrication |
Publications (1)
Publication Number | Publication Date |
---|---|
AU4575500A true AU4575500A (en) | 2000-12-18 |
Family
ID=9546085
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
AU45755/00A Abandoned AU4575500A (en) | 1999-05-27 | 2000-05-11 | Portable integrated circuit device with a reduced format chip card in comparison with standard chip cards and method for the production thereof |
Country Status (3)
Country | Link |
---|---|
AU (1) | AU4575500A (fr) |
FR (1) | FR2794267B1 (fr) |
WO (1) | WO2000073987A1 (fr) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2003075543A2 (fr) * | 2002-03-04 | 2003-09-12 | Ramkumar Somasundaram | Telephone mobile a cartes sim multiples pouvant emettre/recevoir a la fois plusieurs numeros de pylones de transmission de societes de telephonie mobile |
Family Cites Families (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0262297A (ja) * | 1988-08-29 | 1990-03-02 | Matsushita Electric Ind Co Ltd | 集積回路装置およびそれを用いたicカード |
FR2645680B1 (fr) * | 1989-04-07 | 1994-04-29 | Thomson Microelectronics Sa Sg | Encapsulation de modules electroniques et procede de fabrication |
DE4326816A1 (de) * | 1993-08-10 | 1995-02-16 | Giesecke & Devrient Gmbh | Elektronisches Modul für Karten und Herstellung eines solchen Moduls |
DE19513282B4 (de) * | 1995-04-07 | 2006-09-14 | Giesecke & Devrient Gmbh | Vorrichtung und Verfahren zum Schneiden von Kuststoffen sowie nach dem Verfahren hergestellter Datenträger |
-
1999
- 1999-05-27 FR FR9906730A patent/FR2794267B1/fr not_active Expired - Fee Related
-
2000
- 2000-05-11 AU AU45755/00A patent/AU4575500A/en not_active Abandoned
- 2000-05-11 WO PCT/FR2000/001270 patent/WO2000073987A1/fr active Application Filing
Also Published As
Publication number | Publication date |
---|---|
FR2794267B1 (fr) | 2003-06-20 |
FR2794267A1 (fr) | 2000-12-01 |
WO2000073987A1 (fr) | 2000-12-07 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
MK6 | Application lapsed section 142(2)(f)/reg. 8.3(3) - pct applic. not entering national phase |