AU4318189A - Pipeline structures and methods - Google Patents

Pipeline structures and methods

Info

Publication number
AU4318189A
AU4318189A AU43181/89A AU4318189A AU4318189A AU 4318189 A AU4318189 A AU 4318189A AU 43181/89 A AU43181/89 A AU 43181/89A AU 4318189 A AU4318189 A AU 4318189A AU 4318189 A AU4318189 A AU 4318189A
Authority
AU
Australia
Prior art keywords
methods
pipeline structures
pipeline
structures
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
AU43181/89A
Inventor
Joseph C. Circello
Richar H. Duerden
Roger W. Luce
Ralph H. Olson
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Edgcore Tech Inc
Original Assignee
Edgcore Tech Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Edgcore Tech Inc filed Critical Edgcore Tech Inc
Publication of AU4318189A publication Critical patent/AU4318189A/en
Abandoned legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3818—Decoding for concurrent execution
    • G06F9/382—Pipelined decoding, e.g. using predecoding
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0844—Multiple simultaneous or quasi-simultaneous cache accessing
    • G06F12/0846—Cache with multiple tag or data arrays being simultaneously accessible
    • G06F12/0848—Partitioned cache, e.g. separate instruction and operand caches
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/30032—Movement instructions, e.g. MOVE, SHIFT, ROTATE, SHUFFLE
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/3005—Arrangements for executing specific machine instructions to perform operations for flow control
    • G06F9/30054—Unconditional branch instructions
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30145—Instruction analysis, e.g. decoding, instruction word fields
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30145—Instruction analysis, e.g. decoding, instruction word fields
    • G06F9/3016—Decoding the operand specifier, e.g. specifier format
    • G06F9/30167—Decoding the operand specifier, e.g. specifier format of immediate specifier, e.g. constants
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/3017—Runtime instruction translation, e.g. macros
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/32—Address formation of the next instruction, e.g. by incrementing the instruction counter
    • G06F9/322—Address formation of the next instruction, e.g. by incrementing the instruction counter for non-sequential address
    • G06F9/325—Address formation of the next instruction, e.g. by incrementing the instruction counter for non-sequential address for loops, e.g. loop detection or loop counter
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3802—Instruction prefetching
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3802—Instruction prefetching
    • G06F9/3804—Instruction prefetching for branches, e.g. hedging, branch folding
    • G06F9/3806—Instruction prefetching for branches, e.g. hedging, branch folding using address prediction, e.g. return stack, branch history buffer
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3885—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units
    • G06F9/3889—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units controlled by multiple instructions, e.g. MIMD, decoupled access or execute

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Advance Control (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
AU43181/89A 1988-09-02 1989-08-30 Pipeline structures and methods Abandoned AU4318189A (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US07/241,111 US5101341A (en) 1988-08-25 1988-09-02 Pipelined system for reducing instruction access time by accumulating predecoded instruction bits a FIFO
US241111 1988-09-02

Publications (1)

Publication Number Publication Date
AU4318189A true AU4318189A (en) 1990-04-02

Family

ID=22909294

Family Applications (1)

Application Number Title Priority Date Filing Date
AU43181/89A Abandoned AU4318189A (en) 1988-09-02 1989-08-30 Pipeline structures and methods

Country Status (3)

Country Link
US (1) US5101341A (en)
AU (1) AU4318189A (en)
WO (1) WO1990003001A1 (en)

Families Citing this family (88)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2810068B2 (en) 1988-11-11 1998-10-15 株式会社日立製作所 Processor system, computer system, and instruction processing method
CA2016068C (en) * 1989-05-24 2000-04-04 Robert W. Horst Multiple instruction issue computer architecture
DE69032812T2 (en) * 1989-07-07 1999-04-29 Hitachi, Ltd., Tokio/Tokyo Device and method for parallel processing
DE69030905T2 (en) * 1989-08-28 1998-01-29 Nippon Electric Co Microprocessor with pipeline predecoder unit and main decoder unit
CA2030404A1 (en) * 1989-11-27 1991-05-28 Robert W. Horst Microinstruction sequencer
US5230068A (en) * 1990-02-26 1993-07-20 Nexgen Microsystems Cache memory system for dynamically altering single cache memory line as either branch target entry or pre-fetch instruction queue based upon instruction sequence
US5317718A (en) * 1990-03-27 1994-05-31 Digital Equipment Corporation Data processing system and method with prefetch buffers
DE69130588T2 (en) * 1990-05-29 1999-05-27 National Semiconductor Corp., Santa Clara, Calif. Partially decoded instruction cache and method therefor
US5450555A (en) * 1990-06-29 1995-09-12 Digital Equipment Corporation Register logging in pipelined computer using register log queue of register content changes and base queue of register log queue pointers for respective instructions
US5305446A (en) 1990-09-28 1994-04-19 Texas Instruments Incorporated Processing devices with improved addressing capabilities, systems and methods
DE69231011T2 (en) * 1991-02-08 2000-09-28 Fujitsu Ltd., Kawasaki Cache memory for processing command data and data processor with the same
US5301295A (en) * 1991-05-22 1994-04-05 Analog Devices, Inc. Data processor apparatus and method with selective caching of instructions
US5539911A (en) 1991-07-08 1996-07-23 Seiko Epson Corporation High-performance, superscalar-based computer system with out-of-order instruction execution
US5961629A (en) * 1991-07-08 1999-10-05 Seiko Epson Corporation High performance, superscalar-based computer system with out-of-order instruction execution
US5493687A (en) 1991-07-08 1996-02-20 Seiko Epson Corporation RISC microprocessor architecture implementing multiple typed register sets
JP3182438B2 (en) * 1991-10-28 2001-07-03 株式会社日立製作所 Data processor
DE69326066T2 (en) * 1992-03-25 2000-03-30 Zilog, Inc. FAST COMMAND DECODING IN A PIPELINE PROCESSOR
DE4237417C2 (en) * 1992-03-25 1997-01-30 Hewlett Packard Co Data processing system
US5438668A (en) * 1992-03-31 1995-08-01 Seiko Epson Corporation System and method for extraction, alignment and decoding of CISC instructions into a nano-instruction bucket for execution by a RISC computer
EP0636256B1 (en) * 1992-03-31 1997-06-04 Seiko Epson Corporation Superscalar risc processor instruction scheduling
DE69308548T2 (en) * 1992-05-01 1997-06-12 Seiko Epson Corp DEVICE AND METHOD FOR COMPLETING THE COMMAND IN A SUPER-SCALAR PROCESSOR.
US6240508B1 (en) * 1992-07-06 2001-05-29 Compaq Computer Corporation Decode and execution synchronized pipeline processing using decode generated memory read queue with stop entry to allow execution generated memory read
US6735685B1 (en) * 1992-09-29 2004-05-11 Seiko Epson Corporation System and method for handling load and/or store operations in a superscalar microprocessor
WO1994008287A1 (en) 1992-09-29 1994-04-14 Seiko Epson Corporation System and method for handling load and/or store operations in a superscalar microprocessor
EP1107111A3 (en) * 1992-12-31 2002-02-06 Seiko Epson Corporation System and method for register renaming
US5628021A (en) * 1992-12-31 1997-05-06 Seiko Epson Corporation System and method for assigning tags to control instruction processing in a superscalar processor
US5467473A (en) * 1993-01-08 1995-11-14 International Business Machines Corporation Out of order instruction load and store comparison
US5519847A (en) * 1993-06-30 1996-05-21 Intel Corporation Method of pipelining sequential writes in a flash memory
EP0651324B1 (en) * 1993-10-29 2006-03-22 Advanced Micro Devices, Inc. Speculative instruction queue for variable byte length instructions
DE69427265T2 (en) 1993-10-29 2002-05-02 Advanced Micro Devices, Inc. Superskalarbefehlsdekoder
US5630082A (en) * 1993-10-29 1997-05-13 Advanced Micro Devices, Inc. Apparatus and method for instruction queue scanning
US5689672A (en) * 1993-10-29 1997-11-18 Advanced Micro Devices, Inc. Pre-decoded instruction cache and method therefor particularly suitable for variable byte-length instructions
EP1186995B1 (en) * 1993-11-05 2003-09-03 Intergraph Corporation Instruction memory with associative cross-bar switch
US6360313B1 (en) 1993-11-05 2002-03-19 Intergraph Corporation Instruction cache associative crossbar switch
EP0652510B1 (en) * 1993-11-05 2000-01-26 Intergraph Corporation Software scheduled superscalar computer architecture
US5996062A (en) * 1993-11-24 1999-11-30 Intergraph Corporation Method and apparatus for controlling an instruction pipeline in a data processing system
GB2285154B (en) * 1993-12-24 1998-04-01 Advanced Risc Mach Ltd Branch cache
US5974534A (en) * 1994-02-14 1999-10-26 Hewlett-Packard Company Predecoding and steering mechanism for instructions in a superscalar processor
US5751990A (en) * 1994-04-26 1998-05-12 International Business Machines Corporation Abridged virtual address cache directory
US5592634A (en) * 1994-05-16 1997-01-07 Motorola Inc. Zero-cycle multi-state branch cache prediction data processing system and method thereof
US5623615A (en) * 1994-08-04 1997-04-22 International Business Machines Corporation Circuit and method for reducing prefetch cycles on microprocessors
US5732243A (en) * 1994-10-18 1998-03-24 Cyrix Corporation Branch processing unit with target cache using low/high banking to support split prefetching
US6128720A (en) * 1994-12-29 2000-10-03 International Business Machines Corporation Distributed processing array with component processors performing customized interpretation of instructions
US5940437A (en) * 1995-01-03 1999-08-17 Intel Corporation System and method for reducing the peak load on the processor of a block processing modem
US5532947A (en) * 1995-01-25 1996-07-02 International Business Machines Corporation Combined decoder/adder circuit which provides improved access speed to a cache
US5822558A (en) * 1995-04-12 1998-10-13 Advanced Micro Devices, Inc. Method and apparatus for predecoding variable byte-length instructions within a superscalar microprocessor
US5828895A (en) * 1995-09-20 1998-10-27 International Business Machines Corporation Methods and system for predecoding instructions in a superscalar data processing system
US5748855A (en) * 1995-10-02 1998-05-05 Iinternational Business Machines Corporation Method and system for performance monitoring of misaligned memory accesses in a processing system
US5691920A (en) * 1995-10-02 1997-11-25 International Business Machines Corporation Method and system for performance monitoring of dispatch unit efficiency in a processing system
US5751945A (en) * 1995-10-02 1998-05-12 International Business Machines Corporation Method and system for performance monitoring stalls to identify pipeline bottlenecks and stalls in a processing system
US5752062A (en) * 1995-10-02 1998-05-12 International Business Machines Corporation Method and system for performance monitoring through monitoring an order of processor events during execution in a processing system
US5797019A (en) * 1995-10-02 1998-08-18 International Business Machines Corporation Method and system for performance monitoring time lengths of disabled interrupts in a processing system
US5729726A (en) * 1995-10-02 1998-03-17 International Business Machines Corporation Method and system for performance monitoring efficiency of branch unit operation in a processing system
US5949971A (en) * 1995-10-02 1999-09-07 International Business Machines Corporation Method and system for performance monitoring through identification of frequency and length of time of execution of serialization instructions in a processing system
US5926642A (en) * 1995-10-06 1999-07-20 Advanced Micro Devices, Inc. RISC86 instruction set
US5809273A (en) * 1996-01-26 1998-09-15 Advanced Micro Devices, Inc. Instruction predecode and multiple instruction decode
US5794063A (en) * 1996-01-26 1998-08-11 Advanced Micro Devices, Inc. Instruction decoder including emulation using indirect specifiers
US5819056A (en) * 1995-10-06 1998-10-06 Advanced Micro Devices, Inc. Instruction buffer organization method and system
US5920713A (en) * 1995-10-06 1999-07-06 Advanced Micro Devices, Inc. Instruction decoder including two-way emulation code branching
US6093213A (en) * 1995-10-06 2000-07-25 Advanced Micro Devices, Inc. Flexible implementation of a system management mode (SMM) in a processor
SE509499C2 (en) * 1996-05-03 1999-02-01 Ericsson Telefon Ab L M Method and apparatus for handling conditional jumps in instructional processing in a pipeline architecture
US5805877A (en) * 1996-09-23 1998-09-08 Motorola, Inc. Data processor with branch target address cache and method of operation
JP3681026B2 (en) * 1997-03-27 2005-08-10 株式会社ソニー・コンピュータエンタテインメント Information processing apparatus and method
US5940602A (en) * 1997-06-11 1999-08-17 Advanced Micro Devices, Inc. Method and apparatus for predecoding variable byte length instructions for scanning of a number of RISC operations
US5935238A (en) * 1997-06-19 1999-08-10 Sun Microsystems, Inc. Selection from multiple fetch addresses generated concurrently including predicted and actual target by control-flow instructions in current and previous instruction bundles
US5964869A (en) * 1997-06-19 1999-10-12 Sun Microsystems, Inc. Instruction fetch mechanism with simultaneous prediction of control-flow instructions
US6134649A (en) * 1997-11-17 2000-10-17 Advanced Micro Devices, Inc. Control transfer indication in predecode which identifies control transfer instruction and an alternate feature of an instruction
US6167506A (en) 1997-11-17 2000-12-26 Advanced Micro Devices, Inc. Replacing displacement in control transfer instruction with encoding indicative of target address, including offset and target cache line location
US6151671A (en) * 1998-02-20 2000-11-21 Intel Corporation System and method of maintaining and utilizing multiple return stack buffers
US6061786A (en) * 1998-04-23 2000-05-09 Advanced Micro Devices, Inc. Processor configured to select a next fetch address by partially decoding a byte of a control transfer instruction
JP3798180B2 (en) * 1998-05-21 2006-07-19 テキサス インスツルメンツ インコーポレイテツド Method and system for buffering instructions in a processor
US6636959B1 (en) 1999-10-14 2003-10-21 Advanced Micro Devices, Inc. Predictor miss decoder updating line predictor storing instruction fetch address and alignment information upon instruction decode termination condition
US6647490B2 (en) 1999-10-14 2003-11-11 Advanced Micro Devices, Inc. Training line predictor for branch targets
US6546478B1 (en) 1999-10-14 2003-04-08 Advanced Micro Devices, Inc. Line predictor entry with location pointers and control information for corresponding instructions in a cache line
US7558900B2 (en) * 2004-09-27 2009-07-07 Winbound Electronics Corporation Serial flash semiconductor memory
US7941653B2 (en) * 2008-12-04 2011-05-10 Analog Devices, Inc. Jump instruction having a reference to a pointer for accessing a branch address table
US9378146B2 (en) 2013-08-20 2016-06-28 Apple Inc. Operand cache design
US9459869B2 (en) 2013-08-20 2016-10-04 Apple Inc. Intelligent caching for an operand cache
US9652233B2 (en) 2013-08-20 2017-05-16 Apple Inc. Hint values for use with an operand cache
US9619394B2 (en) 2015-07-21 2017-04-11 Apple Inc. Operand cache flush, eviction, and clean techniques using hint information and dirty information
US9785567B2 (en) 2015-09-11 2017-10-10 Apple Inc. Operand cache control techniques
US10613987B2 (en) 2016-09-23 2020-04-07 Apple Inc. Operand cache coherence for SIMD processor supporting predication
CN107038125B (en) * 2017-04-25 2020-11-24 上海兆芯集成电路有限公司 Processor cache with independent pipeline to speed prefetch requests
CN113779755B (en) * 2021-08-05 2023-11-17 中科联芯(广州)科技有限公司 Design method of silicon-based multispectral integrated circuit chip and integrated circuit chip
US11616596B1 (en) * 2021-09-24 2023-03-28 Apple Inc. Instruction-based multi-thread multi-mode PDSCH decoder for cellular data device
US11775307B2 (en) * 2021-09-24 2023-10-03 Apple Inc. Systems and methods for synchronizing data processing in a cellular modem
US11595154B1 (en) * 2021-09-24 2023-02-28 Apple Inc. Instruction-based multi-thread multi-mode PDCCH decoder for cellular data device
CN114035850A (en) * 2021-12-08 2022-02-11 苏州睿芯集成电路科技有限公司 RISC-V based precoding design method and system for direct jump

Family Cites Families (40)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
BE789583A (en) * 1971-10-01 1973-02-01 Sanders Associates Inc PROGRAM CONTROL APPARATUS FOR DATA PROCESSING MACHINE
FR130806A (en) * 1973-11-21
US3947823A (en) * 1973-12-26 1976-03-30 International Business Machines Corp. Means for coordinating asynchronous main store accesses in a multiprocessing system using virtual storage
US4323964A (en) * 1976-11-01 1982-04-06 Data General Corporation CPU Employing micro programmable control for use in a data processing system
US4200927A (en) * 1978-01-03 1980-04-29 International Business Machines Corporation Multi-instruction stream branch processing mechanism
US4287561A (en) * 1978-03-16 1981-09-01 International Business Machines Corporation Address formulation interlock mechanism
US4527237A (en) * 1979-10-11 1985-07-02 Nanodata Computer Corporation Data processing system
JPS5687282A (en) * 1979-12-14 1981-07-15 Nec Corp Data processor
CA1174370A (en) * 1980-05-19 1984-09-11 Hidekazu Matsumoto Data processing unit with pipelined operands
US4390946A (en) * 1980-10-20 1983-06-28 Control Data Corporation Lookahead addressing in a pipeline computer control store with separate memory segments for single and multiple microcode instruction sequences
US4437149A (en) * 1980-11-17 1984-03-13 International Business Machines Corporation Cache memory architecture with decoding
US4399507A (en) * 1981-06-30 1983-08-16 Ibm Corporation Instruction address stack in the data memory of an instruction-pipelined processor
US4530050A (en) * 1981-08-26 1985-07-16 Hitachi, Ltd. Central processing unit for executing instructions of variable length having end information for operand specifiers
JPS58106636A (en) * 1981-12-18 1983-06-25 Hitachi Ltd Pipeline operating device
JPS58129550A (en) * 1982-01-27 1983-08-02 Toshiba Corp Arithmetic sequence device
US4685080A (en) * 1982-02-22 1987-08-04 International Business Machines Corp. Microword generation mechanism utilizing separate programmable logic arrays for first and second microwords
US4468736A (en) * 1982-06-08 1984-08-28 Burroughs Corporation Mechanism for creating dependency free code for multiple processing elements
JPS592179A (en) * 1982-06-29 1984-01-07 Shindengen Electric Mfg Co Ltd Voting processing device in public stadium
US4519033A (en) * 1982-08-02 1985-05-21 Motorola, Inc. Control state sequencer
JPS59501426A (en) * 1982-08-23 1984-08-09 ウエスタ−ン　エレクトリツク　カムパニ−，インコ−ポレ−テツド Mechanism for calculating the next address in advance
US4604691A (en) * 1982-09-07 1986-08-05 Nippon Electric Co., Ltd. Data processing system having branch instruction prefetching performance
US4613935A (en) * 1983-02-02 1986-09-23 Couleur John F Method and apparatus for pipe line processing with a single arithmetic logic unit
US4594655A (en) * 1983-03-14 1986-06-10 International Business Machines Corporation (k)-Instructions-at-a-time pipelined processor for parallel execution of inherently sequential instructions
JPS59205605A (en) * 1983-05-07 1984-11-21 Hitachi Ltd Sequence controller
EP0150177A1 (en) * 1983-07-11 1985-08-07 Prime Computer, Inc. Data processing system
US4574344A (en) * 1983-09-29 1986-03-04 Tandem Computers Incorporated Entry control store for enhanced CPU pipeline performance
US4812971A (en) * 1983-10-03 1989-03-14 Digital Equipment Corporation Central processing unit for a digital computer
US4764861A (en) * 1984-02-08 1988-08-16 Nec Corporation Instruction fpefetching device with prediction of a branch destination for each branch count instruction
US4742451A (en) * 1984-05-21 1988-05-03 Digital Equipment Corporation Instruction prefetch system for conditional branch instruction for central processor unit
US4620275A (en) * 1984-06-20 1986-10-28 Wallach Steven J Computer system
US4794524A (en) * 1984-07-03 1988-12-27 Zilog, Inc. Pipelined single chip microprocessor having on-chip cache and on-chip memory management unit
US4691277A (en) * 1984-10-24 1987-09-01 International Business Machines Corp. Small instruction cache using branch target table to effect instruction prefetch
US4777587A (en) * 1985-08-30 1988-10-11 Advanced Micro Devices, Inc. System for processing single-cycle branch instruction in a pipeline having relative, absolute, indirect and trap addresses
US4701842A (en) * 1985-10-04 1987-10-20 International Business Machines Corporation Method and apparatus for avoiding excessive delay in a pipelined processor during the execution of a microbranch instruction
US4722049A (en) * 1985-10-11 1988-01-26 Unisys Corporation Apparatus for out-of-order program execution
US4755935A (en) * 1986-01-27 1988-07-05 Schlumberger Technology Corporation Prefetch memory system having next-instruction buffer which stores target tracks of jumps prior to CPU access of instruction
US4722050A (en) * 1986-03-27 1988-01-26 Hewlett-Packard Company Method and apparatus for facilitating instruction processing of a digital computer
US4811208A (en) * 1986-05-16 1989-03-07 Intel Corporation Stack frame cache on a microprocessor chip
US4811215A (en) * 1986-12-12 1989-03-07 Intergraph Corporation Instruction execution accelerator for a pipelined digital machine with virtual memory
US4802085A (en) * 1987-01-22 1989-01-31 National Semiconductor Corporation Apparatus and method for detecting and handling memory-mapped I/O by a pipelined microprocessor

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