AU3991599A - Synchronous reset generation in an asynchronous system - Google Patents

Synchronous reset generation in an asynchronous system

Info

Publication number
AU3991599A
AU3991599A AU39915/99A AU3991599A AU3991599A AU 3991599 A AU3991599 A AU 3991599A AU 39915/99 A AU39915/99 A AU 39915/99A AU 3991599 A AU3991599 A AU 3991599A AU 3991599 A AU3991599 A AU 3991599A
Authority
AU
Australia
Prior art keywords
asynchronous system
synchronous reset
reset generation
generation
synchronous
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
AU39915/99A
Inventor
Peter Michael Murphy
Vijaya Ramadoss
Jeffry Richard Summers
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Technicolor USA Inc
Original Assignee
Thomson Consumer Electronics Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Thomson Consumer Electronics Inc filed Critical Thomson Consumer Electronics Inc
Publication of AU3991599A publication Critical patent/AU3991599A/en
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
    • H03K5/135—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals by the use of time reference signals, e.g. clock signals

Landscapes

  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Electronic Switches (AREA)
AU39915/99A 1998-05-27 1999-05-13 Synchronous reset generation in an asynchronous system Withdrawn AU3991599A (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US8541398A 1998-05-27 1998-05-27
US09085413 1998-05-27
PCT/US1999/010671 WO1999062173A1 (en) 1998-05-27 1999-05-13 Synchronous reset generation in an asynchronous system

Publications (1)

Publication Number Publication Date
AU3991599A true AU3991599A (en) 1999-12-13

Family

ID=22191430

Family Applications (1)

Application Number Title Priority Date Filing Date
AU39915/99A Withdrawn AU3991599A (en) 1998-05-27 1999-05-13 Synchronous reset generation in an asynchronous system

Country Status (2)

Country Link
AU (1) AU3991599A (en)
WO (1) WO1999062173A1 (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7257788B2 (en) 2004-11-08 2007-08-14 International Business Machines Corporation Method and apparatus for converting globally clock-gated circuits to locally clock-gated circuits
US9053271B1 (en) 2014-02-06 2015-06-09 Freescale Semiconductor, Inc. Integrated circuit reset system modification tool

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6211089Y2 (en) * 1978-01-30 1987-03-16
US4644498A (en) * 1983-04-04 1987-02-17 General Electric Company Fault-tolerant real time clock
US5012127A (en) * 1987-09-24 1991-04-30 Ncr Corporation Synchronizer circuit with asynchronous clearing
JPH0793558B2 (en) * 1989-12-15 1995-10-09 安藤電気株式会社 Timing signal delay circuit
US5537655A (en) * 1992-09-28 1996-07-16 The Boeing Company Synchronized fault tolerant reset
KR0165404B1 (en) * 1995-06-17 1999-03-20 이대원 Method & circuit for delaying digital signal

Also Published As

Publication number Publication date
WO1999062173A1 (en) 1999-12-02

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Legal Events

Date Code Title Description
MK13 Application withdrawn section 141(2)/reg 8.3(2) - pct appl. non-entering nat. phase, withdrawn by applicant