AU3664400A - Generic aid method for placing signal processing applications on parallel computers - Google Patents

Generic aid method for placing signal processing applications on parallel computers

Info

Publication number
AU3664400A
AU3664400A AU36644/00A AU3664400A AU3664400A AU 3664400 A AU3664400 A AU 3664400A AU 36644/00 A AU36644/00 A AU 36644/00A AU 3664400 A AU3664400 A AU 3664400A AU 3664400 A AU3664400 A AU 3664400A
Authority
AU
Australia
Prior art keywords
generic
signal processing
processing applications
parallel computers
aid method
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
AU36644/00A
Inventor
Christophe Guettier
Jean Jourdan
Juliette Mattioli
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Thales SA
Original Assignee
Thomson CSF SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Thomson CSF SA filed Critical Thomson CSF SA
Publication of AU3664400A publication Critical patent/AU3664400A/en
Abandoned legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/50—Allocation of resources, e.g. of the central processing unit [CPU]
    • G06F9/5061—Partitioning or combining of resources
    • G06F9/5066—Algorithms for mapping a plurality of inter-dependent sub-tasks onto a plurality of physical CPUs

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Devices For Executing Special Programs (AREA)
AU36644/00A 1999-04-02 2000-03-31 Generic aid method for placing signal processing applications on parallel computers Abandoned AU3664400A (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
FR9904182 1999-04-02
FR9904182A FR2791789B1 (en) 1999-04-02 1999-04-02 GENERIC METHOD FOR ASSISTING PLACEMENT OF SIGNAL PROCESSING APPLICATIONS ON PARALLEL COMPUTERS
PCT/FR2000/000824 WO2000060460A1 (en) 1999-04-02 2000-03-31 Generic aid method for placing signal processing applications on parallel computers

Publications (1)

Publication Number Publication Date
AU3664400A true AU3664400A (en) 2000-10-23

Family

ID=9543985

Family Applications (1)

Application Number Title Priority Date Filing Date
AU36644/00A Abandoned AU3664400A (en) 1999-04-02 2000-03-31 Generic aid method for placing signal processing applications on parallel computers

Country Status (4)

Country Link
EP (1) EP1082656A1 (en)
AU (1) AU3664400A (en)
FR (1) FR2791789B1 (en)
WO (1) WO2000060460A1 (en)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2818406B1 (en) * 2000-12-19 2003-03-07 Thomson Csf METHOD FOR PLACING MULTIPROCESSOR APPLICATIONS
FR2819601B1 (en) 2001-01-16 2003-07-18 Canon Kk COMPUTER PROGRAM PARTITION METHOD AND DEVICE
AU2002243655A1 (en) 2001-01-25 2002-08-06 Improv Systems, Inc. Compiler for multiple processor and distributed memory architectures
FR2820526B1 (en) 2001-02-05 2003-06-13 Thomson Csf METHOD FOR SIMULATING PERFORMANCE, AND METHOD FOR MAKING MULTIPROCESSOR APPLICATIONS, AND DEVICES FOR IMPLEMENTING SAID METHODS
DE102010028896A1 (en) * 2010-05-11 2011-11-17 Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. Method and device for assigning a plurality of subtasks of a task to a plurality of arithmetic units of a given processor architecture

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5418953A (en) * 1993-04-12 1995-05-23 Loral/Rohm Mil-Spec Corp. Method for automated deployment of a software program onto a multi-processor architecture
FR2732787B1 (en) * 1995-04-07 1997-05-16 Thomson Csf METHOD OF GRAPHIC INPUT OF SIGNAL PROCESSING APPLICATION

Also Published As

Publication number Publication date
EP1082656A1 (en) 2001-03-14
FR2791789B1 (en) 2001-08-10
WO2000060460A1 (en) 2000-10-12
FR2791789A1 (en) 2000-10-06

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Legal Events

Date Code Title Description
MK6 Application lapsed section 142(2)(f)/reg. 8.3(3) - pct applic. not entering national phase