AU3182101A - Packet reception device - Google Patents

Packet reception device

Info

Publication number
AU3182101A
AU3182101A AU31821/01A AU3182101A AU3182101A AU 3182101 A AU3182101 A AU 3182101A AU 31821/01 A AU31821/01 A AU 31821/01A AU 3182101 A AU3182101 A AU 3182101A AU 3182101 A AU3182101 A AU 3182101A
Authority
AU
Australia
Prior art keywords
samples
work queue
signal
packets
real time
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
AU31821/01A
Inventor
Maurice Lemoine
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
EADS Defence and Security Networks SAS
Original Assignee
Matra Nortel Communications SAS
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matra Nortel Communications SAS filed Critical Matra Nortel Communications SAS
Publication of AU3182101A publication Critical patent/AU3182101A/en
Abandoned legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/64—Hybrid switching systems
    • H04L12/6418—Hybrid transport
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements
    • H04J3/062—Synchronisation of signals having the same nominal but fluctuating bit rates, e.g. using buffers
    • H04J3/0632—Synchronisation of packets and cells, e.g. transmission of voice via a packet network, circuit emulation service [CES]
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/64—Hybrid switching systems
    • H04L12/6418—Hybrid transport
    • H04L2012/6472—Internet
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/64—Hybrid switching systems
    • H04L12/6418—Hybrid transport
    • H04L2012/6481—Speech, voice
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/64—Hybrid switching systems
    • H04L12/6418—Hybrid transport
    • H04L2012/6489—Buffer Management, Threshold setting, Scheduling, Shaping

Abstract

The packets received contain each encoding data of a real time signal and an information dating the packet associated with a clock sampling the signal. The reception device comprises an interface (8) recording a work queue of signal samples obtained from the received packets asynchronously, scheduled in accordance with dating data contained in the packets, means for transferring samples (12) forming, at the local clock rhythm, a flow of synchronous samples ( phi ') representing the real time signal, successively transferred from the work queue, and regulating means (10) controlling the transfer means so as to limit variations in the number of samples in the work queue, by inserting or eliminating individual samples or small groups of samples in the work queue depending on the evolution of the number of recorded samples during periods defined relative to the local clock.
AU31821/01A 2000-01-03 2001-01-02 Packet reception device Abandoned AU3182101A (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
FR0000016A FR2803466B1 (en) 2000-01-03 2000-01-03 PACKET RECEIVING DEVICE
FR0000016 2000-01-03
PCT/FR2001/000003 WO2001050692A1 (en) 2000-01-03 2001-01-02 Packet reception device

Publications (1)

Publication Number Publication Date
AU3182101A true AU3182101A (en) 2001-07-16

Family

ID=8845579

Family Applications (1)

Application Number Title Priority Date Filing Date
AU31821/01A Abandoned AU3182101A (en) 2000-01-03 2001-01-02 Packet reception device

Country Status (7)

Country Link
EP (1) EP1245099B1 (en)
AT (1) ATE284106T1 (en)
AU (1) AU3182101A (en)
DE (1) DE60107533T2 (en)
ES (1) ES2233603T3 (en)
FR (1) FR2803466B1 (en)
WO (1) WO2001050692A1 (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10201310A1 (en) * 2002-01-15 2003-07-24 Siemens Ag Method for converting data from data transmission based on data packets to data transmission synchronized in time slots stores data packets in a conversion buffer memory.
ATE547903T1 (en) * 2008-05-30 2012-03-15 Oticon As QUALITY CONNECTION FOR LOW LATENCY SOUND TRANSMISSION

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5623483A (en) * 1995-05-11 1997-04-22 Lucent Technologies Inc. Synchronization system for networked multimedia streams
US5699481A (en) * 1995-05-18 1997-12-16 Rockwell International Corporation Timing recovery scheme for packet speech in multiplexing environment of voice with data applications

Also Published As

Publication number Publication date
ATE284106T1 (en) 2004-12-15
ES2233603T3 (en) 2005-06-16
FR2803466B1 (en) 2003-07-04
DE60107533D1 (en) 2005-01-05
DE60107533T2 (en) 2005-12-15
EP1245099A1 (en) 2002-10-02
FR2803466A1 (en) 2001-07-06
EP1245099B1 (en) 2004-12-01
WO2001050692A1 (en) 2001-07-12

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Legal Events

Date Code Title Description
MK6 Application lapsed section 142(2)(f)/reg. 8.3(3) - pct applic. not entering national phase