AU2785189A - Memory controller as for a video signal processor - Google Patents

Memory controller as for a video signal processor

Info

Publication number
AU2785189A
AU2785189A AU27851/89A AU2785189A AU2785189A AU 2785189 A AU2785189 A AU 2785189A AU 27851/89 A AU27851/89 A AU 27851/89A AU 2785189 A AU2785189 A AU 2785189A AU 2785189 A AU2785189 A AU 2785189A
Authority
AU
Australia
Prior art keywords
video signal
signal processor
memory controller
controller
memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
AU27851/89A
Other versions
AU625151B2 (en
Inventor
Alfred Yuk-Fai Kwan
Allen Henry Simon
David Leroy Sprague
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Intel Corp
Original Assignee
Technology Inc 64
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US07/121,025 external-priority patent/US5088053A/en
Application filed by Technology Inc 64 filed Critical Technology Inc 64
Publication of AU2785189A publication Critical patent/AU2785189A/en
Application granted granted Critical
Publication of AU625151B2 publication Critical patent/AU625151B2/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/18—Handling requests for interconnection or transfer for access to memory bus based on priority control
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/50—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using predictive coding
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N5/00—Details of television systems
    • H04N5/76—Television signal recording
    • H04N5/907—Television signal recording using static stores, e.g. storage tubes or semiconductor memories
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N7/00—Television systems
    • H04N7/24—Systems for the transmission of television signals using pulse code modulation

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Image Processing (AREA)
AU27851/89A 1987-11-16 1988-11-03 Memory controller as for a video signal processor Ceased AU625151B2 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US121025 1987-11-16
US07/121,025 US5088053A (en) 1987-11-16 1987-11-16 Memory controller as for a video signal processor
PCT/US1988/003814 WO1989005012A1 (en) 1987-11-16 1988-11-03 Memory controller as for a video signal processor

Publications (2)

Publication Number Publication Date
AU2785189A true AU2785189A (en) 1989-06-14
AU625151B2 AU625151B2 (en) 1992-07-02

Family

ID=26777974

Family Applications (1)

Application Number Title Priority Date Filing Date
AU27851/89A Ceased AU625151B2 (en) 1987-11-16 1988-11-03 Memory controller as for a video signal processor

Country Status (1)

Country Link
AU (1) AU625151B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112069809A (en) * 2020-08-11 2020-12-11 桂林电子科技大学 Missing text generation method and system

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3665412A (en) * 1970-07-20 1972-05-23 Informalique Comp Int Numerical data multi-processor system

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112069809A (en) * 2020-08-11 2020-12-11 桂林电子科技大学 Missing text generation method and system
CN112069809B (en) * 2020-08-11 2022-05-24 桂林电子科技大学 Missing text generation method and system

Also Published As

Publication number Publication date
AU625151B2 (en) 1992-07-02

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