AU2067295A - Surface treatment process for flat silicon bodies - Google Patents

Surface treatment process for flat silicon bodies

Info

Publication number
AU2067295A
AU2067295A AU20672/95A AU2067295A AU2067295A AU 2067295 A AU2067295 A AU 2067295A AU 20672/95 A AU20672/95 A AU 20672/95A AU 2067295 A AU2067295 A AU 2067295A AU 2067295 A AU2067295 A AU 2067295A
Authority
AU
Australia
Prior art keywords
surface treatment
treatment process
flat silicon
silicon bodies
bodies
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
AU20672/95A
Inventor
Mohammed Aggour
Helmut Jungblut
Hans-Joachim Lewerenz
Jorg Rappich
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hahn Meitner Institut Berlin GmbH
Original Assignee
Hahn Meitner Institut Berlin GmbH
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hahn Meitner Institut Berlin GmbH filed Critical Hahn Meitner Institut Berlin GmbH
Publication of AU2067295A publication Critical patent/AU2067295A/en
Abandoned legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/3063—Electrolytic etching
    • C—CHEMISTRY; METALLURGY
    • C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25F—PROCESSES FOR THE ELECTROLYTIC REMOVAL OF MATERIALS FROM OBJECTS; APPARATUS THEREFOR
    • C25F3/00—Electrolytic etching or polishing
    • C25F3/16—Polishing
    • C25F3/30—Polishing of semiconducting materials

Landscapes

  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Electrochemistry (AREA)
  • Materials Engineering (AREA)
  • Metallurgy (AREA)
  • Organic Chemistry (AREA)
  • Weting (AREA)
AU20672/95A 1994-03-17 1995-03-17 Surface treatment process for flat silicon bodies Abandoned AU2067295A (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
DE4409679 1994-03-17
DE4409679 1994-03-17
PCT/DE1995/000391 WO1995025186A1 (en) 1994-03-17 1995-03-17 Surface treatment process for flat silicon bodies

Publications (1)

Publication Number Publication Date
AU2067295A true AU2067295A (en) 1995-10-03

Family

ID=6513404

Family Applications (1)

Application Number Title Priority Date Filing Date
AU20672/95A Abandoned AU2067295A (en) 1994-03-17 1995-03-17 Surface treatment process for flat silicon bodies

Country Status (3)

Country Link
AU (1) AU2067295A (en)
DE (1) DE19510852C2 (en)
WO (1) WO1995025186A1 (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10256821B4 (en) * 2002-12-04 2005-04-14 Thomas Wolff Method and device for the photoelectrochemical etching of a semiconductor sample, in particular of gallium nitride
DE102005025123B4 (en) * 2005-05-30 2009-04-16 Sulfurcell Solartechnik Gmbh Process and device for the wet-chemical treatment of large-area substrates, in particular for the production of solar cells
DE102010049587A1 (en) * 2010-10-26 2012-04-26 Evonik Degussa Gmbh Process for the electrochemical hydrogen passivation of semiconductor layers

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US2871174A (en) * 1957-04-25 1959-01-27 Bell Telephone Labor Inc Method for electropolishing semiconducting material
DE1446067A1 (en) * 1962-04-27 1969-01-23 Telefunken Patent Process for polishing semiconductor wafers with simultaneous application of an electrolytic and a mechanical treatment
DE4031676A1 (en) * 1990-10-04 1992-04-09 Hahn Meitner Kernforsch Surface treatment of silicon@ wafer by electrochemical etching in dark - includes monitoring of etching progress to produce reproducible surface conditions for subsequent applications
DE4033355C2 (en) * 1990-10-19 1999-08-26 Siemens Ag Process for the electrolytic etching of silicon carbide

Also Published As

Publication number Publication date
DE19510852A1 (en) 1995-09-21
WO1995025186A1 (en) 1995-09-21
DE19510852C2 (en) 2003-05-08

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