AU2021103000A4 - A process for fabricating a multi-layered ceramic capacitor - Google Patents

A process for fabricating a multi-layered ceramic capacitor Download PDF

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AU2021103000A4
AU2021103000A4 AU2021103000A AU2021103000A AU2021103000A4 AU 2021103000 A4 AU2021103000 A4 AU 2021103000A4 AU 2021103000 A AU2021103000 A AU 2021103000A AU 2021103000 A AU2021103000 A AU 2021103000A AU 2021103000 A4 AU2021103000 A4 AU 2021103000A4
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layer
thickness
copper substrate
range
nickel
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Amanuel Abebe
Tadesse Hailu Ayane
Ruthramurthy Balachandran
Gemechu Dengia Debela
H. C. Ananda Murthy
Aschalew Tadesse
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Balachandran Ruthramurthy Dr
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Balachandran Ruthramurthy Dr
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Abstract

A PROCESS FOR FABRICATING A MULTI-LAYERED CERAMIC CAPACITOR The present invention relates to a multi-layered ceramic capacitor and a 5 process for fabricating the same. The process includes providing a first layer (102) having a thickness of 1000 pm and consisting of a copper substrate, pulse electrodepositing a second layer (104), having a thickness of 250 nm and consisting of nickel-iron alloy on said first layer (102), said nickel-iron alloy having nickel in the range of 80 wt. %, and iron in the range of 20 wt. 10 %, depositing a third layer (106), having a thickness of665 nm, and consisting of ZrO2 doped Bao.Sro.TiO3, by pulsed laser deposition process on said second layer (104), and depositing a fourth layer (108), having a thickness of 100 nm, and consisting of platinum, on said third layer (106). The capacitor has a dielectric constant of 700, a dielectric loss of 0.03, and a leakage current 15 density of 30 nA/cm2 . 1/1 100 106F 108 104u 106 102u 104 102 FIG. 1

Description

1/1
100
106F 108 104u 106
102u 104
102
FIG. 1
TITLE A PROCESS FOR FABRICATING A MULTI-LAYERED CERAMIC CAPACITOR FIELD OF THE INVENTION
The present invention relates to the field of capacitors, and in particular the
present invention relates to a multi-layered ceramic capacitor and a process
for fabricating the multi-layered ceramic capacitor.
BACKGROUND OF THE INVENTION
The electronic industry is witnessing a shrinkage of electronic components
at a very fast pace and with time is rapidly reaching the quantum limits. The
size reduction allows for manufacturing of electronic components (for
example integrated circuits and the like) which are not only having small
dimensions, but also cheaper, and more power efficient.
With the advent of computers, used in numerous applications, demand for
high storage capacity in Dynamic Random-Access Memory (DRAM) is
increasing. Here too, the DRAM size is being reduced with time.
Also, the thickness of corresponding constituent components is noted.
Particularly, the material within the capacitor component of DRAM is of
interest.
A typical storage capacitor of a DRAM cell is desired to have a low
minimum capacitance, which facilitates in achieving low bit line
capacitance and low leakage currents. A dielectric material which may be
employed in a DRAM capacitor should have a low leakage current so as to
ensure desired data retention time, and the dielectric must be able to
withstand the operating voltage.
Accordingly, there is a need for overcoming one or more drawbacks
associated with the prior art process.
OBJECTS OF THE INVENTION
Some of the objects of the presently disclosed invention, of which the
minimum one object is fulfilled by at least one embodiment disclosed herein
are as follows:
An object of the present invention is to provide an alternative, which
overcomes at least one drawback encountered in the existing prior art;
Another object of the present invention is to provide a multi-layered ceramic
capacitor;
Still another object of the present invention is to provide a process for
fabricating a multi-layered ceramic capacitor; and
Yet another object of the present invention is to provide a multi-layered
ceramic capacitor and a process for fabricating the same, wherein the
capacitor has a high dielectric constant, low dielectric loss, and low leakage
current.
Other objects and benefits of the present invention will be more apparent
from the following description which is not intended to bind the scope of the
present invention.
SUMMARY OF THE INVENTION
The present invention relates a multi-layered ceramic capacitor and a
process for fabricating the multi-layered ceramic capacitor.
In accordance with one aspect of the present invention, a multi-layered
ceramic capacitor is disclosed. The multi-layered ceramic capacitor
comprising a first layer consisting of copper having a thickness of 1000 im,
a second layer consisting of nickel-iron alloy having a thickness of 250 nm,
the second layer being deposited on an operative upper surface of said first
layer, a third layer consisting of ZrO2 doped Bao. 5 Sro.5 TiO3 having a
thickness of 665 nm deposited on to an operative upper surface of said
second layer, and a fourth layer consisting of platinum having a thickness in
the range of 100 nm. The multi-layered ceramic capacitor has a dielectric
constant of 700, a dielectric loss of 0.03 at a frequency of 1 kHz, and a
leakage current density of 30 nA/cm2 for a voltage of 5 V.
In accordance with another aspect of the present invention, a process for
fabricating the multi-layered ceramic capacitor is disclosed. The process for
fabricating the multi-layered ceramic capacitor includes the steps of
providing a first layer comprising a copper substrate having a thickness in
the range of 800 pm to 1200 im. Further, in the next step, a second layer is
deposited on to an upper surface of the first layer. The second layer is
deposited by a pulse electrodeposition process. The second layer has a
thickness in the range of 220 nm to 280 nm and comprises nickel-iron alloy.
The nickel-iron alloy having nickel in the range of 75 wt. % to 85 wt.00,
and iron in the range of 15 wt. % to 25 wt. %.
In the next step, a third layer comprising a ceramic of ZrO2 doped
Bao.Sro.TiO3 is deposited on to an upper surface of the second layer. The
third layer has a thickness in the range of 620 nm to 680 nm. The third layer
is deposited by using a pulsed laser deposition process.
Finally, a fourth layer is deposited on to an upper surface of the third layer.
The fourth layer has a thickness in the range of 80 nm to 120 nm. The fourth
layer comprises platinum.
In accordance with one embodiment of the present invention, the first layer
or the copper substrate is pre-treated before electrodeposition of the second
layer thereon. The process of pre-treating the copper substrate includes the
steps of cleaning said copper substrate with acetone to obtain a cleaned copper substrate, etching said cleaned copper substrate with nitric acid and deionized water to obtain an etched copper substrate, cleaning said etched copper substrate with water to remove nitric acid to obtained a washed copper substrate, rinsing said washed copper substrate with deionized water to obtain rinsed copper substrate, cleaning the area to be pulse electrodeposited with orthophosphoric acid to obtain a copper substrate with cleaned area, and drying said cleaned area in an ambient atmosphere to obtain said copper substrate with dried area.
In accordance with one embodiment of the present invention, the step of
pulse electrodepositing said second layer includes the following steps of
preparing a solution consisting of nickel sulphate, boric acid, and iron
sulphate in a proportion of 4.8:1:2.2, stirring said solution for a time period
in the range of 300 seconds to 900 seconds to obtain a stirred solution, and
pulse electrodepositing said stirred solution on to said dried area of said
copper substrate under ultrasonic treatment to obtain a nickel-iron alloy
layer deposited copper substrate thereon.
In accordance with one embodiment of the present invention, the step of
pulse laser depositing said third layer includes the sub-steps of providing a
deposition chamber, wherein said nickel-iron alloy layer deposited copper
substrate is placed within said deposition chamber, evacuating said
deposition chamber to a pressure of about 5 micro-Torr, and introducing nitrogen gas within said deposition chamber to a pressure of about 10 m
Torr, heating said nickel-iron alloy layer deposited copper substrate to a
temperature in the range of 240 °C to 260 °C to obtain a heated substrate,
depositing Bao.sSro.sTiO3by laser ablation on said heated substrate to obtain
a deposited substrate, cutting said deposited substrate into small pieces, and
annealing said small pieces in air at a temperature in the range of 640 °C to
810 °C for 90 minutes to 150 minutes to obtain an annealed substrate.
In accordance with one embodiment of the present invention, the ZrO2
doped Bao.Sro.TiO3 is synthesized by sol-gel process. The sol-gel process
includes the steps of blending 2 wt. % of zirconium acetate with barium
acetate, strontium acetate, and titanium isopropoxide in a proportion 1:1:2
along with acetic acid and ethylene glycol to obtain a blend thereof,
calcining said blend at a temperature of 800 °C for a time period of 5 hours
to obtain a calcined product, sintering said calcined product at a temperature
of 1300 °C for a time period of 6 hours to obtain a sintered product, and
pulverizing said sintered product to obtain ZrO2 doped barium strontium
titanate (ZrO2dopedBao.5Sro.5 TiO3).
In accordance with one embodiment of the present invention, the fourth
layer consisting of platinum is deposited by thermal evaporation process.
BRIEF DESCRIPTION OF THE ACCOMPANYING DRAWING
The present invention will now be described with the help of the
accompanying drawing, in which
FIG. 1 illustrates a schematic cross-sectional view of a multi-layered
ceramic capacitor in accordance with the embodiments of the present
invention.
LIST OF NUMERALS
The following is the list of numerals and their meaning as used in the
present specification.
100 - Multi-layered ceramic capacitor
102 - First layer (copper substrate)
102u - Operative upper surface of the first layer
104 - Second layer (nickel-iron alloy)
104u - Operative upper surface of the second layer
106 - Third layer (ZrO2 doped Barium strontium titanate)
106u - Operative upper surface of the third layer
108 - Fourth layer (platinum)
DETAILED DESCRIPTION
All the terms and expressions, which may be technical, scientific, or
otherwise, as used in the present invention have the same meaning as
understood by a person having ordinary skill in the art to which the present
invention belongs, unless and otherwise explicitly specified.
In the present specification, and the claims, the articles "a", "an", and "the"
include plural references unless the context clearly dictates otherwise.
The term "comprising" as used in the present specification and the claims
will be understood to mean that the list following is non-exhaustive and may
or may not include any other extra suitable features or elements or steps or
constituents as applicable.
Further, the terms "about" or "approximately" used in combination with
ranges relating to sizes of parts, or any other physical properties or
characteristics, are meant to include small variations that may occur in the
upper and/or lower limits of the ranges of the sizes.
The present invention discloses a multi-layered ceramic capacitor and a
process for fabricating the multi-layered ceramic capacitor.
FIG. 1 illustrates a schematic cross-sectional view of a multi-layered
ceramic capacitor in accordance with the embodiments of the present
invention.
In accordance with an aspect of the present invention, a multi-layered
ceramic capacitor (100) is disclosed, wherein the multi-layered ceramic
capacitor (100) is characterized by having a dielectric constant of 700, a
dielectric loss of 0.03 at a frequency of 1 kHz, and a leakage current density
of 30 nA/cm2 for a voltage of 5 V.
The multi-layered ceramic capacitor (100) comprises multiple layers. In
particular, the multi-layered ceramic capacitor (100) comprises a first layer
(102), a second layer (104), a third layer (106), and a fourth layer (108),
wherein the first layer (102) forms the base, the second layer (104) is
disposed on the first layer (102), the third layer (106) is disposed on the
second layer (104), and the fourth layer (108) is disposed on the third layer
(106).
In accordance with the present invention, the first layer (102) comprises
copper. Copper is used as the base layer of the multi-layered ceramic
capacitor as copper has excellent thermal and electric properties, which
enhances or improves the carrier collecting efficiency. Copper used herein is
99.99 % pure. In the present invention, copper foils (with 99.99 % purity)
are used, and are procured from Shoko, Japan.
In accordance with the present invention, the first layer (102) has a
thickness in the range of 800 pm to 1200 im. In accordance with one embodiment of the present invention, the first layer (102) has a thickness of
1000 im.
In accordance with the present invention, the second layer (104) comprises
nickel-iron alloy. The second layer (104) is disposed or deposited upon an
upper surface (102u) of the first layer (102). The nickel-iron alloy comprises
nickel in the range of 75 wt. % to 85 wt. %, and iron in the range of 15 wt.
% to 25 wt. %. In accordance with one embodiment of the present
invention, nickel is 80 wt. % whereas iron is 20 wt. %. Nickel-iron alloy is a
soft magnetic material, exhibits improved strength, and increased wear
resistance.
In accordance with the present invention, the second layer (104) has a
thickness in the range of 220 nm to 280 nm. In accordance with one
embodiment of the present invention, the second layer (104) has a thickness
of 250 nm.
In accordance with the present invention, the third layer (106) comprises
ZrO2 doped barium strontium titanate dielectric material. The third layer
(106) material which is ZrO2 doped barium strontium titanate dielectric
material has high dielectric constant (k). This is required to reduce the
effective oxide thickness (EOT) to increase the capacitance, wide band gap
to reduce the leakage current and high breakdown to ensure good reliability.
In particular, in accordance with the embodiment of the present invention,
ZrO2 doped Bao.Sro.TiO3is employed due to its high dielectric constant,
low dielectric loss, and low leakage current density. The third layer (106) is
disposed on an operative upper surface (104u) of the second layer (104).
In accordance with the present invention, the third layer (106) has a
thickness in the range of 620 nm to 680 nm. In accordance with one
embodiment of the present invention, the third layer (106) has a thickness of
665 nm.
In accordance with the present invention, the fourth layer (108) comprises
platinum. In accordance with the present invention, the fourth layer (108) is
deposited upon an operative upper surface (106u) of the third layer (106).
The fourth layer (108) has a thickness in the range of 80 nm to 120 nm. In
one embodiment of the present invention, the fourth layer (108) has a
thickness of 100 nm.
In accordance with another aspect of the present invention, a process for
fabricating the multi-layered ceramic capacitor (100) is disclosed. The
process for fabricating the multi-layered ceramic capacitor (100) includes
the following steps, which are described herein below in detail.
A copper foil with 99.99 % copper is provided, which serves as the first
layer (102) or the base layer for fabricating the multi-layered capacitor
(100). The copper foil or the copper substrate or the first layer (102) can have a thickness in the range of 800 pm to 1200 im. In one specific embodiment the thickness of the first layer is 1000 im.
In accordance with one embodiment of the present invention, the copper foil
or the first layer (102) is pre-treated before deposition of the second layer
(104). More specifically, the copper substrate is cleaned with acetone to
obtain a cleaned copper substrate. The cleaned copper substrate so obtained
is then etched by using an etchant. In accordance with one embodiment of
the present invention, the etchant can be nitric acid. The etched copper
substrate so obtained is then washed with deionized water to remove the
etched particles and nitric acid therefrom and obtain a washed copper
substrate. The washed copper substrate is further rinsed with deionized
water to obtain a rinsed copper substrate. Further, a peripheral area of the
copper substrate is tapped or covered with a suitable material. The
uncovered area is the portion over which the second layer (104) has to be
deposited or pulse electrodeposited. The uncovered area is cleaned with
orthophosphoric acid to obtain a copper substrate with cleaned uncovered
area. Finally, the cleaned uncovered area is dried in an ambient atmosphere
to obtain the copper substrate with dried area.
In accordance with the present invention, the second layer (104) is pulse
electrodeposited over the operative upper surface (102u) of first layer (102).
The second layer (104) has a thickness in the range of 220 nm to 280 nm and consists of nickel-iron alloy. In one embodiment the thickness of the second layer (104) is 250 nm. The nickel-iron alloy comprises nickel in the range of 75 wt. % to 85 wt. %, and iron in the range of 15 wt. % to 25 wt.
%. In one embodiment the amount of nickel is 80 wt. % and the amount of
iron is 20 wt. %.
In accordance with one embodiment of the present invention, the process of
pulse electrodeposition is carried out by the following sub-steps which are
described herein below in detail.
In the first step a solution consisting of nickel sulphate, boric acid, and iron
sulphate in a proportion of 4.8:1:2.2 is prepared, which is stirred for a time
period in the range of 300 seconds to 900 seconds to obtain a stirred
solution. The stirred solution is further pulse electrodeposited on to the dried
area of the copper substrate under ultrasonic treatment or without ultrasonic
treatment to obtain a nickel-iron alloy layer deposited copper substrate
thereon.
In accordance with the present invention, the third layer (106) is deposited
on to the operative upper surface (104u) by pulsed laser deposition process.
In one embodiment of the present invention, the thickness of the third layer
(106) is in the range of 620 nm to 680 nm. In one embodiment of the present
invention, the thickness of the third layer (106) is 665 nm. The third layer
(106) comprises ZrO2 doped Bao.5 Sro.TiO3 (referred to as ZBST herein
after).
In accordance with one embodiment of the present invention, ZBST is
synthesized by sol-gel process. The sol-gel process includes the steps of
blending 2 wt. % of zirconium acetate with barium acetate, strontium
acetate, and titanium isopropoxide in a proportion 1:1:2 along with acetic
acid and ethylene glycol to obtain a blend thereof, calcining said blend at a
temperature of 800 °C for a time period of 5 hours to obtain a calcined
product, sintering said calcined product at a temperature of 1300 °C for a
time period of 6 hours to obtain a sintered product, and pulverizing said
sintered product to obtain zirconium doped barium strontium titanate (ZrO2
doped Bao.5 Sro.5 TiO3).
In accordance with the embodiments of the present invention, the deposition
of the third layer (106) is carried out by the following sub-steps. Firstly, a
deposition chamber is provided, which is salable and can be evacuated
using a suitable evacuating apparatus. The nickel-iron alloy layer deposited
copper substrate is placed within the deposition chamber. The deposition
chamber is evacuated to a pressure of about 5 micro-Torr, and introducing
nitrogen gas within the deposition chamber to a pressure of about 10 m
Torr. The nickel-iron alloy layer deposited with a copper substrate is heated
to a temperature in the range of 240 °C to 260 °C to obtain a heated substrate. The deposition of ZBST is carried out by a laser ablation process, wherein the laser ablated ZBST is deposited on to the substrate. Further, the deposited substrates may be cut into small pieces depending upon the requirement, and are further annealed in air at a temperature in the range of
640 °C to 810 °C for 90 minutes to 150 minutes to obtain an annealed
substrate.
Further, the fourth layer (108) is deposited on to the upper operative surface
(106u) of the third layer (106) by thermal evaporation process. In
accordance with the present invention, the thickness of the fourth layer
(108) can be in the range of 80 nm to 120 nm, specifically, the fourth layer
can have thickness of 100 nm, and can be made of platinum.
TECHNICAL ADVANCES AND ADVANTAGES OF THE INVENTION
The presently disclosed invention, as described herein above, provides
several technical advances and advantages of which some are listed herein
below:
- the multi-layered ceramic capacitor has:
o high dielectric constant;
o low dielectric loss;
o reduced leakage current; and
- the process for fabricating the multi-layered ceramic capacitor is:
o simple; and
o economic.

Claims (5)

I claim:
1. A process for fabricating a multi-layered ceramic capacitor (100), said
process characterized by having the following steps:
- providing a first layer (102) having a thickness in the range of 800 pm
to 1200 pm and consisting of a copper substrate;
- pulse electrodepositing a second layer (104), having a thickness in the
range of 220 nm to 280 nm and consisting of nickel-iron alloy on to
an operative upper surface (102u) of said first layer (102), said nickel
iron alloy having nickel in the range of 75 wt. % to 85 wt. %, and iron
in the range of 15 wt. % to 25 wt. %;
- depositing a third layer (106), having a thickness in the range of 620
nm to 680 nm, and consisting of ZrO2 doped Bao.Sro.TiO3, by pulsed
laser deposition process on to an operative upper surface (104u) of
said second layer (104); and
- depositing a fourth layer (108), having a thickness in the range of 80
nm to 120 nm, and consisting of platinum, on to an operative upper
surface (106u) of said third layer (106);
wherein before the step of pulse electrodepositing said first layer (102)
consisting of said copper substrate is pre-treated, wherein said step of pre
treating said first layer (102) includes the following sub-steps:
- cleaning said copper substrate with acetone to obtain a cleaned copper
substrate;
- etching said cleaned copper substrate by nitric acid and deionized
water to obtain an etched copper substrate;
- cleaning said etched copper substrate with water to remove nitric acid
to obtained a washed copper substrate;
- rinsing said washed copper substrate with deionized water to obtain
rinsed copper substrate;
- cleaning the area to be pulse electrodeposited with orthophosphoric
acid to obtain a copper substrate with cleaned area; and
- drying said cleaned area in an ambient atmosphere to obtain said
copper substrate with dried area;
wherein said step of pulse electrodepositing said second layer (104)
includes the following steps:
- preparing a solution consisting of nickel sulphate, boric acid, and iron
sulphate in a proportion of 4.8:1:2.2;
- stirring said solution for a time period in the range of 300 seconds to
900 seconds to obtain a stirred solution; and
- pulse electrodepositing said stirred solution on to said dried area of
said copper substrate under ultrasonic treatment to obtain a nickel-iron
alloy layer deposited copper substrate thereon;
wherein said step of pulse laser depositing said third layer includes the
sub-steps of:
- providing a deposition chamber, wherein said nickel-iron alloy layer
deposited copper substrate is placed within said deposition chamber;
- evacuating said deposition chamber to a pressure of about 5 micro
Torr, and introducing nitrogen gas within said deposition chamber to
a pressure of about 10 m Torr;
- heating said nickel-iron alloy layer deposited copper substrate to a
temperature in the range of 240 °C to 260 °C to obtain a heated
substrate;
- depositing ZrO2 doped Bao.5Sro.TiO3 by laser ablation on said heated
substrate to obtain a deposited substrate;
- cutting said deposited substrate into small pieces; and
- annealing said small pieces in air at a temperature in the range of 640
°C to 810 °C for 90 minutes to 150 minutes to obtain an annealed
substrate; wherein said ZrO2 doped Bao.5 Sro. 5TiO3 is synthesized by sol-gel process, wherein the sol-gel process includes the steps of:
- blending 2 wt. % zirconium acetate with barium acetate, strontium
acetate, and titanium isopropoxide in a proportion 1:1:2 along with
acetic acid and ethylene glycol to obtain a blend thereof;
- calcining said blend at a temperature of 800 °C for a time period of 5
hours to obtain a calcined product;
- sintering said calcined product at a temperature of 1300 °C for a time
period of 6 hours to obtain a sintered product; and
- pulverizing said sintered product to obtain ZrO2 doped barium
strontium titanate (ZrO2 doped Bao.Sro.TiO3).
2. The process as claimed in claim 1, wherein said fourth layer consisting of
platinum is deposited by thermal evaporation process.
3. The process as claimed in claim 1, wherein said first layer is having a
thickness of 1000 im; and wherein said second layer is having a thickness
of 250 nm.
4. The process as claimed in claim 1, wherein said third layer is having a
thickness of 665 nm and said fourth layer is having a thickness of 100 nm.
5. A multi-layered ceramic capacitor (100) characterized by having:
- a first layer (102) consisting of copper having a thickness of 1000 im;
- a second layer (104) consisting of nickel-iron alloy having a thickness
of 250 nm, said second layer (104) deposited on an operative upper
surface (102u) of said first layer (102);
- a third layer (106) consisting of ZrO2 doped Bao.Sro.5 TiO3 having a
thickness of 665 nm deposited on to an operative upper surface (104u)
of said second layer (104); and
- a fourth layer (108) consisting of platinum having a thickness in the
range of 100 nm;
wherein said ceramic capacitor (100) having:
- a dielectric constant of 700;
- a dielectric loss of 0.03 at a frequency of1 KHz; and
- a leakage current density of 30 nA/cm2 for a voltage of 5 V.
AU2021103000A 2021-02-15 2021-05-31 A process for fabricating a multi-layered ceramic capacitor Ceased AU2021103000A4 (en)

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IN202121006341 2021-02-15

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